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Wade Fife cb04b641a3 x300: Expand DRAM address space to 1G 
The address ranges configured for the AXI interconnect IP limited the
amount of accessible DRAM to two 32 MB regions. This change makes the
full 1G available to all DRAM ports.


Original-commit: bba0cddfadcb744e8a6fae27d57ba8d3995eaf64
2020-05-18 17:50:38 -05:00
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aurora_64b66b_pcs_pma
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi4_dualport_sram
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi64_4k_2clk_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi64_8k_2clk_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_intercon_2x64_128_bd
x300: Expand DRAM address space to 1G
2020-05-18 17:50:38 -05:00
bootram
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
bus_clk_gen
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ddr3_32bit
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo_4k_2clk
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo_short_2clk
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
input_sample_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
one_gig_eth_pcs_pma
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
pcie_clk_gen
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
radio_clk_gen
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ten_gig_eth_pcs_pma
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.inc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00