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Wade Fife cb04b641a3 x300: Expand DRAM address space to 1G 
The address ranges configured for the AXI interconnect IP limited the
amount of accessible DRAM to two 32 MB regions. This change makes the
full 1G available to all DRAM ports.


Original-commit: bba0cddfadcb744e8a6fae27d57ba8d3995eaf64
2020-05-18 17:50:38 -05:00
..
b2xxmini
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
b200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x
fpga: e31x: Replace symbolic link for Cygwin
2020-05-12 13:47:20 -05:00
e320
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
python
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300
x300: Expand DRAM address space to 1G
2020-05-18 17:50:38 -05:00
Makefile.common
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00