5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
116 lines
4.7 KiB
Verilog
116 lines
4.7 KiB
Verilog
//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: adc_iq_repacker
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//
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// Description:
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//
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// This component repacks IQ from independent vectors into a single
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// output signal, and implements data swapping when requested.
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//
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// The parameters for this component describe the expected amount of
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// data to be received as well as the data to be generated.
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//
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// - SPC = Samples per cycle: amount of samples to be expected
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// on each I and Q input vector on each "clk" cycle.
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// - SAMPLE_WIDTH = Amount of bits composing each sample
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//
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// This modules incurs in two clk cycles of delay on the data and valid
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// signals from input to output.
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//
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// Example case : SPC = 2, SAMPLE_WIDTH = 16
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//
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// adc_x_in size(for I and Q) = 2 x 16 = 32
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// adc_out size = 2 x 2 x 16 = 64
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//
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// _______ _______ _______ ______
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// clk _| |_______| |_______| |_______|
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// _ _______________ _______________ _______________ ______
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// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______
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// _ _______________ _______________ _______________ ______
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// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______
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// _______________________________
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// valid_in _| |______________________
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// _ _______________ _______________ _______________ ______
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// adc_out _X____64{'X'}____X____64{'X'}____X__Q1,I1,Q0,I0__X__Q3,..
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// ______________________
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// valid_out _________________________________|
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//
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// When the swap input is high, the order in which Q and I samples
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// appear on the output vector is inverted
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//
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// _______ _______ _______ ______
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// clk _| |_______| |_______| |_______|
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// _ _______________ _______________ _______________ ______
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// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______
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// _ _______________ _______________ _______________ ______
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// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______
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// _______________________________
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// valid_in _| |______________________
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// _ _______________ _______________ _______________ ______
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// adc_out _X____64{'X'}____X____64{'X'}____X__I1,Q1,I0,Q0__X__I3,..
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// ______________________
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// valid_out _________________________________|
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//
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// Parameters:
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// SPC = Samples per cycle
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// SAMPLE_WIDTH = width of i/q sample inputs. Output will be 2*SAMPLE_WIDTH
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//
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module adc_iq_repacker #(
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parameter SPC = 1,
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parameter SAMPLE_WIDTH = 16
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)
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(
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input wire clk,
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// Data in
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input wire [SPC*SAMPLE_WIDTH-1:0] adc_q_in,
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input wire [SPC*SAMPLE_WIDTH-1:0] adc_i_in,
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input wire valid_in,
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// This signal is currently driven in a related clock, and even though it runs at half the rate is should be fine
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// to handle it in this clock domain(in nature it will also stay high one asserted until the next reset.)
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input wire enable,
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// Data is packed [Q,I] (I in LSBs) when swap_iq is '0', and [I,Q] otherwise
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input wire swap_iq,
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// Data out
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output reg [SPC*SAMPLE_WIDTH*2-1:0] data_out_tdata,
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output reg data_out_tvalid
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);
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localparam IQ_WIDTH = SAMPLE_WIDTH*2;
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reg valid = 1'b0, valid_dly = 1'b0;
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reg [SPC*SAMPLE_WIDTH-1:0] adc_q_data_in = {SPC*SAMPLE_WIDTH{1'b0}};
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reg [SPC*SAMPLE_WIDTH-1:0] adc_i_data_in = {SPC*SAMPLE_WIDTH{1'b0}};
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integer sample_num;
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// It is safe to not reset this domain because all of the input signals will be cleared
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// by a synchronous reset. Safe default values are assigned to all these registers.
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always @(posedge clk) begin
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adc_q_data_in <= adc_q_in;
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adc_i_data_in <= adc_i_in;
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// Place Q in the MSBs, I in the LSBs by default, unless swapped = 1.
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for (sample_num=0; sample_num < (SPC); sample_num = sample_num + 1)
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begin : data_out_gen
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if (swap_iq) begin
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data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <=
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{adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH],
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adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]};
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end else begin
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data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <=
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{adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH],
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adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]};
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end
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end
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// Valid is simply a transferred version of the 1x clock's valid. Delay it one
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// more cycle to align outputs.
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valid <= valid_in && enable;
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data_out_tvalid <= valid;
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end
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endmodule
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