161 lines
7.4 KiB
Verilog
161 lines
7.4 KiB
Verilog
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// Adapts from internal VITA to ethernet packets. Also handles ZPU and ethernet crossover interfaces.
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module eth_interface
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#(parameter BASE=0,
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parameter XO_FIFOSIZE=10,
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parameter ZPU_FIFOSIZE=10,
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parameter VITA_FIFOSIZE=10,
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parameter ETHOUT_FIFOSIZE=10)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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// Eth ports
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output [63:0] eth_tx_tdata, output [3:0] eth_tx_tuser, output eth_tx_tlast, output eth_tx_tvalid, input eth_tx_tready,
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input [63:0] eth_rx_tdata, input [3:0] eth_rx_tuser, input eth_rx_tlast, input eth_rx_tvalid, output eth_rx_tready,
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// Vita router interface
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output [63:0] e2v_tdata, output e2v_tlast, output e2v_tvalid, input e2v_tready,
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input [63:0] v2e_tdata, input v2e_tlast, input v2e_tvalid, output v2e_tready,
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// Ethernet crossover
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output [63:0] xo_tdata, output [3:0] xo_tuser, output xo_tlast, output xo_tvalid, input xo_tready,
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input [63:0] xi_tdata, input [3:0] xi_tuser, input xi_tlast, input xi_tvalid, output xi_tready,
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// ZPU
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output [63:0] e2z_tdata, output [3:0] e2z_tuser, output e2z_tlast, output e2z_tvalid, input e2z_tready,
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input [63:0] z2e_tdata, input [3:0] z2e_tuser, input z2e_tlast, input z2e_tvalid, output z2e_tready,
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// Debug
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output [31:0] debug_flags,
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output [31:0] debug
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);
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wire [63:0] v2ef_tdata;
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wire [3:0] v2ef_tuser;
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wire v2ef_tlast, v2ef_tvalid, v2ef_tready;
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// //////////////////////////////////////////////////////////////
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// Incoming Ethernet path
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// Includes FIFO on the output going to ZPU
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wire [63:0] epg_tdata_int;
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wire [3:0] epg_tuser_int;
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wire epg_tlast_int, epg_tvalid_int, epg_tready_int;
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//
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// Packet gate ensures on entire ingressing packet is buffered before feeding it downstream so that it bursts
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// efficiently internally without holding resources allocted for longer than optimal. This also means that an upstream
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// error discovered in the packet can allow the packet to be destroyed here, before it gets deeper into the USRP.
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//
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axi_packet_gate #(.WIDTH(68), .SIZE(10)) packet_gater //holds 8K pkts
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({eth_rx_tuser, eth_rx_tdata}), .i_tlast(eth_rx_tlast),
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.i_terror(eth_rx_tuser[3]), //top bit of user bus is error
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.i_tvalid(eth_rx_tvalid), .i_tready(eth_rx_tready),
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.o_tdata({epg_tuser_int, epg_tdata_int}), .o_tlast(epg_tlast_int),
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.o_tvalid(epg_tvalid_int), .o_tready(epg_tready_int));
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//
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// Based on programmed rules, parse network headers and decide which internal destination(s) this packet will be forwarded to.
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//
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wire [63:0] e2z_tdata_int;
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wire [3:0] e2z_tuser_int;
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wire e2z_tlast_int, e2z_tvalid_int, e2z_tready_int;
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wire [2:0] dispatch_debug_flags;
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eth_dispatch #(.BASE(BASE+8)) eth_dispatch
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(.clk(clk), .reset(reset), .clear(clear),
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.set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
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.in_tdata(epg_tdata_int), .in_tuser(epg_tuser_int), .in_tlast(epg_tlast_int), .in_tvalid(epg_tvalid_int), .in_tready(epg_tready_int),
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.vita_tdata(e2v_tdata), .vita_tlast(e2v_tlast), .vita_tvalid(e2v_tvalid), .vita_tready(e2v_tready),
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.zpu_tdata(e2z_tdata_int), .zpu_tuser(e2z_tuser_int), .zpu_tlast(e2z_tlast_int), .zpu_tvalid(e2z_tvalid_int), .zpu_tready(e2z_tready_int),
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.xo_tdata(xo_tdata), .xo_tuser(xo_tuser), .xo_tlast(xo_tlast), .xo_tvalid(xo_tvalid), .xo_tready(xo_tready), // to other eth port
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.debug_flags(dispatch_debug_flags),.debug(debug));
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//
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// ZPU can be slow to respond (relative to packet wirespeed) so extra buffer for packets destined there so it doesn't back up.
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//
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axi_fifo #(.WIDTH(69),.SIZE(ZPU_FIFOSIZE)) zpu_fifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({e2z_tlast_int,e2z_tuser_int,e2z_tdata_int}), .i_tvalid(e2z_tvalid_int), .i_tready(e2z_tready_int),
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.o_tdata({e2z_tlast,e2z_tuser,e2z_tdata}), .o_tvalid(e2z_tvalid), .o_tready(e2z_tready));
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// //////////////////////////////////////////////////////////////
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// Outgoing Ethernet path
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// Includes FIFOs on path from VITA router, from ethernet crossover, and on the overall output
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wire [63:0] eth_tx_tdata_int;
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wire [3:0] eth_tx_tuser_int;
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wire eth_tx_tlast_int, eth_tx_tvalid_int, eth_tx_tready_int;
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wire [63:0] xi_tdata_int;
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wire [3:0] xi_tuser_int;
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wire xi_tlast_int, xi_tvalid_int, xi_tready_int;
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wire [63:0] v2e_tdata_int;
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wire v2e_tlast_int, v2e_tvalid_int, v2e_tready_int;
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axi_fifo #(.WIDTH(65),.SIZE(VITA_FIFOSIZE)) vitaout_fifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({v2e_tlast,v2e_tdata}), .i_tvalid(v2e_tvalid), .i_tready(v2e_tready),
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.o_tdata({v2e_tlast_int,v2e_tdata_int}), .o_tvalid(v2e_tvalid_int), .o_tready(v2e_tready_int));
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chdr_eth_framer #(.BASE(BASE)) my_eth_framer
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(.clk(clk), .reset(reset), .clear(clear),
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.set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
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.in_tdata(v2e_tdata_int), .in_tlast(v2e_tlast_int), .in_tvalid(v2e_tvalid_int), .in_tready(v2e_tready_int),
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.out_tdata(v2ef_tdata), .out_tuser(v2ef_tuser), .out_tlast(v2ef_tlast), .out_tvalid(v2ef_tvalid), .out_tready(v2ef_tready),
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.debug());
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axi_fifo #(.WIDTH(69),.SIZE(XO_FIFOSIZE)) xo_fifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({xi_tlast,xi_tuser,xi_tdata}), .i_tvalid(xi_tvalid), .i_tready(xi_tready),
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.o_tdata({xi_tlast_int,xi_tuser_int,xi_tdata_int}), .o_tvalid(xi_tvalid_int), .o_tready(xi_tready_int));
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axi_mux4 #(.PRIO(0), .WIDTH(68)) eth_mux
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(.clk(clk), .reset(reset), .clear(clear),
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.i0_tdata({z2e_tuser,z2e_tdata}), .i0_tlast(z2e_tlast), .i0_tvalid(z2e_tvalid), .i0_tready(z2e_tready),
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.i1_tdata({v2ef_tuser,v2ef_tdata}), .i1_tlast(v2ef_tlast), .i1_tvalid(v2ef_tvalid), .i1_tready(v2ef_tready),
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.i2_tdata({xi_tuser_int,xi_tdata_int}), .i2_tlast(xi_tlast_int), .i2_tvalid(xi_tvalid_int), .i2_tready(xi_tready_int),
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.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
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.o_tdata({eth_tx_tuser_int,eth_tx_tdata_int}), .o_tlast(eth_tx_tlast_int), .o_tvalid(eth_tx_tvalid_int), .o_tready(eth_tx_tready_int));
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axi_fifo #(.WIDTH(69),.SIZE(ETHOUT_FIFOSIZE)) ethout_fifo
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({eth_tx_tlast_int,eth_tx_tuser_int,eth_tx_tdata_int}), .i_tvalid(eth_tx_tvalid_int), .i_tready(eth_tx_tready_int),
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.o_tdata({eth_tx_tlast,eth_tx_tuser,eth_tx_tdata}), .o_tvalid(eth_tx_tvalid), .o_tready(eth_tx_tready));
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//
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// Provide instrumentation so that abnormal FIFO conditions can be identifed.
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//
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/* -----\/----- EXCLUDED -----\/-----
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setting_reg #(.my_addr(BASE+15), .awidth(16), .width(1)) sr_reset_fifo_debug
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(),.changed(clear_debug_flags));
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always @(posedge clk)
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if (reset)
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debug_flags <= 0;
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else if (clear_debug_flags)
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debug_flags <= 0;
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else
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debug_flags <= debug_flags | {eth_rx_tuser[3],
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~eth_tx_tready_int,
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~xi_tready,
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~v2e_tready,
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~e2z_tready_int,
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~eth_rx_tready,
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~dispatch_debug_flags[2:0]};
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-----/\----- EXCLUDED -----/\----- */
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assign debug_flags = {eth_rx_tuser[3],
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~eth_tx_tready_int,
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~xi_tready,
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~v2e_tready,
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~e2z_tready_int,
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~eth_rx_tready,
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~dispatch_debug_flags[2:0]};
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endmodule // eth_interface
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