5a525c84f57a63412914a40082e885af0f5c7791
Original-commit: 00711ba213dde8aa0a099d2b18d3da0a33e6af79
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%