61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
234 lines
10 KiB
VHDL
234 lines
10 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: dac_gearbox_12x8
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--
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-- Description:
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--
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-- Gearbox to expand the data width from 12 SPC to 8 SPC.
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-- Input Clocks, all aligned to one another and coming from same MMCM.
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-- PLL reference clock = 61.44 or 62.5 MHz.
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-- RfClk: 184.32 or 187.5 MHz (3x PLL reference clock)
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-- Clk1x: 122.88 or 125 MHz (2x PLL reference clock)
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-- Clk2x: 245.76 or 250 MHz (4x PLL reference clock)
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity dac_gearbox_12x8 is
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port(
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Clk1x : in std_logic;
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RfClk : in std_logic;
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ac1Reset_n : in std_logic;
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arReset_n : in std_logic;
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-- Data packing: [Q11,I11,Q10,I10,...,Q3,I3,Q2,I2,Q1,I1,Q0,I0] (I in LSBs)
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c1DataIn : in std_logic_vector(383 downto 0);
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c1DataValidIn : in std_logic;
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-- Data packing: [Q7,I7,Q6,I6,...,Q3,I3,Q2,I2,Q1,I1,Q0,I0] (I in LSBs)
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rDataOut : out std_logic_vector(255 downto 0) := (others => '0');
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rReadyForOutput : in std_logic;
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rDataValidOut : out std_logic
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);
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end dac_gearbox_12x8;
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architecture RTL of dac_gearbox_12x8 is
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constant kDataWidth : natural := 16;
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constant kDataI0Lsb : natural := 0;
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constant kDataI0Msb : natural := kDataWidth-1;
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constant kDataQ0Lsb : natural := kDataI0Msb+1;
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constant kDataQ0Msb : natural := kDataQ0Lsb+kDataWidth-1;
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constant kDataI1Lsb : natural := kDataQ0Msb+1;
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constant kDataI1Msb : natural := kDataI1Lsb+kDataWidth-1;
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constant kDataQ1Lsb : natural := kDataI1Msb+1;
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constant kDataQ1Msb : natural := kDataQ1Lsb+kDataWidth-1;
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constant kDataI2Lsb : natural := kDataQ1Msb+1;
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constant kDataI2Msb : natural := kDataI2Lsb+kDataWidth-1;
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constant kDataQ2Lsb : natural := kDataI2Msb+1;
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constant kDataQ2Msb : natural := kDataQ2Lsb+kDataWidth-1;
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constant kDataI3Lsb : natural := kDataQ2Msb+1;
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constant kDataI3Msb : natural := kDataI3Lsb+kDataWidth-1;
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constant kDataQ3Lsb : natural := kDataI3Msb+1;
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constant kDataQ3Msb : natural := kDataQ3Lsb+kDataWidth-1;
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constant kDataI4Lsb : natural := kDataQ3Msb+1;
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constant kDataI4Msb : natural := kDataI4Lsb+kDataWidth-1;
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constant kDataQ4Lsb : natural := kDataI4Msb+1;
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constant kDataQ4Msb : natural := kDataQ4Lsb+kDataWidth-1;
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constant kDataI5Lsb : natural := kDataQ4Msb+1;
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constant kDataI5Msb : natural := kDataI5Lsb+kDataWidth-1;
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constant kDataQ5Lsb : natural := kDataI5Msb+1;
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constant kDataQ5Msb : natural := kDataQ5Lsb+kDataWidth-1;
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constant kDataI6Lsb : natural := kDataQ5Msb+1;
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constant kDataI6Msb : natural := kDataI6Lsb+kDataWidth-1;
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constant kDataQ6Lsb : natural := kDataI6Msb+1;
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constant kDataQ6Msb : natural := kDataQ6Lsb+kDataWidth-1;
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constant kDataI7Lsb : natural := kDataQ6Msb+1;
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constant kDataI7Msb : natural := kDataI7Lsb+kDataWidth-1;
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constant kDataQ7Lsb : natural := kDataI7Msb+1;
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constant kDataQ7Msb : natural := kDataQ7Lsb+kDataWidth-1;
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subtype Word_t is std_logic_vector(383 downto 0);
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type Words_t is array(natural range<>) of Word_t;
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signal rDataInDly : Words_t(3 downto 0);
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signal rDataValidDly : std_logic_vector(3 downto 0) := (others => '0');
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signal c1PhaseCount, c1DataValidInDly : std_logic := '0';
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signal rPhaseShiftReg : std_logic_vector(2 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Data Packing 12 SPC to 8 SPC
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-----------------------------------------------------------------------------
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Clk1xDataCount: process(ac1Reset_n, Clk1x)
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begin
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if ac1Reset_n = '0' then
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c1PhaseCount <= '0';
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c1DataValidInDly <= '0';
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elsif rising_edge(Clk1x) then
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c1DataValidInDly <= c1DataValidIn;
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c1PhaseCount <= (not c1PhaseCount) and (c1DataValidIn or c1DataValidInDly);
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end if;
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end process;
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DataClkCrossing: process(RfClk)
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begin
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if rising_edge(RfClk) then
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rDataInDly <= rDataInDly(rDataInDly'high-1 downto 0) & c1DataIn;
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end if;
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end process;
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-- Store clock phase information in a shift register. The shift register
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-- is a 3 bit register and it used in output data packer.
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PhaseClkCrossing: process(arReset_n,RfClk)
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begin
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if arReset_n = '0' then
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rPhaseShiftReg <= (others => '0');
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elsif rising_edge(RfClk) then
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rPhaseShiftReg(2 downto 1) <= rPhaseShiftReg(1 downto 0);
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rPhaseShiftReg(0) <= c1PhaseCount;
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end if;
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end process;
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-----------------------------------------------------------------------------
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--
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-- Timing diagram: Data valid is asserted when both clock are edge aligned.
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--
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-- | | |
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-- v <-Clocks edge aligned v v
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-- Clk1x ¯¯\____/¯¯¯¯¯\_____/¯¯¯¯¯\_____/¯¯¯¯¯\_____/¯¯¯¯¯\_____/¯¯¯¯¯\___
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-- |
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-- v <- O/p data valid assertion
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-- RfClk ¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯
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-- | | |
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-- c1DataValid _/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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-- | | |
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-- c1DValidDly _________/¯¯¯¯¯¯¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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-- | | |
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-- c1PhaseCount _______/¯¯¯¯¯¯¯¯¯¯¯¯\|_______|__/¯¯¯¯|¯¯¯¯¯¯¯\__________/¯¯
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-- | | |
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-- v <- rPhaseSR= "001"
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-- rPhaseSR(0) ________________/¯¯¯¯¯¯¯¯\_____|_______|_/¯¯¯¯¯¯¯\_________________
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-- | |
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-- v <- rPhaseSR= "010"
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-- rPhaseSR(1) _________________________/¯¯¯¯¯¯¯¯\____|__________/¯¯¯¯¯¯¯\____________
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-- |
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-- v <- rPhaseSR= "100"
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-- rPhaseSR(2) __________________________________/¯¯¯¯¯¯¯¯\_______________/¯¯¯¯¯¯¯\___
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--
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-- rDValidDly0 _________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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--
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-- rDValidDly1 _________________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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--
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-- rDValidDly2 __________________________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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--
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-- In this design use a single bit counter on the input clock (Clk1x) domain
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-- and pass it to the RfClk domain. When data valid is asserted when both
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-- clocks are rising edge aligned, only one bit in rPhaseSR high, the
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-- remaining bits are zero. We use the position of the bit counter in the
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-- shift register to do data packing.
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--
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--
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-- Timing diagram: When data valid is asserted when both clock are NOT edge
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-- aligned.
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--
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-- | | |
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-- v <-Clocks edge aligned v v
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-- Clk1x ¯¯\____/¯¯¯¯¯\_____/¯¯¯¯¯\_____/¯¯¯¯¯\_____/¯¯¯¯¯\_____/¯¯¯¯¯\___
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-- |
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-- v <- O/p data valid assertion
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-- RfClk ¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯¯¯\___/¯
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-- | | | |
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-- c1DataValid ________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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-- | | | |
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-- c1DValidDly ___________________/¯¯¯¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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-- | | | |
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-- c1PhaseCount ___________________/¯¯¯¯¯¯¯¯¯¯|¯\_____|_____/¯|¯¯¯¯¯¯¯|¯¯\__________/¯¯
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-- | | | |
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-- v <- rPhaseSR= "001" |
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-- rPhaseSR(0) ________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯|¯\_____|_/¯¯¯¯¯|¯¯¯¯¯¯¯¯¯¯
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-- | | |
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-- v <- rPhaseSR= "011"
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-- rPhaseSR(1) ________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯|¯\_____|_/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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-- | |
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-- v <- rPhaseSR= "110"
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-- rPhaseSR(2) ________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯\_______/¯¯¯¯¯¯¯¯¯¯
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-- ^
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-- | <- rPhaseSR= "101"
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--
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-- rDValidDly0 _________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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--
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-- rDValidDly1 _________________________/¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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--
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-- The above timing diagram is when input data valid is asserted when both
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-- clocks rising edges are not aligned. In this case the more than one bit in
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-- rPhaseSR is asserted which is unique to this case. As mentioned in the
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-- above case, we use rPhaseSR value to determine data packing.
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-- Output Data Packer
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DataOut: process(RfClk)
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begin
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if rising_edge(RfClk) then
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-- rPhaseShiftReg = "011"
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rDataOut <= rDataInDly(2)(kDataQ7Msb downto kDataI0Lsb);
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if rPhaseShiftReg = "110" or rPhaseShiftReg = "100" then
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rDataOut <= rDataInDly(2)(kDataQ3Msb downto kDataI0Lsb) &
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rDataInDly(3)(c1DataIn'length-1 downto kDataQ7Msb+1);
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elsif rPhaseShiftReg = "101" or rPhaseShiftReg = "001" then
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rDataOut <= rDataInDly(3)(c1DataIn'length-1 downto kDataI4Lsb);
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elsif rPhaseShiftReg = "010" then
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rDataOut <= rDataInDly(3)(kDataQ7Msb downto kDataI0Lsb);
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end if;
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end if;
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end process;
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DataValidOut: process(RfClk, arReset_n)
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begin
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if arReset_n = '0' then
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rDataValidDly <= (others => '0');
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rDataValidOut <= '0';
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elsif rising_edge(RfClk) then
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rDataValidDly <= rDataValidDly(rDataValidDly'left-1 downto 0) &
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c1DataValidIn;
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-- Data valid out asserting based on phase alignment RfClk and Clk1x.
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-- When RfClk and Clk1x are not phase aligned.
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rDataValidOut <= rDataValidDly(2) and rReadyForOutput;
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-- When RfClk and Clk1x are phase aligned.
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if (rPhaseShiftReg(2) xor rPhaseShiftReg(1) xor rPhaseShiftReg(0)) = '1' then
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rDataValidOut <= rDataValidDly(2) and rDataValidDly(3) and rReadyForOutput;
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end if;
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end if;
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end process;
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end RTL;
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