5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
520 lines
18 KiB
Verilog
520 lines
18 KiB
Verilog
//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rf_atr_control
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//
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// Description:
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//
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// Implements control over RF switches via CtrlPort. Uses RAM to store multiple
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// ATR configurations.
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// There are three supported control schemes for these switches:
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// - ATR Disabled - Single persistent state.
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// - Classic ATR - Each channel's switches depend on the transmission state
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// of the respective channel.
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// - DB State - Each channel's switches depend on the transmission state
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// of all channels in this radio.
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//
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// Parameters:
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//
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// REG_BASE : Base address to use for registers.
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// REG_SIZE : Register space size.
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//
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module rf_atr_control #(
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parameter REG_BASE = 0,
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parameter REG_SIZE = 'h2000
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) (
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// Slave ctrlport interface
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status = 2'b00,
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output reg [31:0] s_ctrlport_resp_data = {32 {1'b0}},
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// Run state signals that indicate tx and rx operation
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input wire [7:0] db_state,
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// Switch control outputs
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output reg rf0_tx_rx_rfs,
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output reg rf0_rx_rfs,
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output reg rf0_tdds,
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output reg rf1_tx_rx_rfs,
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output reg rf1_rx_rfs,
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output reg rf1_tdds,
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output reg rf2_tx_rx_rfs,
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output reg rf2_rx_rfs,
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output reg rf2_tdds,
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output reg rf3_tx_rx_rfs,
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output reg rf3_rx_rfs,
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output reg rf3_tdds
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);
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`include "../../../../lib/rfnoc/core/ctrlport.vh"
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`include "regmap/rf_atr_regmap_utils.vh"
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//---------------------------------------------------------------
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// ATR memory signals
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//---------------------------------------------------------------
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reg ram_rf0_wea;
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wire [RFS_SIZE-1:0] ram_rf0_doa;
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wire [RFS_SIZE-1:0] ram_rf0_dob;
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reg ram_rf1_wea;
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wire [RFS_SIZE-1:0] ram_rf1_doa;
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wire [RFS_SIZE-1:0] ram_rf1_dob;
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reg ram_rf2_wea;
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wire [RFS_SIZE-1:0] ram_rf2_doa;
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wire [RFS_SIZE-1:0] ram_rf2_dob;
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reg ram_rf3_wea;
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wire [RFS_SIZE-1:0] ram_rf3_doa;
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wire [RFS_SIZE-1:0] ram_rf3_dob;
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//---------------------------------------------------------------
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// ATR Scheme signals
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//---------------------------------------------------------------
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reg [3:0] atr_disable = 4'b0;
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// DB state/Classic ATR selector
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reg [3:0] atr_mode = 4'b0;
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//---------------------------------------------------------------------------
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// Control interface handling
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//---------------------------------------------------------------------------
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// Check that address is within this module's range.
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wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE);
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// Check that address is targeting an ATR state.
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wire address_is_atr = (s_ctrlport_req_addr >= REG_BASE + RF0_ATR_STATE(0)) && (s_ctrlport_req_addr <= REG_BASE + RF3_ATR_STATE(RF3_ATR_STATE_COUNT-1));
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// Read request shift register to align memory read and response generation.
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reg [ 1:0] read_req_shift_reg = 2'b0;
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// Mask out 8 bits for ATR configurations to be able to compare all ATR
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// configurations against the same base register address.
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wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};
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// Decode the ATR state being addressed.
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wire [ 7:0] atr_address = s_ctrlport_req_addr[9:2];
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_data <= 32'b0;
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s_ctrlport_resp_status <= 2'b00;
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atr_disable <= 4'b0;
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atr_mode <= 4'b0;
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ram_rf0_wea <= 1'b0;
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ram_rf1_wea <= 1'b0;
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ram_rf2_wea <= 1'b0;
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ram_rf3_wea <= 1'b0;
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end else begin
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// default assignments
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read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};
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ram_rf0_wea <= 1'b0;
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ram_rf1_wea <= 1'b0;
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ram_rf2_wea <= 1'b0;
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ram_rf3_wea <= 1'b0;
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// Write registers
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if (s_ctrlport_req_wr) begin
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// Acknowledge by default
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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// Address ATR state writes
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if(address_is_atr) begin
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case (register_base_address)
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REG_BASE + RF0_ATR_STATE(0): begin
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ram_rf0_wea <= 1'b1;
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end
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REG_BASE + RF1_ATR_STATE(0): begin
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ram_rf1_wea <= 1'b1;
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end
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REG_BASE + RF2_ATR_STATE(0): begin
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ram_rf2_wea <= 1'b1;
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end
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REG_BASE + RF3_ATR_STATE(0): begin
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ram_rf3_wea <= 1'b1;
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end
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// error on undefined address
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default: begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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end
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endcase
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end else begin
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// Address writes to the rest of the register space
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case (s_ctrlport_req_addr)
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REG_BASE + ATR_OPTION_REGISTER: begin
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atr_mode[0] <= s_ctrlport_req_data[RF0_ATR_OPTION];
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atr_mode[1] <= s_ctrlport_req_data[RF1_ATR_OPTION];
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atr_mode[2] <= s_ctrlport_req_data[RF2_ATR_OPTION];
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atr_mode[3] <= s_ctrlport_req_data[RF3_ATR_OPTION];
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end
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REG_BASE + RF_ATR_DISABLED: begin
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atr_disable[0] <= s_ctrlport_req_data[RF0_ATR_DISABLED];
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atr_disable[1] <= s_ctrlport_req_data[RF1_ATR_DISABLED];
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atr_disable[2] <= s_ctrlport_req_data[RF2_ATR_DISABLED];
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atr_disable[3] <= s_ctrlport_req_data[RF3_ATR_DISABLED];
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end
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// Read registers
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end else if (read_req_shift_reg[1]) begin
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// Acknowledge by default
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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// Address ATR state reads
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if(address_is_atr) begin
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case (register_base_address)
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REG_BASE + RF0_ATR_STATE(0): begin
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s_ctrlport_resp_data <= ram_rf0_doa & RF_ATR_STATE_MASK;
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end
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REG_BASE + RF1_ATR_STATE(0): begin
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s_ctrlport_resp_data <= ram_rf1_doa & RF_ATR_STATE_MASK;
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end
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REG_BASE + RF2_ATR_STATE(0): begin
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s_ctrlport_resp_data <= ram_rf2_doa & RF_ATR_STATE_MASK;
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end
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REG_BASE + RF3_ATR_STATE(0): begin
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s_ctrlport_resp_data <= ram_rf3_doa & RF_ATR_STATE_MASK;
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end
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default: begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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end
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endcase
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end else begin
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// Address reads to the rest of the register space
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case (s_ctrlport_req_addr)
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REG_BASE + ATR_OPTION_REGISTER: begin
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s_ctrlport_resp_data[RF0_ATR_OPTION] <= atr_mode[0];
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s_ctrlport_resp_data[RF1_ATR_OPTION] <= atr_mode[1];
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s_ctrlport_resp_data[RF2_ATR_OPTION] <= atr_mode[2];
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s_ctrlport_resp_data[RF3_ATR_OPTION] <= atr_mode[3];
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end
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REG_BASE + RF_ATR_DISABLED: begin
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s_ctrlport_resp_data[RF0_ATR_DISABLED] <= atr_disable[0];
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s_ctrlport_resp_data[RF1_ATR_DISABLED] <= atr_disable[1];
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s_ctrlport_resp_data[RF2_ATR_DISABLED] <= atr_disable[2];
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s_ctrlport_resp_data[RF3_ATR_DISABLED] <= atr_disable[3];
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end
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// No register implementation for provided address
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default: begin
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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// register without reset
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reg [ 7:0] ram_addr = 8'b0;
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reg [RFS_SIZE-1:0] ram_datain = {RFS_SIZE{1'b0}};
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always @(posedge ctrlport_clk) begin
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// memories
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ram_addr <= atr_address;
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ram_datain <= s_ctrlport_req_data[RFS_SIZE-1:0];
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end
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// ATR Scheme selection
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reg [7:0] atr_config_rf [3:0];
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generate
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genvar i;
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for (i = 0; i < 4; i = i + 1) begin: read_address_gen
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always @(posedge ctrlport_clk) begin
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if (atr_disable[i]) begin
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atr_config_rf[i] <= 8'b0;
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end else begin
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if (atr_mode[i]) begin
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atr_config_rf[i] <= {6'b0, db_state[2*i+:2]};
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end else begin
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atr_config_rf[i] <= db_state;
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end
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end
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end
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end
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endgenerate
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// Output decoding
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always @(posedge ctrlport_clk) begin
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rf0_tx_rx_rfs <= ram_rf0_dob[TX_RX_RFS];
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rf0_rx_rfs <= ram_rf0_dob[RX_RFS];
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rf0_tdds <= ram_rf0_dob[TDDS];
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rf1_tx_rx_rfs <= ram_rf1_dob[TX_RX_RFS];
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rf1_rx_rfs <= ram_rf1_dob[RX_RFS];
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rf1_tdds <= ram_rf1_dob[TDDS];
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rf2_tx_rx_rfs <= ram_rf2_dob[TX_RX_RFS];
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rf2_rx_rfs <= ram_rf2_dob[RX_RFS];
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rf2_tdds <= ram_rf2_dob[TDDS];
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rf3_tx_rx_rfs <= ram_rf3_dob[TX_RX_RFS];
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rf3_rx_rfs <= ram_rf3_dob[RX_RFS];
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rf3_tdds <= ram_rf3_dob[TDDS];
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end
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//---------------------------------------------------------------
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// ATR memory
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//---------------------------------------------------------------
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ram_2port #(
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.DWIDTH (RFS_SIZE),
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.AWIDTH (8),
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.RW_MODE ("READ-FIRST"),
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.RAM_TYPE ("AUTOMATIC"),
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.OUT_REG (0)
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) ram_rf0_i (
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.clka (ctrlport_clk),
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.ena (1'b1),
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.wea (ram_rf0_wea),
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.addra (ram_addr),
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.dia (ram_datain),
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.doa (ram_rf0_doa),
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.clkb (ctrlport_clk),
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.enb (1'b1),
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.web (1'b0),
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.addrb (atr_config_rf[0]),
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.dib ({RFS_SIZE{1'b0}}),
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.dob (ram_rf0_dob));
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ram_2port #(
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.DWIDTH (RFS_SIZE),
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.AWIDTH (8),
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.RW_MODE ("READ-FIRST"),
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.RAM_TYPE ("AUTOMATIC"),
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.OUT_REG (0)
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) ram_rf1_i (
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.clka (ctrlport_clk),
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.ena (1'b1),
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.wea (ram_rf1_wea),
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.addra (ram_addr),
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.dia (ram_datain),
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.doa (ram_rf1_doa),
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.clkb (ctrlport_clk),
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.enb (1'b1),
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.web (1'b0),
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.addrb (atr_config_rf[1]),
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.dib ({RFS_SIZE{1'b0}}),
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.dob (ram_rf1_dob));
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ram_2port #(
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.DWIDTH (RFS_SIZE),
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.AWIDTH (8),
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.RW_MODE ("READ-FIRST"),
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.RAM_TYPE ("AUTOMATIC"),
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.OUT_REG (0)
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) ram_rf2_i (
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.clka (ctrlport_clk),
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.ena (1'b1),
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.wea (ram_rf2_wea),
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.addra (ram_addr),
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.dia (ram_datain),
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.doa (ram_rf2_doa),
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.clkb (ctrlport_clk),
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.enb (1'b1),
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.web (1'b0),
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.addrb (atr_config_rf[2]),
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.dib ({RFS_SIZE{1'b0}}),
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.dob (ram_rf2_dob));
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ram_2port #(
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.DWIDTH (RFS_SIZE),
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.AWIDTH (8),
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.RW_MODE ("READ-FIRST"),
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.RAM_TYPE ("AUTOMATIC"),
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.OUT_REG (0)
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) ram_rf3_i (
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.clka (ctrlport_clk),
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.ena (1'b1),
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.wea (ram_rf3_wea),
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.addra (ram_addr),
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.dia (ram_datain),
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.doa (ram_rf3_doa),
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.clkb (ctrlport_clk),
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.enb (1'b1),
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.web (1'b0),
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.addrb (atr_config_rf[3]),
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.dib ({RFS_SIZE{1'b0}}),
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.dob (ram_rf3_dob));
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endmodule
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//XmlParse xml_on
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//<regmap name="RF_ATR_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="RF_ATR_REGISTERS">
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// <info>
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// Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1
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// switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for
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// all four switches are not considered time critical controls, and are hence driven by an I/O
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// expander controlled via I2C.
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// This register map describes how to control the behavior of the 3 HMC849A switches' control lines.
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// There are three supported control schemes for these switches:</br>
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// <ul>
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// <li>ATR Disabled - Single persistent state.</li>
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// <li>Classic ATR - Each channel's switches depend on the transmission state
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// of the respective channel.</li>
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// <li>DB State - Each channel's switches depend on the transmission state
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// of all channels in this radio.</li>
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// </ul>
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// </info>
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//
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// <enumeratedtype name="RF_SWITCHES_SIZE_TYPE">
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// <value name="RFS_SIZE" integer="3"/>
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// </enumeratedtype>
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//
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// <regtype name="RF_ATR_STATE" size="32">
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// <info>Holds the value for the control lines of each channel's switches
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// for a particular ATR sate</info>
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// <bitfield name="TX_RX_RFS" range="0" initialvalue="0"/>
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// <bitfield name="RX_RFS" range="1" initialvalue="0"/>
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// <bitfield name="TDDS" range="2" initialvalue="0"/>
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// </regtype>
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//
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// <register name="RF0_ATR_STATE" typename="RF_ATR_STATE" offset="0x00" count="256" options="--step 4">
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// <info>
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// Describes switch control behavior for the different ATR states. When @.RF0_ATR_OPTION
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// is set to use the DB states, TX and RX states for RF0-RF3 are
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// combined to create a single vector. This creates 256 different
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// combinations, each with its own register. When @.RF0_ATR_OPTION is set to
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// classic ATR, the first 4 offsets in this register group will be driven
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// in accordance with the state of RF0.
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// CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1,
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// TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1]
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// </info>
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// </register>
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//
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// <register name="RF1_ATR_STATE" typename="RF_ATR_STATE" offset="0x400" count="256" options="--step 4">
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// <info>
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// Describes switch control behavior for the different ATR states. When @.RF1_ATR_OPTION
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// is set to use the DB states, TX and RX states for RF0-RF3 are
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// combined to create a single vector. This creates 256 different
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// combinations, each with its own register. When @.RF1_ATR_OPTION is set to
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// classic ATR, the first 4 offsets in this register group will be driven
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// in accordance with the state of RF1.
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// CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1,
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// TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1]
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// </info>
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// </register>
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//
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// <register name="RF2_ATR_STATE" typename="RF_ATR_STATE" offset="0x800" count="256" options="--step 4">
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// <info>
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// Describes switch control behavior for the different ATR states. When @.RF2_ATR_OPTION
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// is set to use the DB states, TX and RX states for RF0-RF3 are
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// combined to create a single vector. This creates 256 different
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// combinations, each with its own register. When @.RF2_ATR_OPTION is set to
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// classic ATR, the first 4 offsets in this register group will be driven
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// in accordance with the state of RF2.
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// CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1,
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// TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1]
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// </info>
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// </register>
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//
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// <register name="RF3_ATR_STATE" typename="RF_ATR_STATE" offset="0xC00" count="256" options="--step 4">
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// <info>
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// Describes switch control behavior for the different ATR states. When @.RF3_ATR_OPTION
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// is set to use the DB states, TX and RX states for RF0-RF3 are
|
|
// combined to create a single vector. This creates 256 different
|
|
// combinations, each with its own register. When @.RF3_ATR_OPTION is set to
|
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// classic ATR, the first 4 offsets in this register group will be driven
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// in accordance with the state of RF3.
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// CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1,
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// TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1]
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// </info>
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// </register>
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// <register name="ATR_OPTION_REGISTER" offset="0x1000" size="32">
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// <info>
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// Controls whether switch control lines use the TX and RX state of
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// their respective channel (Classic ATR) or the daughterboard state
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// to select which state to use from values set in RF_ATR_STATE registers.
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// For each particular bit:</br>
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// 0: Use DB state for ATR</br>
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// 1: Classic ATR mode.
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// </info>
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// <bitfield name="RF0_ATR_OPTION" range="0" initialvalue="0">
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// <info>
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// Control ATR scheme for RF0.
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// </info>
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// </bitfield>
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// <bitfield name="RF1_ATR_OPTION" range="1" initialvalue="0">
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// <info>
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// Control ATR scheme for RF1.
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// </info>
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// </bitfield>
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// <bitfield name="RF2_ATR_OPTION" range="2" initialvalue="0">
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// <info>
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// Control ATR scheme for RF2.
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// </info>
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// </bitfield>
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// <bitfield name="RF3_ATR_OPTION" range="3" initialvalue="0">
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// <info>
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// Control ATR scheme for RF3.
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// </info>
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// </bitfield>
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// </register>
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// <register name="RF_ATR_DISABLED" offset="0x1004" size="32">
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// <info>
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// Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.
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// </info>
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// <bitfield name="RF0_ATR_DISABLED" range="0" initialvalue="0"/>
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// <bitfield name="RF1_ATR_DISABLED" range="1" initialvalue="0"/>
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// <bitfield name="RF2_ATR_DISABLED" range="2" initialvalue="0"/>
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// <bitfield name="RF3_ATR_DISABLED" range="3" initialvalue="0"/>
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// </register>
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// </group>
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//</regmap>
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//XmlParse xml_off
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