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b210-k7-fpga/top/n3xx
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Wade Fife 869861c8cf fpga: Set default part for sim in setupenv.sh 
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.


Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
2021-08-30 08:20:10 -05:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dboards
fpga: n3xx: Fix timeout for timekeeper registers
2020-08-19 12:28:22 -05:00
doc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dts
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
ip
fpga: n3xx: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
sim
fpga: Update testbenches to work in ModelSim
2021-06-17 08:16:59 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_n3xx.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
Makefile.n3xx.inc
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
mb_clocks.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_timing.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_clocking.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_core.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
n3xx_db_fe_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_channel_wrapper.v
N3xx: Fix White Rabbit
2021-08-04 15:19:58 -05:00
n3xx_mgt_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_wrapper.v
fpga: n3xx: Fix White Rabbit images
2020-07-01 15:49:13 -05:00
n3xx_serial_dac_arb.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_serial_dac.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr_top.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_bist_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n300_bist_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n300_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n300_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n300_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n310_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_bist_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n310_bist_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n310_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n310_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n310_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n320_bist_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n320_bist_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n320_bist_static_router.hex
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n320_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
n320_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
n320_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
setupenv.sh
fpga: Set default part for sim in setupenv.sh
2021-08-30 08:20:10 -05:00
WrapBufg.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00