52 lines
1.5 KiB
Verilog
52 lines
1.5 KiB
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Use this module in conjunction with settings_bus.v to add stateful reads
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// to the settings bis. This enables you to do things like have registers reset atomicly
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// as they are read. It also pipelines the address path to ease timing.
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//
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module settings_readback
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#(parameter AWIDTH=16, parameter DWIDTH=32, parameter RB_ADDRW=2)
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(
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input wb_clk,
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input wb_rst,
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input [AWIDTH-1:0] wb_adr_i,
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input wb_stb_i,
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input wb_we_i,
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input [DWIDTH-1:0] rb_data,
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output reg [RB_ADDRW-1:0] rb_addr,
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output [DWIDTH-1:0] wb_dat_o,
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output reg rb_rd_stb
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);
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always @(posedge wb_clk)
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if (wb_stb_i && ~wb_we_i) begin
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rb_addr <= wb_adr_i[RB_ADDRW+1:2];
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rb_rd_stb <= 1'b1;
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end else begin
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rb_rd_stb <= 1'b0;
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end
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assign wb_dat_o = rb_data;
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endmodule // settings_readback
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