59 lines
1.6 KiB
Verilog
59 lines
1.6 KiB
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock
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module settings_bus
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#(parameter AWIDTH=16, parameter DWIDTH=32, parameter SWIDTH=8)
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(input wb_clk,
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input wb_rst,
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input [AWIDTH-1:0] wb_adr_i,
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input [DWIDTH-1:0] wb_dat_i,
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input wb_stb_i,
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input wb_we_i,
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output reg wb_ack_o,
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output reg strobe,
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output reg [SWIDTH-1:0] addr,
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output reg [31:0] data);
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reg stb_int, stb_int_d1;
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always @(posedge wb_clk)
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if(wb_rst)
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begin
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strobe <= 1'b0;
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addr <= {SWIDTH{1'b0}};
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data <= 32'd0;
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end
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else if(wb_we_i & wb_stb_i & ~wb_ack_o)
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begin
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strobe <= 1'b1;
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addr <= wb_adr_i[SWIDTH+1:2];
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data <= wb_dat_i;
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end
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else
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strobe <= 1'b0;
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always @(posedge wb_clk)
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if(wb_rst)
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wb_ack_o <= 0;
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else
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wb_ack_o <= wb_stb_i & ~wb_ack_o;
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endmodule // settings_bus
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