63 lines
2.0 KiB
Verilog
63 lines
2.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module trigger_context_pkt
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#(parameter BASE=0)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input packet_consumed, output trigger);
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wire [23:0] cycles;
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wire [15:0] packets;
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wire [6:0] dummy1;
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wire [14:0] dummy2;
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wire enable_cycle, enable_consumed;
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reg [30:0] cycle_count, packet_count;
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setting_reg #(.my_addr(BASE), .at_reset(0)) sr_cycles
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({enable_cycle,dummy1,cycles}),.changed());
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setting_reg #(.my_addr(BASE+1), .at_reset(0)) sr_packets
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({enable_consumed,dummy2,packets}),.changed());
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always @(posedge clk)
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if(reset | clear)
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cycle_count <= 0;
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else
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if(trigger)
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cycle_count <= 0;
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else if((enable_cycle & packet_consumed) | (cycle_count != 0))
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cycle_count <= cycle_count + 1;
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always @(posedge clk)
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if(reset | clear)
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packet_count <= 0;
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else
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if(trigger)
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packet_count <= 0;
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else if(packet_consumed & enable_consumed)
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packet_count <= packet_count + 1;
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assign trigger = (enable_cycle & (cycle_count >= cycles)) | (enable_consumed & (packet_count >= packets));
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endmodule // trigger_context_pkt
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