103 lines
3.0 KiB
Verilog
103 lines
3.0 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module cvita_dechunker # (
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parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
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) (
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input clk,
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input reset,
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input clear,
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input [15:0] frame_size,
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input [63:0] i_tdata,
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input i_tvalid,
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output i_tready,
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output [63:0] o_tdata,
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output o_tlast,
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output o_tvalid,
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input o_tready,
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output error
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);
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localparam ST_HEADER = 2'd0;
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localparam ST_DATA = 2'd1;
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localparam ST_PADDING = 2'd2;
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localparam ST_ERROR = 2'd3;
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reg [1:0] state;
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reg [15:0] frame_rem, pkt_rem;
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wire i_tlast;
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wire [15:0] cvita_len_ceil = i_tdata[47:32] + 7;
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wire [15:0] axi_len = {3'b000, cvita_len_ceil[15:3]};
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always @(posedge clk) begin
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if (reset | clear) begin
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state <= ST_HEADER;
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frame_rem <= 16'd0;
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pkt_rem <= 16'd0;
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end else if (i_tvalid & i_tready) begin
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case (state)
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ST_HEADER: begin
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if (axi_len > frame_size)
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state <= ST_ERROR;
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else if (~o_tlast)
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state <= ST_DATA;
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else
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state <= ST_PADDING;
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frame_rem <= frame_size - 16'd1;
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pkt_rem <= axi_len - 16'd1;
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end
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ST_DATA: begin
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if (o_tlast) begin
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state <= i_tlast ? ST_HEADER : ST_PADDING;
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pkt_rem <= 16'd0;
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end else begin
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state <= ST_DATA;
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pkt_rem <= pkt_rem - 16'd1;
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end
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frame_rem <= frame_rem - 16'd1;
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end
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ST_PADDING: begin
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if (i_tlast) begin
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state <= ST_HEADER;
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frame_rem <= 16'd0;
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end else begin
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state <= ST_PADDING;
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frame_rem <= frame_rem - 16'd1;
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end
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end
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endcase
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end
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end
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assign i_tready = o_tready | (state == ST_PADDING);
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assign i_tlast = (frame_rem == 16'd1); //Temp signal
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assign o_tvalid = i_tvalid & (state != ST_PADDING);
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assign o_tlast = (pkt_rem != 0) ? (pkt_rem == 16'd1) : (axi_len == 16'd1);
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assign o_tdata = i_tdata;
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assign error = (state == ST_ERROR);
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endmodule // cvita_dechunker
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