136 lines
3.9 KiB
Verilog
136 lines
3.9 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// This module is instantiated in parallel with a FIFO with AXI4-STREAM interfaces.
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// It tracks how many complete packets are contained within the FIFO, and also indicates
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// when the first word of a packet is presented on the FIFO outputs.
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//
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module monitor_axi_fifo
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#(
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parameter COUNT_BITS=8
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)
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(
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input clk,
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input reset,
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input clear,
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// Monitored FIFO signals
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input i_tvalid,
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input i_tready,
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input i_tlast,
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input o_tvalid,
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input o_tready,
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input o_tlast,
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// FIFO status outputs
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output reg [COUNT_BITS-1:0] pkt_count, // Exact whole packet count
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output pkt_present // Flags any whole packets present
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);
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localparam WAIT_SOF = 0;
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localparam WAIT_EOF = 1;
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reg in_state, out_state;
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reg pause_tx;
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//
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// Count packets arriving into large FIFO
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//
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always @(posedge clk)
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if (reset | clear) begin
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in_state <= WAIT_SOF;
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end else
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case(in_state)
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//
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// After RESET or the EOF of previous packet, the first cycle with
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// input valid and input ready asserted is the SOF.
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//
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WAIT_SOF:
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if (i_tvalid && i_tready) begin
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in_state <= WAIT_EOF;
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end else begin
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in_state <= WAIT_SOF;
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end
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//
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// EOF is signalled by the assertion i_tlast whilst input valid and ready are asserted.
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//
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WAIT_EOF:
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if (i_tlast && i_tvalid && i_tready) begin
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in_state <= WAIT_SOF;
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end else begin
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in_state <= WAIT_EOF;
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end
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endcase // case(in_state)
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//
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// Count packets leaving large FIFO
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//
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always @(posedge clk)
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if (reset | clear) begin
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out_state <= WAIT_SOF;
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end else
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case(out_state)
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//
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// After RESET or the EOF of previous packet, the first cycle with
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// output valid and output ready asserted is the SOF.
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//
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WAIT_SOF:
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if (o_tvalid && o_tready) begin
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out_state <= WAIT_EOF;
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end else begin
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out_state <= WAIT_SOF;
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end
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//
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// EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
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//
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WAIT_EOF:
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if (o_tlast && o_tvalid && o_tready) begin
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out_state <= WAIT_SOF;
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end else begin
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out_state <= WAIT_EOF;
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end
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endcase // case(in_state)
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//
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// Count packets in FIFO.
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// No protection on counter wrap,
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// unclear how to gracefully deal with it.
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// Perhaps generate Error IRQ so that S/W could clean up?
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// Configure so that the pkt_count is ample for the application.
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//
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always @(posedge clk)
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if (reset | clear)
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pkt_count <= 0;
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else if (((out_state==WAIT_EOF) && o_tlast && o_tvalid && o_tready ) &&
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((in_state==WAIT_EOF) && i_tlast && i_tvalid && i_tready))
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pkt_count <= pkt_count;
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else if ((out_state==WAIT_EOF) && o_tlast && o_tvalid && o_tready)
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pkt_count <= pkt_count - 1;
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else if ((in_state==WAIT_EOF) && i_tlast && i_tvalid && i_tready)
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pkt_count <= pkt_count + 1;
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// Non-zero packet count indicates packet(s) present.
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assign pkt_present = |pkt_count;
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endmodule // count_tx_packets
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