135 lines
3.5 KiB
Verilog
135 lines
3.5 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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`define LOG2(N) (\
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N < 2 ? 0 : \
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N < 4 ? 1 : \
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N < 8 ? 2 : \
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N < 16 ? 3 : \
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N < 32 ? 4 : \
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N < 64 ? 5 : \
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N < 128 ? 6 : \
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N < 256 ? 7 : \
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N < 512 ? 8 : \
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N < 1024 ? 9 : \
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10)
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module axi_slave_mux
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#(
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parameter FIFO_WIDTH = 64, // AXI4-STREAM data bus width
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parameter DST_WIDTH = 16, // Width of DST field we are routing on.
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parameter NUM_INPUTS = 2 // number of input AXI buses
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)
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(
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input clk,
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input reset,
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input clear,
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// Inputs
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input [(FIFO_WIDTH*NUM_INPUTS)-1:0] i_tdata,
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input [NUM_INPUTS-1:0] i_tvalid,
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input [NUM_INPUTS-1:0] i_tlast,
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output [NUM_INPUTS-1:0] i_tready,
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// Forwarding Flags
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input [NUM_INPUTS-1:0] forward_valid,
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output reg [NUM_INPUTS-1:0] forward_ack,
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// Output
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output [FIFO_WIDTH-1:0] o_tdata,
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output o_tvalid,
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output o_tlast,
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input o_tready
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);
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wire [FIFO_WIDTH-1:0] i_tdata_array [0:NUM_INPUTS-1];
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reg [`LOG2(NUM_INPUTS):0] select;
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reg enable;
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reg state;
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localparam CHECK_THIS_INPUT = 0;
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localparam WAIT_LAST = 1;
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always @(posedge clk)
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if (reset | clear) begin
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state <= CHECK_THIS_INPUT;
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select <= 0;
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enable <= 0;
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forward_ack <= 0;
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end else begin
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case(state)
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// Is the currently selected input addressing this slave with a ready packet?
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CHECK_THIS_INPUT: begin
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if (forward_valid[select]) begin
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enable <= 1;
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forward_ack[select] <= 1;
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state <= WAIT_LAST;
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end else if (select == NUM_INPUTS - 1 ) begin
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select <= 0;
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end else begin
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select <= select + 1;
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end
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end
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// Assert ACK immediately to forwarding logic and then wait for end of packet.
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WAIT_LAST: begin
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if (i_tlast[select] && i_tvalid[select] && o_tready) begin
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if (select == NUM_INPUTS - 1 ) begin
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select <= 0;
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end else begin
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select <= select + 1;
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end
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state <= CHECK_THIS_INPUT;
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forward_ack <= 0;
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enable <= 0;
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end else begin
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forward_ack[select] <= 1;
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enable <= 1;
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end
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end
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endcase // case(state)
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end
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//
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// Combinatorial mux
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//
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genvar m;
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generate
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for (m = 0; m < NUM_INPUTS; m = m + 1) begin: form_buses
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assign i_tdata_array[m] = i_tdata[(m*FIFO_WIDTH)+FIFO_WIDTH-1:m*FIFO_WIDTH];
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end
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endgenerate
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assign o_tdata = i_tdata_array[select];
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assign o_tvalid = enable && i_tvalid[select];
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assign o_tlast = enable && i_tlast[select];
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// assign i_tready = {NUM_INPUTS{o_tready}} & (enable << select);
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generate
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for (m = 0; m < NUM_INPUTS; m = m + 1) begin: form_ready
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assign i_tready[m] = o_tready && enable && (select == m);
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end
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endgenerate
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endmodule // axi_slave_mux
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