97 lines
2.7 KiB
Verilog
97 lines
2.7 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// This module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
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// It extracts and indicates the header (first word) of a packet in the FIFO. The header and flag are pipelined
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// for timing closure.
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//
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module axi_fifo_header
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#(
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parameter WIDTH=64 // Bit width of FIFO word.
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)
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(
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input clk,
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input reset,
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input clear,
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// Monitored FIFO signals
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input [WIDTH-1:0] o_tdata,
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input o_tvalid,
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input o_tready,
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input o_tlast,
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input pkt_present,
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// Header signals
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output reg [WIDTH-1:0] header,
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output reg header_valid
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);
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localparam WAIT_SOF = 0;
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localparam WAIT_EOF = 1;
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reg out_state;
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//
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// Monitor packets leaving FIFO
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//
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always @(posedge clk)
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if (reset | clear) begin
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out_state <= WAIT_SOF;
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end else
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case(out_state)
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//
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// After RESET or the EOF of previous packet, the first cycle with
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// output valid asserted is the SOF and presents the Header word.
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// The cycle following the concurrent presentation of asserted output
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// valid and output ready presents the word following the header.
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//
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WAIT_SOF:
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if (o_tvalid && o_tready) begin
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out_state <= WAIT_EOF;
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end else begin
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out_state <= WAIT_SOF;
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end
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//
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// EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
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//
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WAIT_EOF:
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if (o_tlast && o_tvalid && o_tready) begin
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out_state <= WAIT_SOF;
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end else begin
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out_state <= WAIT_EOF;
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end
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endcase // case(in_state)
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//
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// Pipeline Header signals
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//
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always @(posedge clk)
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if (reset | clear) begin
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header <= 0;
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header_valid <= 0;
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end else if (o_tvalid && (out_state == WAIT_SOF) && pkt_present) begin
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// Header will remian valid until o_tready is asserted as this will cause a state transition.
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header <= o_tdata;
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header_valid <= 1;
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end else begin
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header_valid <= 0;
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end
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endmodule // axi_fifo_header
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