miegl
a95cce3d20
Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc. This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior.
251 lines
8.1 KiB
Verilog
251 lines
8.1 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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module chdr_16sc_to_12sc
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#(parameter BASE=0)
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(
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// Clocks and resets
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input clk,
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input reset,
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// Settings bus
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input set_stb,
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input [7:0] set_addr,
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input [31:0] set_data,
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// Input CHDR bus
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input [63:0] i_tdata,
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input i_tlast,
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input i_tvalid,
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output i_tready,
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// Output CHDR bus
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output [63:0] o_tdata,
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output o_tlast,
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output o_tvalid,
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input o_tready,
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// Debug
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output [31:0] debug
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);
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wire chdr_has_time = i_tdata[61];
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wire [11:0] q0;
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wire [11:0] i0;
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wire [11:0] q1;
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wire [11:0] i1;
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wire [11:0] q2;
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wire [11:0] i2;
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wire [16:0] round_q0;
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wire [16:0] round_i0;
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wire [16:0] round_q1;
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wire [16:0] round_i1;
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wire [16:0] round_q2;
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wire [16:0] round_i2;
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reg [63:0] curr_word;
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// Pipeline register
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reg [63:0] buff;
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reg buff_tvalid;
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reg buff_tlast;
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// CHDR has either 8 bytes of header or 16 if VITA time is included.
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wire [15:0] chdr_header_bytes = chdr_has_time? 16 : 8;
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// Calculate size of samples input in bytes by taking CHDR size filed and subtracting header length.
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wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_bytes;
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// Calculate size of samples to be output by taking input size and scaling by 3/4
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wire [15:0] sample_byte_count_out = (sample_byte_count_in*3) >> 2;
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// Calculate size of output CHDR packet by adding back header size to new payload size.
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wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_bytes;
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reg odd;
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wire set_sid;
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wire [15:0] new_sid_dst;
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setting_reg #(.my_addr(BASE), .width(17)) new_destination
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out({set_sid, new_sid_dst[15:0]}));
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// state machine
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localparam HEADER = 3'd0;
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localparam TIME = 3'd1;
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localparam SAMPLE1 = 3'd2;
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localparam SAMPLE2 = 3'd3;
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localparam SAMPLE3 = 3'd4;
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localparam SAMPLE4 = 3'd5;
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reg [2:0] state;
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always @(posedge clk)
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if (reset) begin
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state <= HEADER;
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buff <= 64'd0;
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buff_tvalid <= 1'd0;
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buff_tlast <= 1'd0;
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end else begin
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case(state)
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//
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// Process header
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// Check for timestamp. Byte count conversion is done above.
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// If there is residual data in the buffer, store the header and
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// output the line in the buffer. If not, output the header.
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//
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HEADER: begin
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if (i_tvalid & i_tready) begin
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odd <= sample_byte_count_in [2];
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if (buff_tvalid) begin
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buff <= curr_word;
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buff_tvalid <= i_tvalid;
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buff_tlast <= i_tlast;
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end else begin
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buff <= 64'd0;
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buff_tvalid <= 1'd0;
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buff_tlast <= 1'd0;
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end
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state <= i_tlast ? HEADER : (i_tdata[61]) ? TIME : SAMPLE1;
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end else if (buff_tvalid & o_tready) begin
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buff <= 64'd0;
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buff_tvalid <= 1'd0;
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buff_tlast <= 1'd0;
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end
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end
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//
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// Process time field
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// If the header is in the buffer, output the header and
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// store the timestamp. If not, output the timestamp.
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//
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TIME: begin
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if (i_tvalid & i_tready) begin
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if (buff_tvalid) begin
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buff <= curr_word;
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buff_tvalid <= i_tvalid;
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buff_tlast <= i_tlast;
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end else begin
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buff <= 64'd0;
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buff_tvalid <= 1'd0;
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buff_tlast <= 1'd0;
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end
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state <= i_tlast ? HEADER: SAMPLE1;
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end
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end
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//
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// There are 3 lines of output data for each 4 lines of input data.
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// The 4 sample states below represent the 4 lines of input.
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// They are repeatedly cycled until all data is consumed.
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//
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// Process first line
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// The 8 bytes are converted to 6 bytes, so there is not enough for an
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// 8-byte output line. Store the data unless this is the last line in
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// the packet. If the timestamp is in the buffer, output it.
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//
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SAMPLE1: begin
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if (i_tvalid & i_tready) begin
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buff <= curr_word;
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buff_tvalid <= i_tlast;
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buff_tlast <= i_tlast;
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state <= i_tlast ? HEADER : SAMPLE2;
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end
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end
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//
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// Process second line
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// Output a line comprised of the 6 bytes from the fist line and
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// 2 bytes from this line. Store the remaining 4 bytes.
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//
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SAMPLE2: begin
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if (i_tvalid & i_tready) begin
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buff <= {i0[7:0],q1,i1,32'd0};
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buff_tvalid <= i_tlast;
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buff_tlast <= i_tlast;
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state <= i_tlast ? HEADER : SAMPLE3;
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end
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end
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//
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// Process third line
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// Output line comprised of the 4 remaining bytes from the second line
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// and 4 bytes from this line. Store the remaining 2 bytes unless this
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// is the last line in the packet and the number of samples is odd.
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//
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SAMPLE3: begin
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if (i_tvalid & i_tready) begin
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buff <= {q1[3:0],i1,48'd0};
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buff_tvalid <= i_tlast & ~odd;
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buff_tlast <= i_tlast & ~odd;
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state <= i_tlast ? HEADER : SAMPLE4;
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end
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end
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//
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// Process fourth line
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// Output line comprised of the remaining 2 bytes from the third line
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// and the 6 bytes from this line.
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//
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SAMPLE4: begin
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if (i_tvalid & i_tready) begin
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buff <= 64'd0;
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buff_tvalid <= 1'd0;
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buff_tlast <= 1'd0;
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state <= i_tlast ? HEADER : SAMPLE1;
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end
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end
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//
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// Should never get here.
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//
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default: state <= HEADER;
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endcase
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end
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// Add rounding value into 16bit samples before trunctaion
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assign round_q0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
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assign round_i0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
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// Truncate with saturation to 12bits precision.
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assign q0 = (round_q0[16:15] == 2'b01) ? 12'h7FF : ((round_q0[16:15] == 2'b10) ? 12'h800 : round_q0[15:4]);
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assign i0 = (round_i0[16:15] == 2'b01) ? 12'h7FF : ((round_i0[16:15] == 2'b10) ? 12'h800 : round_i0[15:4]);
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// Add rounding value into 16bit samples before trunctaion
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assign round_q1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
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assign round_i1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
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// Truncate with saturation to 12bits precision.
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assign q1 = (round_q1[16:15] == 2'b01) ? 12'h3FF : ((round_q1[16:15] == 2'b10) ? 12'h800 : round_q1[15:4]);
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assign i1 = (round_i1[16:15] == 2'b01) ? 12'h3FF : ((round_i1[16:15] == 2'b10) ? 12'h800 : round_i1[15:4]);
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//
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// Mux for current word
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//
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always @(*) begin
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// Default assignment prevents latch inference for illegal/unhandled states.
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curr_word = 64'd0;
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case(state)
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HEADER: curr_word = {i_tdata[63:48], output_chdr_pkt_size, set_sid ?
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{i_tdata[15:0], new_sid_dst[15:0]} : i_tdata[31:0]};
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TIME: curr_word = i_tdata;
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SAMPLE1: curr_word = {q0, i0, q1, i1, 16'b0};
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SAMPLE2: curr_word = {buff[63:16], q0, i0[11:8]};
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SAMPLE3: curr_word = {buff[63:32], q0, i0, q1[11:4]};
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SAMPLE4: curr_word = {buff[63:48], q0, i0, q1, i1};
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default: curr_word = 64'd0;
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endcase
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end
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assign o_tdata = buff_tvalid ? buff : curr_word;
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assign o_tvalid = (state == HEADER && buff_tvalid) || (i_tvalid &&
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(state != SAMPLE1 || (state == SAMPLE1 && buff_tvalid)));
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assign o_tlast = buff_tvalid ? buff_tlast : i_tlast && (state == HEADER ||
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state == TIME || (state == SAMPLE3 && odd) || state == SAMPLE4);
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assign i_tready = o_tready;
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endmodule
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