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miegl a95cce3d20 rtl: remove inferred CHDR conversion latches 
Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc.

This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior.
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..
.gitignore
Merge FPGA repository back into UHD repository
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build_8_to_16
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build_12_to_16
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build_16_to_8
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build_16_to_12
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chdr_8s_to_16s.v
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chdr_8sc_to_16sc_tb.v
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chdr_8sc_to_16sc.hex
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chdr_8sc_to_16sc.v
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chdr_12sc_to_16sc_tb.v
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chdr_12sc_to_16sc.v
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chdr_16s_to_8s.v
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chdr_16s_to_32f.v
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chdr_16sc_to_8sc_tb.v
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chdr_16sc_to_8sc.v
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chdr_16sc_to_12sc_tb.v
sim: Update chdr_16sc_to_sc12 testbench
2021-08-10 15:19:32 -05:00
chdr_16sc_to_12sc.v
rtl: remove inferred CHDR conversion latches
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chdr_16sc_to_32f_tb.v
Merge FPGA repository back into UHD repository
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chdr_16sc_to_32f.v
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chdr_16sc_to_xxxx_chain.v
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chdr_32f_to_16s.v
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chdr_32f_to_16sc_tb.v
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chdr_32f_to_16sc.v
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chdr_xxxx_to_16sc_chain.v
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context_packet_gen.v
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float_to_iq_tb.v
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float_to_iq.v
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from8_to_x.hex
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from12_to_x.hex
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from16_to_x.hex
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generate_bits.cpp
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iq_to_float_input.txt
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iq_to_float_output.txt
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iq_to_float_tb.v
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iq_to_float.v
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Makefile.srcs
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new_rx_control.v
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new_rx_framer.v
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new_rx_tb.v
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new_tx_control_tb.v
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new_tx_control.v
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new_tx_deframer.v
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new_tx_tb.v
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trigger_context_pkt.v
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tx_responder.v
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xxf_to_xxs.v
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xxs_to_xxf.v
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