FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
Adds a BUILD_BASE_DIR makefile variable that allows you to specify the
base directory for FPGA build outputs. This allows you to put the
output from each run of make into a unique directory, or to run
multiple instances of make in parallel with each build's output being
put in a different directory. For example:
make X310_XG BUILD_BASE_DIR=/path/to/builds
Original-commit: bc6db8409ba756bbad0d0c158ffb00c614b58fd9
The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
to include XO3 PLL
- Add ability to shift outgoing data for
the GPIO communication interface with
the X410 FPGA.
- Include project files required to build
the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.
Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to
the location of the UHD "fpga" directory. This allows you to include
files in your out-of-tree modules relative to the FPGA directory. For
example, you could include the library header file rfnoc_chdr_utils.vh
using the following:
`include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
Some simulators may not support `" outside of the context of a `define,
in which case you can do the following:
`define RFNOC_CHDR_UTILS_PATH \
`"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
`include `RFNOC_CHDR_UTILS_PATH
Original-commit: 66267f515802ff3f965fd44e1f0d3097ada7484f
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.
Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
PkgComplex adds functions for doing complex arithmetic in SystemVerilog
simulation.
PkgMath provides mathematical operations and constants that aren't
built into SystemVerilog, such as a constant for pi and the function
round().
PkgRandom adds randomization functions beyond what standard Verilog
supports but that don't require any special licenses or simulators.
Original-commit: da4202e6f74796603072aa14544581604e81df02
This updates the existing PART_NAME generation used in simulation
makefiles to work with newer part families by calling
viv_gen_part_id.py to generate the part name needed by Vivado.
Original-commit: 648c70ae758ab1d15c7ec6cbe57672e8c27640cd
This adds the MSIM_VIV_COMPLIBDIR environment variable to specify
a non-default location for the compilation libraries.
This also allows a modelsim.ini other than the one in the ModelSim
installation folder to be used. By default, the one in the simulation
libraries compilation directory will be used. This can be changed by
setting MSIM_MODELSIM_INI to the one you want to use, or set it to an
empty string to use the one in the ModelSim installation folder.
Original-commit: 08473776b28a949027ec8cf2596d8d1b438b979b
This adds the ability to call BUILD_VIVADO_IP, as before, followed by
REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and
then rebuild the IP with the patched file.
Original-commit: 78315eca698333ad4dc32818e24c7bf6a740c0cb
- 2to3 was used to convert the Python scripts, except where the tool
choked and manual intervention was required
- All references to "python" where replaced with "python3"
- buffer() was replaced by memoryview()
Original-commit: ca68195b5d12c5410cfac8d459a0b0902c4c72c7
During recreation of block diagrams any RTL modules will be kept in
hidden directories within the build directory. Updates of the RTL
sources might not be taken into account. Solution is to remove Xilinx's
hidden project directories before calling vivado.
Original-commit: f17a5113e228ac1bc5312193eb8f687e127184a3
This adds support for colored output and support for directories added
to the list of source files (for HLS support).
Original-commit: 5b3d66e5b7cedb7098de3e4dbbee70af04a3626e
For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.
Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a
Add -voptargs=+acc to the default options when running vsim. This
option enables debug command access to objects in the design, which is
generally needed for debugging in the GUI.
Original-commit: eed2d2348cab7dc786673f0649373809d04027d5
This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.
Adds or modifies the following simulation make targets:
make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim
Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS - Added to SystemVerilog invocation of vlog
VLOG_ARGS - Added to Verilog invocation of vlog
VHDL_ARGS - Added to VHDL invocation of vcom
Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.
This commit also updates the license files and paths therein.
We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.
== Original Codebase and Rebasing ==
The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/
It can be used for bisecting, reference, and a more detailed history.
The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.
If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:
- Create a directory to store patches (this should be an empty
directory):
mkdir ~/patches
- Now make sure that your FPGA codebase is based on the same state as
the code that was merged:
cd src/fpga # Or wherever your FPGA code is stored
git rebase v4.0.0.0-pre-uhd-merge
Note: The rebase command may look slightly different depending on what
exactly you're trying to rebase.
- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:
git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches
Note: Make sure that only patches are stored in your output directory.
It should otherwise be empty. Make sure that you picked the correct
range of commits, and only commits you wanted to rebase were exported
as patch files.
- Go to the UHD repository and apply the patches:
cd src/uhd # Or wherever your UHD repository is stored
git am --directory fpga ~/patches/*
rm -rf ~/patches # This is for cleanup
== Contributors ==
The following people have contributed mainly to these files (this list
is not complete):
Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
