This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.
Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.
New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.
For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:
make -j4 X310_IP
Or, build two X310 bitstreams simultaneously:
make -j2 X310_XG X310_HG
Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
Change the width of the crossbar in the AXI Interconnect IP from
256-bit to 512-bit to match the DRAM memory controller width and to
give better performance.
Original-commit: 822cd03c8cd686f8b0554774adcbdd3803128bc2
White Rabbit is not supported in X410, however the register map included an
incorrect reference to this unsupported feature.
This commit removes the WR reference from both the source and html files.
Original-commit: 7edd92dbcf2da1a1c0fabe02a97fdb6afdc89077
Wade Fife