miegl/b210-k7-fpga
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56e84828fe057ffb136800112cff08ed3c17c853
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3 Commits
Author SHA1 Message Date
Ashish Chaudhari adf2da6ac7 fpga: Multiple X300 FPGA bugfixes and enhancements 
- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
 2014-09-24 18:45:31 -07:00
Ashish Chaudhari 6b7004c311 fpga: Added FPGA code for X300 MIMO alignment bugfix 
Original-commit: 3347e831f002da769632dfe0c70ea17c2d749a8a
 2014-08-19 12:05:46 -07:00
Ben Hilburn fbbc991a7d Pushing the bulk of UHD-3.7.0 code. 
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
 2014-02-14 12:05:07 -08:00