41 lines
1.9 KiB
Plaintext
41 lines
1.9 KiB
Plaintext
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NET "FPGA_CLK_p" TNM_NET = "FPGA_CLK_p";
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TIMESPEC "TS_FPGA_CLK_p" = PERIOD "FPGA_CLK_p" 5000 ps HIGH 50 %;
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NET "FPGA_CLK_n" TNM_NET = "FPGA_CLK_n";
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TIMESPEC "TS_FPGA_CLK_n" = PERIOD "FPGA_CLK_n" 5000 ps HIGH 50 %;
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NET "FPGA_125MHz_CLK" TNM_NET = "FPGA_125MHz_CLK";
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TIMESPEC "TS_FPGA_125MHz_CLK" = PERIOD "FPGA_125MHz_CLK" 8000 ps HIGH 50 %;
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#NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P";
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#TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 8333 ps HIGH 50 %;
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#NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P";
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#TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 8333 ps HIGH 50 %;
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NET "DB0_ADC_DCLK_P" TNM_NET = "DB0_ADC_DCLK_P";
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TIMESPEC "TS_DB0_ADC_DCLK_P" = PERIOD "DB0_ADC_DCLK_P" 5000 ps HIGH 50 %;
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OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" RISING;
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OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB0_ADC_DCLK_P" FALLING;
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NET "DB1_ADC_DCLK_P" TNM_NET = "DB1_ADC_DCLK_P";
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TIMESPEC "TS_DB1_ADC_DCLK_P" = PERIOD "DB1_ADC_DCLK_P" 5000 ps HIGH 50 %;
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OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" RISING;
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OFFSET = IN 0.75ns VALID 1.5nS BEFORE "DB1_ADC_DCLK_P" FALLING;
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NET "bus_clk" TNM = bus_clk_grp;
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NET "ioport2_clk" TNM = ioport2_clk_grp;
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NET "rio40_clk" TNM = rio40_clk_grp;
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TIMESPEC TS_BUS_CLK_TO_IOPORT2_CLK_FALEPATH = FROM bus_clk_grp TO ioport2_clk_grp TIG;
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TIMESPEC TS_IOPORT2_CLK_TO_BUS_CLK_FALEPATH = FROM ioport2_clk_grp TO bus_clk_grp TIG;
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TIMESPEC TS_IOPORT2_CLK_TO_RIO40_CLK_FALEPATH = FROM ioport2_clk_grp TO rio40_clk_grp TIG;
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TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_clk_grp TIG;
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# FPGA_CLK_p/n is externally phase shifted to allow for crossing from the ADC clock domain
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# to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent,
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# lock the locations of the MMCM and BUFG to generate radio_clk.
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INST "radio_clk_gen/mmcm_adv_inst" LOC = MMCME2_ADV_X0Y0;
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INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8; |