Commit Graph
12 Commits
Author SHA1 Message Date
Wade Fife 3b1d62928d fpga: Change RFNoC YAML version numbers to strings
Change version from a numeric to a string, in order to
differentiate between versions like "1.1" and "1.10".


Original-commit: ca21048bd2f832b20bb36763f76d46b861b697a5
2021-06-08 15:48:59 -05:00
Wade Fife ba66b26dc5 fpga: e320: Improve timing on LVDS interface
Original-commit: c6578eda2ba482b87583ebd989cdf5cbd5c3f672
2020-12-11 07:41:13 -06:00
michael-west bb7e7023e6 E320: Revert addition of Replay block
The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 413ebee61254fd0b9ab0cd11b475b8a849579cd8
2020-09-04 15:45:51 -07:00
mattprost 52172aaaf3 fpga: Add Replay Block to RFNoC Core Image
Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.

Signed-off-by: mattprost <matt.prost@ni.com>


Original-commit: 437381bd2cfe137c5e7e2a70aab8226bfb1c70cd
2020-09-03 15:26:33 -05:00
Wade Fife eab91d8ed0 fpga: Update DRAM IO signatures
This updates the IO signatures so that all devices and RFNoC blocks use
the same IO signature for the DRAM. This is needed because the IO
signatures must match between the RFNoC blocks and the devices. This
means that some devices have extra bits in the IO signature for the
address, but the extra bits will simply be ignored.


Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a
2020-09-03 15:26:33 -05:00
Wade Fife 7e3f04d0ab fpga: e320: Update AXI interconnect address range
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: d352f5a9c3bd3791f0320be1e615146fe7459453
2020-08-28 15:07:38 -05:00
Wade Fife fd113147be fpga: e320: Fix timeout for timekeeper registers
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.


Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81
2020-08-19 12:28:22 -05:00
Martin Braun 324f9d3c9a fpga: e320: Fix default YAML target to E320_1G
It was set to E320_HG, which is not a valid target, causing build errors
unless -t E320_1G was provided to rfnoc_image_builder.


Original-commit: 9ed42affcaa88e026cb4f82807e69b546ed30c8c
2020-08-17 07:56:30 -05:00
RobertWalstab 84a9230183 fpga, mpm: Bump FPGA compat number
Original-commit: 54d698e3707cf1be5d38537db783ebadd850e729
2020-07-24 15:24:14 -05:00
Alex Williams 08c24691a9 e320: Swap out liberio for internal Ethernet
Original-commit: d01e091c4c7ccc323d305580a27754918b02974b
2020-07-16 10:00:12 -05:00
Wade Fife d16d1e121c fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin
Original-commit: 7f5f771796de590c4ed4bba7b09cda3a906535c6
2020-06-12 15:50:16 -05:00
+18 6b67702ad7 Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
2020-01-28 09:35:36 -08:00