b210-k7-fpga

576 Commits 1 Branch 0 Tags

2 Commits

Author	SHA1	Message	Date
Jonathon PendlumandMartin Braun	d006250dc1	fpga: x400: Add PPS interface to X410/X440 BSP This creates an IO port `pps` for X410, and two IO ports (`pps0`, `pps1`) for X440 which allows modules inside the RFNoC image core to access the FPGA. Note that accessing the PPS signal is generally not required for RFNoC blocks which require access to timing. Co-authored-by: Martin Braun <martin.braun@ettus.com> Original-commit: c3525362643b56910692ad8ddc5d0e8cedd1869c	2024-06-11 10:20:07 +02:00
Jonathon Pendlum	83ad8e36ba	fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters Original-commit: 8444f84add04f025b7e24855e0ba79446e615e01	2022-02-10 18:11:41 -07:00

Author

SHA1

Message

Date

Jonathon PendlumandMartin Braun

d006250dc1

fpga: x400: Add PPS interface to X410/X440 BSP

This creates an IO port `pps` for X410, and two IO ports (`pps0`, `pps1`)
for X440 which allows modules inside the RFNoC image core to access the
FPGA. Note that accessing the PPS signal is generally not required for
RFNoC blocks which require access to timing.

Co-authored-by: Martin Braun <martin.braun@ettus.com>


Original-commit: c3525362643b56910692ad8ddc5d0e8cedd1869c

2024-06-11 10:20:07 +02:00

Jonathon Pendlum

83ad8e36ba

fpga: rfnoc: Add BLANK_OUTPUT to FIR filter block's parameters

Original-commit: 8444f84add04f025b7e24855e0ba79446e615e01

2022-02-10 18:11:41 -07:00