fpga: x300: sfpp: Fix warning about duplicate reg
This removes a duplicate code section that causes build warnings. It also references a wire that gets declared further down and the removed and remaining code sections were incorrectly indented. Original-commit: e8084eb4cb4ec6ff6476feb6e77ab3ea45dd969e
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@@ -395,16 +395,6 @@ generate
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.bist_checker_errors(bist_checker_errors)
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.bist_checker_errors(bist_checker_errors)
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);
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);
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reg mac_crit_err_latch;
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always @(posedge bus_clk) begin
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if (bus_rst | mac_clear) begin
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mac_crit_err_latch <= 1'b0;
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end else begin
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if (mac_crit_err_bclk)
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mac_crit_err_latch <= 1'b1;
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end
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end
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assign m_axis_tuser = 4'd0;
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assign m_axis_tuser = 4'd0;
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wire set_stb;
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wire set_stb;
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@@ -449,15 +439,15 @@ generate
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bist_lock_latency <= bist_lock_latency + 20'd1;
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bist_lock_latency <= bist_lock_latency + 20'd1;
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end
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end
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reg mac_crit_err_latch;
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reg mac_crit_err_latch;
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always @(posedge bus_clk) begin
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always @(posedge bus_clk) begin
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if (bus_rst | mac_clear) begin
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if (bus_rst | mac_clear) begin
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mac_crit_err_latch <= 1'b0;
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mac_crit_err_latch <= 1'b0;
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end else begin
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end else begin
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if (mac_crit_err_bclk)
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if (mac_crit_err_bclk)
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mac_crit_err_latch <= 1'b1;
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mac_crit_err_latch <= 1'b1;
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end
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end
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end
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end
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wire [31:0] core_status = {
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wire [31:0] core_status = {
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6'h0, //[31:26]
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6'h0, //[31:26]
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