fpga: x400: Add X440 200 MHz variant
This adds support for the X440_X4_200 variant which supports up to 200 MHz bandwidth (250 Msps), has a DDC and DUC on each channel, 4 x 10 GbE interfaces, and no DRAM. Original-commit: bdaba58750ce0c2ccc58769936c3c5c4a6b2d2cf
This commit is contained in:
Wade Fife
+7
-1
@@ -62,6 +62,7 @@ X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_40
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X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
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X440_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_FULL=1 DRAM_CH=0
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X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
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X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
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@@ -87,6 +88,7 @@ X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_
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X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
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X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
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X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
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X440_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_200_static_router.hex)
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X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex)
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X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex)
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X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex)
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X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex)
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X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex)
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X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex)
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@@ -227,6 +229,10 @@ X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,CG_400)
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$(call post_build,X410,CG_400)
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X440_X4_200: X440_IP build/usrp_x440_fpga_X4_200.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_200_DEFAULTS))
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$(call post_build,X440,X4_200)
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X440_X1_400: X440_IP build/usrp_x440_fpga_X1_400.dts
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X440_X1_400: X440_IP build/usrp_x440_fpga_X1_400.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
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$(call post_build,X440,X1_400)
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$(call post_build,X440,X1_400)
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@@ -276,7 +282,7 @@ X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts
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.DEFAULT_GOAL := all
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.DEFAULT_GOAL := all
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all: X410_X4_200 X410_CG_400 X410_UC_200 X440_X4_400 X440_CG_400 X440_X4_1600 X440_CG_1600 ##(Default targets)
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all: X410_X4_200 X410_CG_400 X410_UC_200 X440_X4_200 X440_X4_400 X440_CG_400 X440_X4_1600 X440_CG_1600 ##(Default targets)
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X410_IP: ##Build IP only.
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X410_IP: ##Build IP only.
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+$(call vivado_ip,X410,$(DEFS) X410=1)
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+$(call vivado_ip,X410,$(DEFS) X410=1)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,19 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for x440)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// Source: x440_200_rfnoc_image_core.yml
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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@@ -0,0 +1,181 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'x440' # USRP type
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image_core_name: 'x440_200' # Name to use for the RFNoC Image Core files
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default_target: 'X440_X4_200' # Default make target
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size_bytes: 262144 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep2:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep3:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep4:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep5:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep6:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep7:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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# A table of which crossbar routes to include
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# -------------------------------------------
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# Rows correspond to input ports and columns correspond to output ports.
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# Entering a 1 includes and a 0 removes that route from the crossbar.
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crossbar_routes:
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# eth0 eth2 eth4 ep0 ep2 ep4 ep6
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# eth1 eth3 dma ep1 ep3 ep5 ep7
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- [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0)
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- [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1)
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- [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2)
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- [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3)
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- [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC)
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- [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2)
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- [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3)
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 4
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NIPC: RADIO_NIPC
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 4
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NIPC: RADIO_NIPC
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duc0:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 4
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ddc0:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 4
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duc1:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 4
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ddc1:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 4
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A:0 TX
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- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
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# RF A:0 RX
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- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
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- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF A:1 TX
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- { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
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- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
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# RF A:1 RX
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- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
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- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
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# RF A:2 TX
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- { srcblk: ep2, srcport: out0, dstblk: duc0, dstport: in_2 }
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- { srcblk: duc0, srcport: out_2, dstblk: radio0, dstport: in_2 }
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# RF A:2 RX
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- { srcblk: radio0, srcport: out_2, dstblk: ddc0, dstport: in_2 }
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- { srcblk: ddc0, srcport: out_2, dstblk: ep2, dstport: in0 }
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# RF A:3 TX
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- { srcblk: ep3, srcport: out0, dstblk: duc0, dstport: in_3 }
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- { srcblk: duc0, srcport: out_3, dstblk: radio0, dstport: in_3 }
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# RF A:3 RX
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- { srcblk: radio0, srcport: out_3, dstblk: ddc0, dstport: in_3 }
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- { srcblk: ddc0, srcport: out_3, dstblk: ep3, dstport: in0 }
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#
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# RF B:0 TX
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- { srcblk: ep4, srcport: out0, dstblk: duc1, dstport: in_0 }
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- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
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# RF B:0 RX
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- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
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- { srcblk: ddc1, srcport: out_0, dstblk: ep4, dstport: in0 }
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# RF B:1 TX
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- { srcblk: ep5, srcport: out0, dstblk: duc1, dstport: in_1 }
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- { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
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# RF B:1 RX
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- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
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- { srcblk: ddc1, srcport: out_1, dstblk: ep5, dstport: in0 }
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# RF B:2 TX
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- { srcblk: ep6, srcport: out0, dstblk: duc1, dstport: in_2 }
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- { srcblk: duc1, srcport: out_2, dstblk: radio1, dstport: in_2 }
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# RF B:2 RX
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- { srcblk: radio1, srcport: out_2, dstblk: ddc1, dstport: in_2 }
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- { srcblk: ddc1, srcport: out_2, dstblk: ep6, dstport: in0 }
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# RF B:3 TX
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- { srcblk: ep7, srcport: out0, dstblk: duc1, dstport: in_3 }
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- { srcblk: duc1, srcport: out_3, dstblk: radio1, dstport: in_3 }
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# RF B:3 RX
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- { srcblk: radio1, srcport: out_3, dstblk: ddc1, dstport: in_3 }
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- { srcblk: ddc1, srcport: out_3, dstblk: ep7, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
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- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
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- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time }
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- { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
|
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- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
|
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@@ -0,0 +1,33 @@
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00000020
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004002c0
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02c00240
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02400300
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03000040
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008002c1
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02c10241
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02410301
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03010080
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00c002c2
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02c20242
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02420302
|
||||||
|
030200c0
|
||||||
|
010002c3
|
||||||
|
02c30243
|
||||||
|
02430303
|
||||||
|
03030100
|
||||||
|
01400340
|
||||||
|
03400280
|
||||||
|
02800380
|
||||||
|
03800140
|
||||||
|
01800341
|
||||||
|
03410281
|
||||||
|
02810381
|
||||||
|
03810180
|
||||||
|
01c00342
|
||||||
|
03420282
|
||||||
|
02820382
|
||||||
|
038201c0
|
||||||
|
02000343
|
||||||
|
03430283
|
||||||
|
02830383
|
||||||
|
03830200
|
||||||
Reference in New Issue
Block a user