From dbabc04cd92ab66cfd69d47a0f011dfe4a80c500 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Mon, 25 Sep 2023 22:00:49 -0500 Subject: [PATCH] fpga: x400: Add X440 200 MHz variant This adds support for the X440_X4_200 variant which supports up to 200 MHz bandwidth (250 Msps), has a DDC and DUC on each channel, 4 x 10 GbE interfaces, and no DRAM. Original-commit: bdaba58750ce0c2ccc58769936c3c5c4a6b2d2cf --- top/x400/Makefile | 8 +- top/x400/x440_200_rfnoc_image_core.v | 1587 ++++++++++++++++++++++++ top/x400/x440_200_rfnoc_image_core.vh | 19 + top/x400/x440_200_rfnoc_image_core.yml | 181 +++ top/x400/x440_200_static_router.hex | 33 + 5 files changed, 1827 insertions(+), 1 deletion(-) create mode 100644 top/x400/x440_200_rfnoc_image_core.v create mode 100644 top/x400/x440_200_rfnoc_image_core.vh create mode 100644 top/x400/x440_200_rfnoc_image_core.yml create mode 100644 top/x400/x440_200_static_router.hex diff --git a/top/x400/Makefile b/top/x400/Makefile index 0a53721..8e42aec 100644 --- a/top/x400/Makefile +++ b/top/x400/Makefile @@ -62,6 +62,7 @@ X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_40 X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 +X440_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_FULL=1 DRAM_CH=0 X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128 X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128 X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0 @@ -87,6 +88,7 @@ X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_ X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex) X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex) X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex) +X440_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_200_static_router.hex) X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex) X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex) X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex) @@ -227,6 +229,10 @@ X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) $(call post_build,X410,CG_400) +X440_X4_200: X440_IP build/usrp_x440_fpga_X4_200.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_200_DEFAULTS)) + $(call post_build,X440,X4_200) + X440_X1_400: X440_IP build/usrp_x440_fpga_X1_400.dts $(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS)) $(call post_build,X440,X1_400) @@ -276,7 +282,7 @@ X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts .DEFAULT_GOAL := all -all: X410_X4_200 X410_CG_400 X410_UC_200 X440_X4_400 X440_CG_400 X440_X4_1600 X440_CG_1600 ##(Default targets) +all: X410_X4_200 X410_CG_400 X410_UC_200 X440_X4_200 X440_X4_400 X440_CG_400 X440_X4_1600 X440_CG_1600 ##(Default targets) X410_IP: ##Build IP only. +$(call vivado_ip,X410,$(DEFS) X410=1) diff --git a/top/x400/x440_200_rfnoc_image_core.v b/top/x400/x440_200_rfnoc_image_core.v new file mode 100644 index 0000000..df322ab --- /dev/null +++ b/top/x400/x440_200_rfnoc_image_core.v @@ -0,0 +1,1587 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfnoc_image_core (for x440) +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_200_rfnoc_image_core.yml +// + +`default_nettype none + + +module rfnoc_image_core #( + parameter [31:0] CHDR_W = 64, + parameter [31:0] PORT_W = 64, + parameter [31:0] ETH0_W = 64, + parameter [31:0] ETH1_W = 64, + parameter [31:0] ETH2_W = 64, + parameter [31:0] ETH3_W = 64, + parameter [31:0] ETH4_W = 64, + parameter [31:0] DMA_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio0_clk, + input wire radio1_clk, + input wire radio0_2x_clk, + input wire radio1_2x_clk, + input wire dram_clk, + input wire ce_clk, + // Basic + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time0 + input wire [ 63:0] radio_time0, + // time1 + input wire [ 63:0] radio_time1, + // radio0 + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, + // radio1 + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [PORT_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [PORT_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [PORT_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [PORT_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (eth2) + input wire [PORT_W-1:0] s_eth2_tdata, + input wire s_eth2_tlast, + input wire s_eth2_tvalid, + output wire s_eth2_tready, + output wire [PORT_W-1:0] m_eth2_tdata, + output wire m_eth2_tlast, + output wire m_eth2_tvalid, + input wire m_eth2_tready, + // Transport 3 (eth3) + input wire [PORT_W-1:0] s_eth3_tdata, + input wire s_eth3_tlast, + input wire s_eth3_tvalid, + output wire s_eth3_tready, + output wire [PORT_W-1:0] m_eth3_tdata, + output wire m_eth3_tlast, + output wire m_eth3_tvalid, + input wire m_eth3_tready, + // Transport 4 (eth4) + input wire [PORT_W-1:0] s_eth4_tdata, + input wire s_eth4_tlast, + input wire s_eth4_tvalid, + output wire s_eth4_tready, + output wire [PORT_W-1:0] m_eth4_tdata, + output wire m_eth4_tlast, + output wire m_eth4_tvalid, + input wire m_eth4_tready, + // Transport 5 (dma) + input wire [PORT_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [PORT_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + localparam BLOCK_CHDR_W = 64; + localparam BYTE_MTU = MTU + $clog2(CHDR_W/8); + localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8); + localparam EP0_W = 64; + localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8); + localparam EP1_W = 64; + localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8); + localparam EP2_W = 64; + localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8); + localparam EP3_W = 64; + localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8); + localparam EP4_W = 64; + localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8); + localparam EP5_W = 64; + localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8); + localparam EP6_W = 64; + localparam EP6_MTU = BYTE_MTU - $clog2(EP6_W/8); + localparam EP7_W = 64; + localparam EP7_MTU = BYTE_MTU - $clog2(EP7_W/8); + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + + //--------------------------------------------------------------------------- + // CHDR Crossbar + //--------------------------------------------------------------------------- + + wire [PORT_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [PORT_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [PORT_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [PORT_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [PORT_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep4_tdata ; + wire xb_to_ep4_tlast ; + wire xb_to_ep4_tvalid; + wire xb_to_ep4_tready; + wire [PORT_W-1:0] ep4_to_xb_tdata ; + wire ep4_to_xb_tlast ; + wire ep4_to_xb_tvalid; + wire ep4_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep5_tdata ; + wire xb_to_ep5_tlast ; + wire xb_to_ep5_tvalid; + wire xb_to_ep5_tready; + wire [PORT_W-1:0] ep5_to_xb_tdata ; + wire ep5_to_xb_tlast ; + wire ep5_to_xb_tvalid; + wire ep5_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep6_tdata ; + wire xb_to_ep6_tlast ; + wire xb_to_ep6_tvalid; + wire xb_to_ep6_tready; + wire [PORT_W-1:0] ep6_to_xb_tdata ; + wire ep6_to_xb_tlast ; + wire ep6_to_xb_tvalid; + wire ep6_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep7_tdata ; + wire xb_to_ep7_tlast ; + wire xb_to_ep7_tvalid; + wire xb_to_ep7_tready; + wire [PORT_W-1:0] ep7_to_xb_tdata ; + wire ep7_to_xb_tlast ; + wire ep7_to_xb_tvalid; + wire ep7_to_xb_tready; + + chdr_crossbar_nxn #( + .PORT_W (PORT_W), + .NPORTS (14), + .CHDR_WIDTHS ({EP7_W, EP6_W, EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}), + .DEFAULT_PORT (0), + .ROUTES ({ 14'b00000000101111, + 14'b00000000101111, + 14'b00000000101111, + 14'b00000000101111, + 14'b00000000101111, + 14'b00000000101111, + 14'b00000000101111, + 14'b00000000101111, + 14'b11111111100000, + 14'b00000000000000, + 14'b11111111001000, + 14'b11111111000100, + 14'b11111111000010, + 14'b11111111000001 }), + .BYTE_MTU (BYTE_MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (6), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_crossbar_nxn_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep7_to_xb_tdata , ep6_to_xb_tdata , ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , {PORT_W{1'b0}}, s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep7_to_xb_tlast , ep6_to_xb_tlast , ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , 1'b0, s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }), + .s_axis_tvalid ({ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, 1'b0, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, 1'bZ, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep7_tdata , xb_to_ep6_tdata , xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , {PORT_W{1'bZ}}, m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep7_tlast , xb_to_ep6_tlast , xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , 1'bZ, m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }), + .m_axis_tvalid ({xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, 1'bZ, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, 1'b1, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + + //--------------------------------------------------------------------------- + // Stream Endpoints + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 32768; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); + + wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP0_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), + .MTU (EP0_MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 32768; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + + wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP1_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), + .MTU (EP1_MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP2 = 32768; + localparam INGRESS_BUFF_SIZE_EP2 = + REQ_BUFF_SIZE_EP2 == 0 ? 5 : + REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP2); + + wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; + wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP2_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), + .MTU (EP2_MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep2_tdata), + .s_axis_chdr_tlast (xb_to_ep2_tlast), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid), + .s_axis_chdr_tready (xb_to_ep2_tready), + .m_axis_chdr_tdata (ep2_to_xb_tdata), + .m_axis_chdr_tlast (ep2_to_xb_tlast), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid), + .m_axis_chdr_tready (ep2_to_xb_tready), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP3 = 32768; + localparam INGRESS_BUFF_SIZE_EP3 = + REQ_BUFF_SIZE_EP3 == 0 ? 5 : + REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP3); + + wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; + wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP3_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), + .MTU (EP3_MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep3_tdata), + .s_axis_chdr_tlast (xb_to_ep3_tlast), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid), + .s_axis_chdr_tready (xb_to_ep3_tready), + .m_axis_chdr_tdata (ep3_to_xb_tdata), + .m_axis_chdr_tlast (ep3_to_xb_tlast), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid), + .m_axis_chdr_tready (ep3_to_xb_tready), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP4 = 32768; + localparam INGRESS_BUFF_SIZE_EP4 = + REQ_BUFF_SIZE_EP4 == 0 ? 5 : + REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP4); + + wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata; + wire m_ep4_out0_tlast; + wire m_ep4_out0_tvalid; + wire m_ep4_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata; + wire s_ep4_in0_tlast; + wire s_ep4_in0_tvalid; + wire s_ep4_in0_tready; + wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; + wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; + wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; + wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP4_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (4), + .CTRL_XBAR_PORT (5), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), + .MTU (EP4_MTU), + .REPORT_STRM_ERRS (1) + ) ep4_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep4_tdata), + .s_axis_chdr_tlast (xb_to_ep4_tlast), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid), + .s_axis_chdr_tready (xb_to_ep4_tready), + .m_axis_chdr_tdata (ep4_to_xb_tdata), + .m_axis_chdr_tlast (ep4_to_xb_tlast), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid), + .m_axis_chdr_tready (ep4_to_xb_tready), + .s_axis_data_tdata ({s_ep4_in0_tdata}), + .s_axis_data_tlast ({s_ep4_in0_tlast}), + .s_axis_data_tvalid ({s_ep4_in0_tvalid}), + .s_axis_data_tready ({s_ep4_in0_tready}), + .m_axis_data_tdata ({m_ep4_out0_tdata}), + .m_axis_data_tlast ({m_ep4_out0_tlast}), + .m_axis_data_tvalid ({m_ep4_out0_tvalid}), + .m_axis_data_tready ({m_ep4_out0_tready}), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep4_ctrl_tready), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep4_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP5 = 32768; + localparam INGRESS_BUFF_SIZE_EP5 = + REQ_BUFF_SIZE_EP5 == 0 ? 5 : + REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP5); + + wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata; + wire m_ep5_out0_tlast; + wire m_ep5_out0_tvalid; + wire m_ep5_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata; + wire s_ep5_in0_tlast; + wire s_ep5_in0_tvalid; + wire s_ep5_in0_tready; + wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; + wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; + wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; + wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP5_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (5), + .CTRL_XBAR_PORT (6), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), + .MTU (EP5_MTU), + .REPORT_STRM_ERRS (1) + ) ep5_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep5_tdata), + .s_axis_chdr_tlast (xb_to_ep5_tlast), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid), + .s_axis_chdr_tready (xb_to_ep5_tready), + .m_axis_chdr_tdata (ep5_to_xb_tdata), + .m_axis_chdr_tlast (ep5_to_xb_tlast), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid), + .m_axis_chdr_tready (ep5_to_xb_tready), + .s_axis_data_tdata ({s_ep5_in0_tdata}), + .s_axis_data_tlast ({s_ep5_in0_tlast}), + .s_axis_data_tvalid ({s_ep5_in0_tvalid}), + .s_axis_data_tready ({s_ep5_in0_tready}), + .m_axis_data_tdata ({m_ep5_out0_tdata}), + .m_axis_data_tlast ({m_ep5_out0_tlast}), + .m_axis_data_tvalid ({m_ep5_out0_tvalid}), + .m_axis_data_tready ({m_ep5_out0_tready}), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep5_ctrl_tready), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep5_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP6 = 32768; + localparam INGRESS_BUFF_SIZE_EP6 = + REQ_BUFF_SIZE_EP6 == 0 ? 5 : + REQ_BUFF_SIZE_EP6 < 2*(2**EP6_MTU) ? EP6_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP6); + + wire [BLOCK_CHDR_W-1:0] m_ep6_out0_tdata; + wire m_ep6_out0_tlast; + wire m_ep6_out0_tvalid; + wire m_ep6_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep6_in0_tdata; + wire s_ep6_in0_tlast; + wire s_ep6_in0_tvalid; + wire s_ep6_in0_tready; + wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata; + wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast; + wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid; + wire m_ep6_ctrl_tready, s_ep6_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP6_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (6), + .CTRL_XBAR_PORT (7), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6), + .MTU (EP6_MTU), + .REPORT_STRM_ERRS (1) + ) ep6_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep6_tdata), + .s_axis_chdr_tlast (xb_to_ep6_tlast), + .s_axis_chdr_tvalid (xb_to_ep6_tvalid), + .s_axis_chdr_tready (xb_to_ep6_tready), + .m_axis_chdr_tdata (ep6_to_xb_tdata), + .m_axis_chdr_tlast (ep6_to_xb_tlast), + .m_axis_chdr_tvalid (ep6_to_xb_tvalid), + .m_axis_chdr_tready (ep6_to_xb_tready), + .s_axis_data_tdata ({s_ep6_in0_tdata}), + .s_axis_data_tlast ({s_ep6_in0_tlast}), + .s_axis_data_tvalid ({s_ep6_in0_tvalid}), + .s_axis_data_tready ({s_ep6_in0_tready}), + .m_axis_data_tdata ({m_ep6_out0_tdata}), + .m_axis_data_tlast ({m_ep6_out0_tlast}), + .m_axis_data_tvalid ({m_ep6_out0_tvalid}), + .m_axis_data_tready ({m_ep6_out0_tready}), + .s_axis_ctrl_tdata (s_ep6_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep6_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep6_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep6_ctrl_tready), + .m_axis_ctrl_tdata (m_ep6_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep6_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep6_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep6_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP7 = 32768; + localparam INGRESS_BUFF_SIZE_EP7 = + REQ_BUFF_SIZE_EP7 == 0 ? 5 : + REQ_BUFF_SIZE_EP7 < 2*(2**EP7_MTU) ? EP7_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP7); + + wire [BLOCK_CHDR_W-1:0] m_ep7_out0_tdata; + wire m_ep7_out0_tlast; + wire m_ep7_out0_tvalid; + wire m_ep7_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep7_in0_tdata; + wire s_ep7_in0_tlast; + wire s_ep7_in0_tvalid; + wire s_ep7_in0_tready; + wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata; + wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast; + wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid; + wire m_ep7_ctrl_tready, s_ep7_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP7_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (7), + .CTRL_XBAR_PORT (8), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7), + .MTU (EP7_MTU), + .REPORT_STRM_ERRS (1) + ) ep7_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep7_tdata), + .s_axis_chdr_tlast (xb_to_ep7_tlast), + .s_axis_chdr_tvalid (xb_to_ep7_tvalid), + .s_axis_chdr_tready (xb_to_ep7_tready), + .m_axis_chdr_tdata (ep7_to_xb_tdata), + .m_axis_chdr_tlast (ep7_to_xb_tlast), + .m_axis_chdr_tvalid (ep7_to_xb_tvalid), + .m_axis_chdr_tready (ep7_to_xb_tready), + .s_axis_data_tdata ({s_ep7_in0_tdata}), + .s_axis_data_tlast ({s_ep7_in0_tlast}), + .s_axis_data_tvalid ({s_ep7_in0_tvalid}), + .s_axis_data_tready ({s_ep7_in0_tready}), + .m_axis_data_tdata ({m_ep7_out0_tdata}), + .m_axis_data_tlast ({m_ep7_out0_tlast}), + .m_axis_data_tvalid ({m_ep7_out0_tvalid}), + .m_axis_data_tready ({m_ep7_out0_tready}), + .s_axis_ctrl_tdata (s_ep7_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep7_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep7_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep7_ctrl_tready), + .m_axis_ctrl_tdata (m_ep7_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep7_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep7_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep7_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + + //--------------------------------------------------------------------------- + // Control Crossbar + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata, s_duc0_ctrl_tdata; + wire m_duc0_ctrl_tlast, s_duc0_ctrl_tlast; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata, s_ddc0_ctrl_tdata; + wire m_ddc0_ctrl_tlast, s_ddc0_ctrl_tlast; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata, s_duc1_ctrl_tdata; + wire m_duc1_ctrl_tlast, s_duc1_ctrl_tlast; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata, s_ddc1_ctrl_tdata; + wire m_ddc1_ctrl_tlast, s_ddc1_ctrl_tlast; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (8), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + + //--------------------------------------------------------------------------- + // RFNoC Core Kernel + //--------------------------------------------------------------------------- + + wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'hA400), + .DEVICE_FAMILY ("ULTRASCALE"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (6), + .NUM_STREAM_ENDPOINTS(8), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (6), + .NUM_EDGES (32), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + + //--------------------------------------------------------------------------- + // Blocks + //--------------------------------------------------------------------------- + + //----------------------------------- + // radio0 + //----------------------------------- + + wire radio0_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio0_in_3_tdata , s_radio0_in_2_tdata , s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_3_tlast , s_radio0_in_2_tlast , s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_3_tvalid, s_radio0_in_2_tvalid, s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_3_tready, s_radio0_in_2_tready, s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio0_out_3_tdata , m_radio0_out_2_tdata , m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_3_tlast , m_radio0_out_2_tlast , m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_3_tvalid, m_radio0_out_2_tvalid, m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_3_tready, m_radio0_out_2_tready, m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrlport + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time + wire [ 63:0] radio0_radio_time; + // radio + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (2), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_3_tdata , s_radio0_in_2_tdata , s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_3_tlast , s_radio0_in_2_tlast , s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_3_tvalid, s_radio0_in_2_tvalid, s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_3_tready, s_radio0_in_2_tready, s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_3_tdata , m_radio0_out_2_tdata , m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_3_tlast , m_radio0_out_2_tlast , m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_3_tvalid, m_radio0_out_2_tvalid, m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_3_tready, m_radio0_out_2_tready, m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) + ); + + //----------------------------------- + // radio1 + //----------------------------------- + + wire radio1_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio1_in_3_tdata , s_radio1_in_2_tdata , s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_3_tlast , s_radio1_in_2_tlast , s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_3_tvalid, s_radio1_in_2_tvalid, s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_3_tready, s_radio1_in_2_tready, s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio1_out_3_tdata , m_radio1_out_2_tdata , m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_3_tlast , m_radio1_out_2_tlast , m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_3_tvalid, m_radio1_out_2_tvalid, m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_3_tready, m_radio1_out_2_tready, m_radio1_out_1_tready, m_radio1_out_0_tready; + + // ctrlport + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time + wire [ 63:0] radio1_radio_time; + // radio + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (3), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio1_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_3_tdata , s_radio1_in_2_tdata , s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_3_tlast , s_radio1_in_2_tlast , s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_3_tvalid, s_radio1_in_2_tvalid, s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_3_tready, s_radio1_in_2_tready, s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_3_tdata , m_radio1_out_2_tdata , m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_3_tlast , m_radio1_out_2_tlast , m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_3_tvalid, m_radio1_out_2_tvalid, m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_3_tready, m_radio1_out_2_tready, m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) + ); + + //----------------------------------- + // duc0 + //----------------------------------- + + wire duc0_ce_clk; + wire [BLOCK_CHDR_W-1:0] s_duc0_in_3_tdata , s_duc0_in_2_tdata , s_duc0_in_1_tdata , s_duc0_in_0_tdata ; + wire s_duc0_in_3_tlast , s_duc0_in_2_tlast , s_duc0_in_1_tlast , s_duc0_in_0_tlast ; + wire s_duc0_in_3_tvalid, s_duc0_in_2_tvalid, s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; + wire s_duc0_in_3_tready, s_duc0_in_2_tready, s_duc0_in_1_tready, s_duc0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_duc0_out_3_tdata , m_duc0_out_2_tdata , m_duc0_out_1_tdata , m_duc0_out_0_tdata ; + wire m_duc0_out_3_tlast , m_duc0_out_2_tlast , m_duc0_out_1_tlast , m_duc0_out_0_tlast ; + wire m_duc0_out_3_tvalid, m_duc0_out_2_tvalid, m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; + wire m_duc0_out_3_tready, m_duc0_out_2_tready, m_duc0_out_1_tready, m_duc0_out_0_tready; + + rfnoc_block_duc #( + .THIS_PORTID (4), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NUM_HB (3), + .CIC_MAX_INTERP (255), + .MTU (BLOCK_MTU) + ) b_duc0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .s_rfnoc_chdr_tdata ({s_duc0_in_3_tdata , s_duc0_in_2_tdata , s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_3_tlast , s_duc0_in_2_tlast , s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_duc0_in_3_tvalid, s_duc0_in_2_tvalid, s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_duc0_in_3_tready, s_duc0_in_2_tready, s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_3_tdata , m_duc0_out_2_tdata , m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_3_tlast , m_duc0_out_2_tlast , m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_duc0_out_3_tvalid, m_duc0_out_2_tvalid, m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_duc0_out_3_tready, m_duc0_out_2_tready, m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) + ); + + //----------------------------------- + // ddc0 + //----------------------------------- + + wire ddc0_ce_clk; + wire [BLOCK_CHDR_W-1:0] s_ddc0_in_3_tdata , s_ddc0_in_2_tdata , s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; + wire s_ddc0_in_3_tlast , s_ddc0_in_2_tlast , s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; + wire s_ddc0_in_3_tvalid, s_ddc0_in_2_tvalid, s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; + wire s_ddc0_in_3_tready, s_ddc0_in_2_tready, s_ddc0_in_1_tready, s_ddc0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_ddc0_out_3_tdata , m_ddc0_out_2_tdata , m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; + wire m_ddc0_out_3_tlast , m_ddc0_out_2_tlast , m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; + wire m_ddc0_out_3_tvalid, m_ddc0_out_2_tvalid, m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; + wire m_ddc0_out_3_tready, m_ddc0_out_2_tready, m_ddc0_out_1_tready, m_ddc0_out_0_tready; + + rfnoc_block_ddc #( + .THIS_PORTID (5), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NUM_HB (3), + .CIC_MAX_DECIM (255), + .MTU (BLOCK_MTU) + ) b_ddc0_3 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + .s_rfnoc_chdr_tdata ({s_ddc0_in_3_tdata , s_ddc0_in_2_tdata , s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_3_tlast , s_ddc0_in_2_tlast , s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_ddc0_in_3_tvalid, s_ddc0_in_2_tvalid, s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_ddc0_in_3_tready, s_ddc0_in_2_tready, s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_3_tdata , m_ddc0_out_2_tdata , m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_3_tlast , m_ddc0_out_2_tlast , m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_ddc0_out_3_tvalid, m_ddc0_out_2_tvalid, m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_ddc0_out_3_tready, m_ddc0_out_2_tready, m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) + ); + + //----------------------------------- + // duc1 + //----------------------------------- + + wire duc1_ce_clk; + wire [BLOCK_CHDR_W-1:0] s_duc1_in_3_tdata , s_duc1_in_2_tdata , s_duc1_in_1_tdata , s_duc1_in_0_tdata ; + wire s_duc1_in_3_tlast , s_duc1_in_2_tlast , s_duc1_in_1_tlast , s_duc1_in_0_tlast ; + wire s_duc1_in_3_tvalid, s_duc1_in_2_tvalid, s_duc1_in_1_tvalid, s_duc1_in_0_tvalid; + wire s_duc1_in_3_tready, s_duc1_in_2_tready, s_duc1_in_1_tready, s_duc1_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_duc1_out_3_tdata , m_duc1_out_2_tdata , m_duc1_out_1_tdata , m_duc1_out_0_tdata ; + wire m_duc1_out_3_tlast , m_duc1_out_2_tlast , m_duc1_out_1_tlast , m_duc1_out_0_tlast ; + wire m_duc1_out_3_tvalid, m_duc1_out_2_tvalid, m_duc1_out_1_tvalid, m_duc1_out_0_tvalid; + wire m_duc1_out_3_tready, m_duc1_out_2_tready, m_duc1_out_1_tready, m_duc1_out_0_tready; + + rfnoc_block_duc #( + .THIS_PORTID (6), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NUM_HB (3), + .CIC_MAX_INTERP (255), + .MTU (BLOCK_MTU) + ) b_duc1_4 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + .s_rfnoc_chdr_tdata ({s_duc1_in_3_tdata , s_duc1_in_2_tdata , s_duc1_in_1_tdata , s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_3_tlast , s_duc1_in_2_tlast , s_duc1_in_1_tlast , s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_duc1_in_3_tvalid, s_duc1_in_2_tvalid, s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_duc1_in_3_tready, s_duc1_in_2_tready, s_duc1_in_1_tready, s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_3_tdata , m_duc1_out_2_tdata , m_duc1_out_1_tdata , m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_3_tlast , m_duc1_out_2_tlast , m_duc1_out_1_tlast , m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_duc1_out_3_tvalid, m_duc1_out_2_tvalid, m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_duc1_out_3_tready, m_duc1_out_2_tready, m_duc1_out_1_tready, m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_duc1_ctrl_tready) + ); + + //----------------------------------- + // ddc1 + //----------------------------------- + + wire ddc1_ce_clk; + wire [BLOCK_CHDR_W-1:0] s_ddc1_in_3_tdata , s_ddc1_in_2_tdata , s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; + wire s_ddc1_in_3_tlast , s_ddc1_in_2_tlast , s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; + wire s_ddc1_in_3_tvalid, s_ddc1_in_2_tvalid, s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; + wire s_ddc1_in_3_tready, s_ddc1_in_2_tready, s_ddc1_in_1_tready, s_ddc1_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_ddc1_out_3_tdata , m_ddc1_out_2_tdata , m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; + wire m_ddc1_out_3_tlast , m_ddc1_out_2_tlast , m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; + wire m_ddc1_out_3_tvalid, m_ddc1_out_2_tvalid, m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; + wire m_ddc1_out_3_tready, m_ddc1_out_2_tready, m_ddc1_out_1_tready, m_ddc1_out_0_tready; + + rfnoc_block_ddc #( + .THIS_PORTID (7), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NUM_HB (3), + .CIC_MAX_DECIM (255), + .MTU (BLOCK_MTU) + ) b_ddc1_5 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk (ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + .s_rfnoc_chdr_tdata ({s_ddc1_in_3_tdata , s_ddc1_in_2_tdata , s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_3_tlast , s_ddc1_in_2_tlast , s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_ddc1_in_3_tvalid, s_ddc1_in_2_tvalid, s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_ddc1_in_3_tready, s_ddc1_in_2_tready, s_ddc1_in_1_tready, s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_3_tdata , m_ddc1_out_2_tdata , m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_3_tlast , m_ddc1_out_2_tlast , m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_ddc1_out_3_tvalid, m_ddc1_out_2_tvalid, m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_ddc1_out_3_tready, m_ddc1_out_2_tready, m_ddc1_out_1_tready, m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready) + ); + + //--------------------------------------------------------------------------- + // Static Router + //--------------------------------------------------------------------------- + + assign s_duc0_in_0_tdata = m_ep0_out0_tdata; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc0_in_1_tdata = m_ep1_out0_tdata; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast; + assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc0_in_1_tready; + + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast; + assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; + assign m_duc0_out_1_tready = s_radio0_in_1_tready; + + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast; + assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ddc0_in_1_tready; + + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast; + assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; + assign m_ddc0_out_1_tready = s_ep1_in0_tready; + + assign s_duc0_in_2_tdata = m_ep2_out0_tdata; + assign s_duc0_in_2_tlast = m_ep2_out0_tlast; + assign s_duc0_in_2_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_duc0_in_2_tready; + + assign s_radio0_in_2_tdata = m_duc0_out_2_tdata; + assign s_radio0_in_2_tlast = m_duc0_out_2_tlast; + assign s_radio0_in_2_tvalid = m_duc0_out_2_tvalid; + assign m_duc0_out_2_tready = s_radio0_in_2_tready; + + assign s_ddc0_in_2_tdata = m_radio0_out_2_tdata; + assign s_ddc0_in_2_tlast = m_radio0_out_2_tlast; + assign s_ddc0_in_2_tvalid = m_radio0_out_2_tvalid; + assign m_radio0_out_2_tready = s_ddc0_in_2_tready; + + assign s_ep2_in0_tdata = m_ddc0_out_2_tdata; + assign s_ep2_in0_tlast = m_ddc0_out_2_tlast; + assign s_ep2_in0_tvalid = m_ddc0_out_2_tvalid; + assign m_ddc0_out_2_tready = s_ep2_in0_tready; + + assign s_duc0_in_3_tdata = m_ep3_out0_tdata; + assign s_duc0_in_3_tlast = m_ep3_out0_tlast; + assign s_duc0_in_3_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_duc0_in_3_tready; + + assign s_radio0_in_3_tdata = m_duc0_out_3_tdata; + assign s_radio0_in_3_tlast = m_duc0_out_3_tlast; + assign s_radio0_in_3_tvalid = m_duc0_out_3_tvalid; + assign m_duc0_out_3_tready = s_radio0_in_3_tready; + + assign s_ddc0_in_3_tdata = m_radio0_out_3_tdata; + assign s_ddc0_in_3_tlast = m_radio0_out_3_tlast; + assign s_ddc0_in_3_tvalid = m_radio0_out_3_tvalid; + assign m_radio0_out_3_tready = s_ddc0_in_3_tready; + + assign s_ep3_in0_tdata = m_ddc0_out_3_tdata; + assign s_ep3_in0_tlast = m_ddc0_out_3_tlast; + assign s_ep3_in0_tvalid = m_ddc0_out_3_tvalid; + assign m_ddc0_out_3_tready = s_ep3_in0_tready; + + assign s_duc1_in_0_tdata = m_ep4_out0_tdata; + assign s_duc1_in_0_tlast = m_ep4_out0_tlast; + assign s_duc1_in_0_tvalid = m_ep4_out0_tvalid; + assign m_ep4_out0_tready = s_duc1_in_0_tready; + + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast; + assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; + assign m_duc1_out_0_tready = s_radio1_in_0_tready; + + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast; + assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ddc1_in_0_tready; + + assign s_ep4_in0_tdata = m_ddc1_out_0_tdata; + assign s_ep4_in0_tlast = m_ddc1_out_0_tlast; + assign s_ep4_in0_tvalid = m_ddc1_out_0_tvalid; + assign m_ddc1_out_0_tready = s_ep4_in0_tready; + + assign s_duc1_in_1_tdata = m_ep5_out0_tdata; + assign s_duc1_in_1_tlast = m_ep5_out0_tlast; + assign s_duc1_in_1_tvalid = m_ep5_out0_tvalid; + assign m_ep5_out0_tready = s_duc1_in_1_tready; + + assign s_radio1_in_1_tdata = m_duc1_out_1_tdata; + assign s_radio1_in_1_tlast = m_duc1_out_1_tlast; + assign s_radio1_in_1_tvalid = m_duc1_out_1_tvalid; + assign m_duc1_out_1_tready = s_radio1_in_1_tready; + + assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata; + assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast; + assign s_ddc1_in_1_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ddc1_in_1_tready; + + assign s_ep5_in0_tdata = m_ddc1_out_1_tdata; + assign s_ep5_in0_tlast = m_ddc1_out_1_tlast; + assign s_ep5_in0_tvalid = m_ddc1_out_1_tvalid; + assign m_ddc1_out_1_tready = s_ep5_in0_tready; + + assign s_duc1_in_2_tdata = m_ep6_out0_tdata; + assign s_duc1_in_2_tlast = m_ep6_out0_tlast; + assign s_duc1_in_2_tvalid = m_ep6_out0_tvalid; + assign m_ep6_out0_tready = s_duc1_in_2_tready; + + assign s_radio1_in_2_tdata = m_duc1_out_2_tdata; + assign s_radio1_in_2_tlast = m_duc1_out_2_tlast; + assign s_radio1_in_2_tvalid = m_duc1_out_2_tvalid; + assign m_duc1_out_2_tready = s_radio1_in_2_tready; + + assign s_ddc1_in_2_tdata = m_radio1_out_2_tdata; + assign s_ddc1_in_2_tlast = m_radio1_out_2_tlast; + assign s_ddc1_in_2_tvalid = m_radio1_out_2_tvalid; + assign m_radio1_out_2_tready = s_ddc1_in_2_tready; + + assign s_ep6_in0_tdata = m_ddc1_out_2_tdata; + assign s_ep6_in0_tlast = m_ddc1_out_2_tlast; + assign s_ep6_in0_tvalid = m_ddc1_out_2_tvalid; + assign m_ddc1_out_2_tready = s_ep6_in0_tready; + + assign s_duc1_in_3_tdata = m_ep7_out0_tdata; + assign s_duc1_in_3_tlast = m_ep7_out0_tlast; + assign s_duc1_in_3_tvalid = m_ep7_out0_tvalid; + assign m_ep7_out0_tready = s_duc1_in_3_tready; + + assign s_radio1_in_3_tdata = m_duc1_out_3_tdata; + assign s_radio1_in_3_tlast = m_duc1_out_3_tlast; + assign s_radio1_in_3_tvalid = m_duc1_out_3_tvalid; + assign m_duc1_out_3_tready = s_radio1_in_3_tready; + + assign s_ddc1_in_3_tdata = m_radio1_out_3_tdata; + assign s_ddc1_in_3_tlast = m_radio1_out_3_tlast; + assign s_ddc1_in_3_tvalid = m_radio1_out_3_tvalid; + assign m_radio1_out_3_tready = s_ddc1_in_3_tready; + + assign s_ep7_in0_tdata = m_ddc1_out_3_tdata; + assign s_ep7_in0_tlast = m_ddc1_out_3_tlast; + assign s_ep7_in0_tvalid = m_ddc1_out_3_tvalid; + assign m_ddc1_out_3_tready = s_ep7_in0_tready; + + + //--------------------------------------------------------------------------- + // Unused Ports + //--------------------------------------------------------------------------- + + + + //--------------------------------------------------------------------------- + // Clock Domains + //--------------------------------------------------------------------------- + + assign radio0_radio_clk = radio0_clk; + assign radio1_radio_clk = radio1_clk; + assign duc0_ce_clk = ce_clk; + assign ddc0_ce_clk = ce_clk; + assign duc1_ce_clk = ce_clk; + assign ddc1_ce_clk = ce_clk; + + + //--------------------------------------------------------------------------- + // IO Port Connection + //--------------------------------------------------------------------------- + + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time0; + + assign radio1_radio_time = radio_time1; + +endmodule + + +`default_nettype wire diff --git a/top/x400/x440_200_rfnoc_image_core.vh b/top/x400/x440_200_rfnoc_image_core.vh new file mode 100644 index 0000000..e348162 --- /dev/null +++ b/top/x400/x440_200_rfnoc_image_core.vh @@ -0,0 +1,19 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Header: rfnoc_image_core.vh (for x440) +// +// Description: +// +// This is the header file for the RFNoC Image Core. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_200_rfnoc_image_core.yml +// + +`define CHDR_WIDTH 64 +`define RFNOC_PROTOVER { 8'd1, 8'd0 } diff --git a/top/x400/x440_200_rfnoc_image_core.yml b/top/x400/x440_200_rfnoc_image_core.yml new file mode 100644 index 0000000..7c3a350 --- /dev/null +++ b/top/x400/x440_200_rfnoc_image_core.yml @@ -0,0 +1,181 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: >- # Copyright information used in file headers + Copyright 2023 Ettus Research, a National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later +version: '1.0' # File version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'x440' # USRP type +image_core_name: 'x440_200' # Name to use for the RFNoC Image Core files +default_target: 'X440_X4_200' # Default make target + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size_bytes: 262144 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size_bytes: 262144 + ep2: + ctrl: False + data: True + buff_size_bytes: 262144 + ep3: + ctrl: False + data: True + buff_size_bytes: 262144 + ep4: + ctrl: False + data: True + buff_size_bytes: 262144 + ep5: + ctrl: False + data: True + buff_size_bytes: 262144 + ep6: + ctrl: False + data: True + buff_size_bytes: 262144 + ep7: + ctrl: False + data: True + buff_size_bytes: 262144 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 eth2 eth4 ep0 ep2 ep4 ep6 + # eth1 eth3 dma ep1 ep3 ep5 ep7 + - [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0) + - [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1) + - [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2) + - [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3) + - [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC) + - [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3) + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 4 + NIPC: RADIO_NIPC + radio1: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 4 + NIPC: RADIO_NIPC + duc0: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 4 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 4 + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 4 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 4 + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # RF A:0 TX + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # RF A:0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF A:1 TX + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } + - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + # RF A:1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } + - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + # RF A:2 TX + - { srcblk: ep2, srcport: out0, dstblk: duc0, dstport: in_2 } + - { srcblk: duc0, srcport: out_2, dstblk: radio0, dstport: in_2 } + # RF A:2 RX + - { srcblk: radio0, srcport: out_2, dstblk: ddc0, dstport: in_2 } + - { srcblk: ddc0, srcport: out_2, dstblk: ep2, dstport: in0 } + # RF A:3 TX + - { srcblk: ep3, srcport: out0, dstblk: duc0, dstport: in_3 } + - { srcblk: duc0, srcport: out_3, dstblk: radio0, dstport: in_3 } + # RF A:3 RX + - { srcblk: radio0, srcport: out_3, dstblk: ddc0, dstport: in_3 } + - { srcblk: ddc0, srcport: out_3, dstblk: ep3, dstport: in0 } + # + # RF B:0 TX + - { srcblk: ep4, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + # RF B:0 RX + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep4, dstport: in0 } + # RF B:1 TX + - { srcblk: ep5, srcport: out0, dstblk: duc1, dstport: in_1 } + - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 } + # RF B:1 RX + - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 } + - { srcblk: ddc1, srcport: out_1, dstblk: ep5, dstport: in0 } + # RF B:2 TX + - { srcblk: ep6, srcport: out0, dstblk: duc1, dstport: in_2 } + - { srcblk: duc1, srcport: out_2, dstblk: radio1, dstport: in_2 } + # RF B:2 RX + - { srcblk: radio1, srcport: out_2, dstblk: ddc1, dstport: in_2 } + - { srcblk: ddc1, srcport: out_2, dstblk: ep6, dstport: in0 } + # RF B:3 TX + - { srcblk: ep7, srcport: out0, dstblk: duc1, dstport: in_3 } + - { srcblk: duc1, srcport: out_3, dstblk: radio1, dstport: in_3 } + # RF B:3 RX + - { srcblk: radio1, srcport: out_3, dstblk: ddc1, dstport: in_3 } + - { srcblk: ddc1, srcport: out_3, dstblk: ep7, dstport: in0 } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce } diff --git a/top/x400/x440_200_static_router.hex b/top/x400/x440_200_static_router.hex new file mode 100644 index 0000000..247f87b --- /dev/null +++ b/top/x400/x440_200_static_router.hex @@ -0,0 +1,33 @@ +00000020 +004002c0 +02c00240 +02400300 +03000040 +008002c1 +02c10241 +02410301 +03010080 +00c002c2 +02c20242 +02420302 +030200c0 +010002c3 +02c30243 +02430303 +03030100 +01400340 +03400280 +02800380 +03800140 +01800341 +03410281 +02810381 +03810180 +01c00342 +03420282 +02820382 +038201c0 +02000343 +03430283 +02830383 +03830200