fpga: Remove dupes from DESIGN_SRCS

In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.


Original-commit: 1944263412d329d53b32a17e9735b79e59e319d7
This commit is contained in:
Martin Braun
2023-12-13 17:28:09 -06:00
committed by Wade Fife
parent ce0ddc6dac
commit c98c7ab88d
2 changed files with 5 additions and 2 deletions
+2 -2
View File
@@ -24,7 +24,7 @@ BUILD_VIVADO_DESIGN = \
export VIV_TOP_MODULE=$(2); \
export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
export VIV_MODE=$(VIVADO_MODE); \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
cd $(BUILD_DIR); \
$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
@@ -49,7 +49,7 @@ CHECK_VIVADO_DESIGN = \
export VIV_TOP_MODULE=$(2); \
export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
export VIV_MODE=$(VIVADO_MODE); \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \
cd $(BUILD_DIR); \
$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
+3
View File
@@ -13,6 +13,9 @@ RESOLVE_PATH = $(1)
RESOLVE_PATHS = "$(1)"
endif
# A function that removes duplicate entries from lists without changing its order
uniq = $(if $1,$(firstword $1) $(call uniq,$(filter-out $(firstword $1),$1)))
# -------------------------------------------------------------------
# Project Setup
# -------------------------------------------------------------------