diff --git a/tools/make/viv_design_builder.mak b/tools/make/viv_design_builder.mak
index 3ca44b0..9443227 100644
--- a/tools/make/viv_design_builder.mak
+++ b/tools/make/viv_design_builder.mak
@@ -24,7 +24,7 @@ BUILD_VIVADO_DESIGN = \
 	export VIV_TOP_MODULE=$(2); \
 	export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
 	export VIV_MODE=$(VIVADO_MODE); \
-	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
+	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	cd $(BUILD_DIR); \
 	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
@@ -49,7 +49,7 @@ CHECK_VIVADO_DESIGN = \
 	export VIV_TOP_MODULE=$(2); \
 	export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
 	export VIV_MODE=$(VIVADO_MODE); \
-	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \
+	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \
 	cd $(BUILD_DIR); \
 	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
diff --git a/tools/make/viv_preamble.mak b/tools/make/viv_preamble.mak
index df0f271..8469c05 100644
--- a/tools/make/viv_preamble.mak
+++ b/tools/make/viv_preamble.mak
@@ -13,6 +13,9 @@ RESOLVE_PATH = $(1)
 RESOLVE_PATHS = "$(1)"
 endif
 
+# A function that removes duplicate entries from lists without changing its order
+uniq = $(if $1,$(firstword $1) $(call uniq,$(filter-out $(firstword $1),$1)))
+
 # -------------------------------------------------------------------
 # Project Setup
 # -------------------------------------------------------------------