miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: Remove dupes from DESIGN_SRCS

Browse Source 
In the build Makefiles, this adds a function (uniq) which removes
duplicate entries from lists. We apply this to the DESIGN_SRCS passed
to the Vivado build process. This eliminates some warnings from
duplicate source files caused by redundantly referencing source files in
the Makefiles, possibly because they are listed in more than one source
file variable.


Original-commit: 1944263412d329d53b32a17e9735b79e59e319d7
This commit is contained in:
Martin Braun
2023-12-13 17:28:09 -06:00
committed by Wade Fife
parent ce0ddc6dac
commit c98c7ab88d
2 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/make/viv_preamble.mak
+3
View File
@@ -13,6 +13,9 @@ RESOLVE_PATH = $(1)
RESOLVE_PATHS = "$(1)"
endif
# A function that removes duplicate entries from lists without changing its order
uniq = $(if $1,$(firstword $1) $(call uniq,$(filter-out $(firstword $1),$1)))
# -------------------------------------------------------------------
# Project Setup
# -------------------------------------------------------------------