miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: n3xx: Update AXI interconnect address range

Browse Source 
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: c6bb9924e56664ccb337694f8ef485ba8245edfd
This commit is contained in:
Wade Fife
2020-08-28 15:07:38 -05:00
parent 7e3f04d0ab
commit bd5d539bc2
4 changed files with 2217 additions and 2928 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd
+1368 -2191
View File
File diff suppressed because it is too large Load Diff
top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml
+5 -4
View File
@@ -1,10 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="33">
<Root MajorVersion="0" MinorVersion="37">
<CompositeFile CompositeFileTopName="axi_intercon_4x64_256_bd" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1501543653"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1501543653"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1501543653"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1591253143"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1591253143"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1591253143"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/axi_intercon_4x64_256_bd_m00_rs_0/axi_intercon_4x64_256_bd_m00_rs_0.xci" Type="IP">
<Instance HierarchyPath="m00_rs"/>