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mpm/fpga: x4xx: Major updates in preparation for future devices

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FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
This commit is contained in:
Javier Valenzuela
2023-05-23 09:06:17 +02:00
committed by Martin Braun
co-authored by Wade Fife Ryan Marlow Martin Braun Humberto Jimenez
parent ffdcc016cc
commit adf6f576c6
79 changed files with 41079 additions and 2315 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/Makefile
+51 -52
View File
@@ -42,26 +42,26 @@ QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10Gb
QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
# Target specific variables
X410_IP: DEFS += $(QSFP0_10GBE) RFBW_100M=1
X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0
X410_C1_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_100: DEFS += $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_C1_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_200: DEFS += $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0
X410_X1_400: DEFS += $(QSFP0_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_X4_400: DEFS += $(QSFP0_4X10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0
X410_UC_400: DEFS += $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0
X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100
X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=0
X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64
X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=0
X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128
X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
# exclude it. Note that some targets exclude it regardless of this setting.
@@ -78,8 +78,7 @@ X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core
X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex)
X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
# Option to stop after RTL elaboration. Use this flag as a synthesis check.
ifndef TARGET
@@ -112,27 +111,27 @@ endif
##
##Available Targets
##-------------|-----------|-----------------|-----------------|------------
##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
##-------------|-----------|-----------------|-----------------|------------
##X410_X1_100 | 100 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_100 | 100 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_100 | 100 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_100 | 100 MHz | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_100 | 100 MHz | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_100 | 100 MHz | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_200 | 200 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_200 | 200 MHz | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_200 | 200 MHz | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_200 | 200 MHz | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_400 | 400 MHz | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
##X410_XG_400 | 400 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
##X410_X4_400 | 400 MHz | 4 x 10 GbE | Unused | 128b x 4 Ch
##X410_C1_400 | 400 MHz | 100 GbE | Unused | Unused
##X410_UC_400 | 400 MHz | Unused | 100 GbE | Unused
##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | Unused
##-------------|-----------|----|-----------------|-----------------|------------
##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
##-------------|-----------|----|-----------------|-----------------|------------
##X410_X1_100 | 100 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_100 | 100 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_100 | 100 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_100 | 100 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_100 | 100 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_100 | 100 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_200 | 200 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
##X410_XG_200 | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
##X410_X4_200 | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
##X410_X4C_200 | 200 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
##X410_C1_200 | 200 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
##X410_UC_200 | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
##X410_X1_400 | 400 MHz | 4 | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
##X410_XG_400 | 400 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
##X410_X4_400 | 400 MHz | 4 | 4 x 10 GbE | Unused | 128b x 4 Ch
##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused
##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused
##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
##* Note: Not all targets are shipped with UHD.
##* Note: Some YAML configurations might not use all available DRAM channels.
@@ -185,15 +184,15 @@ X410_UC_200: X410_IP build/usrp_x410_fpga_UC_200.dts
$(call post_build,X410,UC_200)
X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
$(call post_build,X410,X1_400)
X410_XG_400: X410_IP build/usrp_x410_fpga_XG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
$(call post_build,X410,XG_400)
X410_X4_400: X410_IP build/usrp_x410_fpga_X4_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
$(call post_build,X410,X4_400)
X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts
@@ -210,10 +209,10 @@ X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
##
##Experimental Targets
##-------------|-----------|-----------------|-----------------|------------
##Target | Bandwidth | QSFP0 | QSFP1 | DRAM
##-------------|-----------|-----------------|-----------------|------------
##X410_CG_200 | 200 | 100 GbE | 100 GbE | 64b x 4 Ch
##-------------|-----------|----|-----------------|-----------------|------------
##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
##-------------|-----------|----|-----------------|-----------------|------------
##X410_CG_200 | 200 | 4 | 100 GbE | 100 GbE | 64b x 4 Ch
X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
@@ -230,10 +229,10 @@ all: X410_X4_200 X410_CG_400 X410_UC_200 ##(Default targets)
X410_IP: ##Build IP only.
+$(call vivado_ip,X410,$(DEFS) X410=1)
build/%.dts: dts/*.dts dts/*.dtsi
build/usrp_x410%.dts: dts/*.dts dts/*.dtsi
-mkdir -p build
tools/parse_versions_for_dts.py \
--input regmap/versioning_regs_regmap_utils.vh \
--input regmap/x410/versioning_regs_regmap_utils.vh \
--output dts/x410-version-info.dtsi \
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
top/x400/Makefile.x4xx.inc
+26 -15
View File
@@ -35,6 +35,7 @@ include $(LIB_DIR)/dsp/Makefile.srcs
include $(LIB_DIR)/ip/Makefile.inc
include $(LIB_DIR)/rfnoc/Makefile.srcs
include $(LIB_DIR)/wb_spi/Makefile.srcs
include $(LIB_DIR)/wishbone/Makefile.srcs
include $(LIB_DIR)/axi4_sv/Makefile.srcs
include $(LIB_DIR)/axi4s_sv/Makefile.srcs
include $(LIB_DIR)/axi4lite_sv/Makefile.srcs
@@ -62,10 +63,7 @@ EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
##################################################
TOP_SRCS =
ifdef X410
TOP_SRCS += \
TOP_SRCS = \
x4xx.v \
x4xx_qsfp_wrapper_temp.sv \
x4xx_qsfp_wrapper.sv \
@@ -78,12 +76,6 @@ x4xx_dio.v \
x4xx_gpio_atr.v \
x4xx_gpio_spi.v \
x4xx_dram.v \
rf/100m/rf_core_100m.v \
rf/200m/rf_core_200m.v \
rf/200m/rf_down_4to2.v \
rf/200m/rf_up_2to4.v \
rf/400m/rf_core_400m.v \
rf/common/rf_reset_controller.vhd \
ctrlport_spi_master.v \
cpld_interface.v \
cpld_interface_regs.v \
@@ -92,20 +84,41 @@ rfdc_timing_control.v \
x4xx_pps_sync.v \
../../lib/timing/pps_generator.v \
dboards/ctrlport_byte_serializer.v \
dboards/db_gpio_interface.v \
dboards/ctrlport_clk_crossing_derived.v \
dboards/db_gpio_reordering.v \
ipass_present_controller.v \
$(IMAGE_CORE)
ifdef X410
TOP_SRCS += \
rf/100m/rf_core_100m.v \
rf/200m/rf_core_200m.v \
rf/200m/rf_down_4to2.v \
rf/200m/rf_up_2to4.v \
rf/400m/rf_core_400m.v \
rf/x410/x410_rf_reset_controller.vhd \
dboards/zbx/db_gpio_interface.v
endif
MB_XDC = \
ifdef X410
MB_XDC += \
constraints/timing/x410_clocks.xdc
endif
MB_XDC += \
constraints/pins/common.xdc \
constraints/pins/rfdc_2x2.xdc \
constraints/timing/shared_constants.sdc \
constraints/timing/common.xdc \
constraints/pins/dram.xdc \
constraints/timing/dram.xdc
ifdef X410
MB_XDC += \
constraints/pins/rfdc_2x2.xdc \
constraints/pins/x410/db_gpio.xdc \
constraints/timing/x410.xdc
endif
# Definitions
# MGT Types from x4xx_mgt_type.vh
MGT_100GbE = 5
@@ -145,9 +158,7 @@ ifneq (,$(findstring QSFP1_3,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_3.xdc
endif
ifdef X410
DESIGN_SRCS = $(abspath $(MB_XDC))
endif
# The XDC files must be read in a specific order, motherboard first and then daughterboard.
# Outside of that, all the other sources can be read in any order desired.
top/x400/constraints/pins/common.xdc
-48
View File
@@ -60,57 +60,9 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports {FABRIC_CLK_OUT_*}]
# Pin constraints for the other PL pins (1.8 V)
###############################################################################
set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}]
set_property IOB TRUE [get_ports {DB1_GPIO[*]}]
set_property PACKAGE_PIN A7 [get_ports {DB1_SYNTH_SYNC}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_SYNTH_SYNC}]
set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}]
set_property IOB TRUE [get_ports {DB0_GPIO[*]}]
set_property PACKAGE_PIN AP5 [get_ports {DB0_SYNTH_SYNC}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_SYNTH_SYNC}]
top/x400/constraints/pins/x410/db_gpio.xdc
+59
View File
@@ -0,0 +1,59 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# DB GPIO pin constraints for X410.
#
###############################################################################
# Pin constraints for the other PL pins (1.8 V)
###############################################################################
set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}]
set_property IOB TRUE [get_ports {DB1_GPIO[*]}]
set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}]
set_property IOB TRUE [get_ports {DB0_GPIO[*]}]
top/x400/constraints/timing/common.xdc
-130
View File
@@ -16,12 +16,6 @@
set ref_clk_period 40.00
create_clock -name ref_clk -period $ref_clk_period [get_ports BASE_REFCLK_FPGA_P]
# PLL Reference Clock. Used to derive data clocks.
# Constrain to the fastest possible clock rate supported in the driver.
# MPM supports 61.44 / 62.5 / 64.0 MHz.
set pll_ref_clk_period 15.625
create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
# MGT Clocks
# Clock Reference | Frequency | Purpose
# MGT_REFCLK_LMK0 | 156.25/125 MHz | 10 GbE
@@ -69,22 +63,11 @@ set synth_sync_ports [get_ports {DB0_SYNTH_SYNC DB1_SYNTH_SYNC}]
set_output_delay -clock [get_clocks pll_ref_clk] -min -$synth_sync_hold_requirement $synth_sync_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $synth_sync_setup_requirement $synth_sync_ports
###############################################################################
# SPI to MB CPLD (PL)
# This interface is defined as system synchronous to pll_ref_clk.
###############################################################################
# The output delays are chosen to allow a large time window of valid data for
# the MB CPLD logic.
set spi_min_out_delay 0.000
set spi_max_out_delay 11.000
# Set output constraints for all ports.
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
# Both CPLD and FPGA use PLL reference clock from a common clock chip.
# The traces from that clock chip to the ICs are not length matched. Assume a
# worst case clock difference of 0.5 ns at the IC inputs. There is no direction
@@ -249,93 +232,6 @@ set_output_delay -clock ref_clk -max $lmk_sync_output_max_delay [get_ports {LMK_
set_output_delay -clock ref_clk -min $lmk_sync_output_min_delay [get_ports {LMK_SYNC}]
###############################################################################
# SPLL SYSREF Capture
###############################################################################
# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
# SYSREF and PLL reference clock are directly fed into the RFSoC.
# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
# output) with a double synchronizer and then transfered to the RFDC clock
# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
# sync. purposes.
# SYSREF is a continuous signal running at PRC freq. / 25, and it is
# intentionally shifted in the LMK chip to align it closer to the
# PRC's falling edge.
# The added delay follows the formula:
# SYSREF LMK delay = 22 * sample clock period
# The highest sampling frequency supported in MPM (3.072 GHz) is used for
# timing constrains. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9).
set sysref_lmk_delay 7.161
#
# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
#
# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
# which essentially over-constrains SYSREF.
#
# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
# calculated as follows:
# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
# - PRC prop. delay (min)
set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
#
# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
# is calculated as follows:
# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
# - PRC prop. delay (min)
set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
###############################################################################
# DB GPIO
# This interface is defined as system synchronous to pll_ref_clk.
# Some timing constants in this section are declared in
# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
###############################################################################
# Set output constraints for all ports.
set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports
# Output enable signal is available one clock cycle ahead of valid data, this
# enables the use of multi-cycle paths.
set db_gpio_out_en_regs [get_cells -hierarchical -filter \
{PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}]
set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports
set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports
# Calculate output delays back from capturing edge, add board delay and clock
# difference.
# Assume worst case as data being generated late and receiving an early clock:
# - Max CPLD TCO
# - Max data propagation delay
# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay
# - Maximum delay from MC100EPT23 clock buffer
set_input_delay -clock pll_ref_clk \
-max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \
+ $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \
$db_gpio_ports
# Negate minimum output delay as it is defined from the change to the start
# clock edge.
# Assume worst case as data being generated early and receiving an late clock:
# - Min CPLD TCO
# - Min data propagation delay (0)
# - Min CPLD clock propagation delay and max FPGA clock propagation delay
set_input_delay -clock pll_ref_clk \
-min [expr {- $db_gpio_cpld_min_out \
- $db_gpio_board_min_delay \
- $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \
$db_gpio_ports
###############################################################################
# x4xx_ps_rfdc_bd
###############################################################################
@@ -350,32 +246,6 @@ set gpio_regs [get_pins -of [get_cells -filter {IS_SEQUENTIAL && NAME =~ *rfdc/c
set mux_regs [get_cells -hier -filter {IS_SEQUENTIAL && NAME =~ *rfdc/calibration_muxes/gpio_to_axis_mux*}]
set_false_path -from $gpio_regs -to $mux_regs
# This property tells Vivado that we require these clocks to be well aligned.
# We have synchronous clock domain crossings between these clocks that can have
# large hold violations after placement due to uneven clock loading.
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \
}]
# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that
# code clocked in this domain will be reset after this clocked is enabled. This
# will make timing easier to meet on these clock domains.
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}]
###############################################################################
# Misc Constraints
top/x400/constraints/timing/x410.xdc
+141
View File
@@ -0,0 +1,141 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Timing constraints exclusive to X410. These should be used
# in conjunction with ./common.xdc
#
###############################################################################
# DB GPIO
# This interface is defined as system synchronous to pll_ref_clk.
# Some timing constants in this section are declared in
# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
###############################################################################
# Set output constraints for all ports.
set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports
# Output enable signal is available one clock cycle ahead of valid data, this
# enables the use of multi-cycle paths.
set db_gpio_out_en_regs [get_cells -hierarchical -filter \
{PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}]
set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports
set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports
# Calculate output delays back from capturing edge, add board delay and clock
# difference.
# Assume worst case as data being generated late and receiving an early clock:
# - Max CPLD TCO
# - Max data propagation delay
# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay
# - Maximum delay from MC100EPT23 clock buffer
set_input_delay -clock pll_ref_clk \
-max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \
+ $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \
$db_gpio_ports
# Negate minimum output delay as it is defined from the change to the start
# clock edge.
# Assume worst case as data being generated early and receiving an late clock:
# - Min CPLD TCO
# - Min data propagation delay (0)
# - Min CPLD clock propagation delay and max FPGA clock propagation delay
set_input_delay -clock pll_ref_clk \
-min [expr {- $db_gpio_cpld_min_out \
- $db_gpio_board_min_delay \
- $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \
$db_gpio_ports
###############################################################################
# x410_ps_rfdc_bd
###############################################################################
# This property tells Vivado that we require these clocks to be well aligned.
# We have synchronous clock domain crossings between these clocks that can have
# large hold violations after placement due to uneven clock loading.
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \
}]
# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that
# code clocked in this domain will be reset after this clocked is enabled. This
# will make timing easier to meet on these clock domains.
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}]
###############################################################################
# SPLL SYSREF Capture
###############################################################################
# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
# SYSREF and PLL reference clock are directly fed into the RFSoC.
# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
# output) with a double synchronizer and then transfered to the RFDC clock
# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
# sync. purposes.
# SYSREF is a continuous signal running at PRC freq. / 25, and it is
# intentionally shifted in the LMK chip to align it closer to the
# PRC's falling edge.
# The added delay follows the formula:
# SYSREF LMK delay = 22 * sample clock period
# The highest sampling frequency supported in MPM (3.072 GHz) is used for
# timing constraints. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9).
set sysref_lmk_delay 7.161
#
# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
#
# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
# which essentially over-constrains SYSREF.
#
# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
# calculated as follows:
# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
# - PRC prop. delay (min)
set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
#
# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
# is calculated as follows:
# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
# - PRC prop. delay (min)
set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
###############################################################################
# SPI to MB CPLD (PL)
# This interface is defined as system synchronous to pll_ref_clk.
###############################################################################
# The output delays are chosen to allow a large time window of valid data for
# the MB CPLD logic.
set spi_min_out_delay 0.000
set spi_max_out_delay 11.000
# Set output constraints for all ports.
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
top/x400/constraints/timing/x410_clocks.xdc
+18
View File
@@ -0,0 +1,18 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X410
#
###############################################################################
# Motherboard Clocks
###############################################################################
# PLL Reference Clock. Used to derive data clocks.
# Constrain to the fastest possible clock rate supported in the driver.
# MPM supports 61.44 / 62.5 / 64.0 MHz.
set pll_ref_clk_period 15.625
create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
top/x400/cpld/regmap/x440/constants_regmap_utils.vh
+28
View File
@@ -0,0 +1,28 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: constants_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group CONSTANTS_GROUP
//===============================================================================
// Enumerated type CONSTANTS_ENUM
localparam CONSTANTS_ENUM_SIZE = 4;
localparam PS_CPLD_SIGNATURE = 'hA522D28; // CONSTANTS_ENUM:PS_CPLD_SIGNATURE
localparam CPLD_REVISION = 'h22080414; // CONSTANTS_ENUM:CPLD_REVISION
localparam OLDEST_CPLD_REVISION = 'h22080414; // CONSTANTS_ENUM:OLDEST_CPLD_REVISION
localparam PL_CPLD_SIGNATURE = 'h3FDC5C47; // CONSTANTS_ENUM:PL_CPLD_SIGNATURE
top/x400/cpld/regmap/x440/led_setup_regmap_utils.vh
+63
View File
@@ -0,0 +1,63 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: led_setup_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// LED_CONTROL : 0x0 (led_control.v)
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group LED_SETUP_REGISTERS
//===============================================================================
// LED_CONTROL Register (from led_control.v)
localparam LED_CONTROL = 'h0; // Register Offset
localparam LED_CONTROL_SIZE = 32; // register width in bits
localparam LED_CONTROL_MASK = 32'h7070707;
localparam CH0_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH0_RX2_LED_EN
localparam CH0_RX2_LED_EN_MSB = 0; //LED_CONTROL:CH0_RX2_LED_EN
localparam CH0_RX2_LED_EN = 0; //LED_CONTROL:CH0_RX2_LED_EN
localparam CH0_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH0_TRX1_LED_RED_EN
localparam CH0_TRX1_LED_RED_EN_MSB = 1; //LED_CONTROL:CH0_TRX1_LED_RED_EN
localparam CH0_TRX1_LED_RED_EN = 1; //LED_CONTROL:CH0_TRX1_LED_RED_EN
localparam CH0_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH0_TRX1_LED_GR_EN
localparam CH0_TRX1_LED_GR_EN_MSB = 2; //LED_CONTROL:CH0_TRX1_LED_GR_EN
localparam CH0_TRX1_LED_GR_EN = 2; //LED_CONTROL:CH0_TRX1_LED_GR_EN
localparam CH1_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH1_RX2_LED_EN
localparam CH1_RX2_LED_EN_MSB = 8; //LED_CONTROL:CH1_RX2_LED_EN
localparam CH1_RX2_LED_EN = 8; //LED_CONTROL:CH1_RX2_LED_EN
localparam CH1_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH1_TRX1_LED_RED_EN
localparam CH1_TRX1_LED_RED_EN_MSB = 9; //LED_CONTROL:CH1_TRX1_LED_RED_EN
localparam CH1_TRX1_LED_RED_EN = 9; //LED_CONTROL:CH1_TRX1_LED_RED_EN
localparam CH1_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH1_TRX1_LED_GR_EN
localparam CH1_TRX1_LED_GR_EN_MSB = 10; //LED_CONTROL:CH1_TRX1_LED_GR_EN
localparam CH1_TRX1_LED_GR_EN = 10; //LED_CONTROL:CH1_TRX1_LED_GR_EN
localparam CH2_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH2_RX2_LED_EN
localparam CH2_RX2_LED_EN_MSB = 16; //LED_CONTROL:CH2_RX2_LED_EN
localparam CH2_RX2_LED_EN = 16; //LED_CONTROL:CH2_RX2_LED_EN
localparam CH2_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH2_TRX1_LED_RED_EN
localparam CH2_TRX1_LED_RED_EN_MSB = 17; //LED_CONTROL:CH2_TRX1_LED_RED_EN
localparam CH2_TRX1_LED_RED_EN = 17; //LED_CONTROL:CH2_TRX1_LED_RED_EN
localparam CH2_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH2_TRX1_LED_GR_EN
localparam CH2_TRX1_LED_GR_EN_MSB = 18; //LED_CONTROL:CH2_TRX1_LED_GR_EN
localparam CH2_TRX1_LED_GR_EN = 18; //LED_CONTROL:CH2_TRX1_LED_GR_EN
localparam CH3_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH3_RX2_LED_EN
localparam CH3_RX2_LED_EN_MSB = 24; //LED_CONTROL:CH3_RX2_LED_EN
localparam CH3_RX2_LED_EN = 24; //LED_CONTROL:CH3_RX2_LED_EN
localparam CH3_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH3_TRX1_LED_RED_EN
localparam CH3_TRX1_LED_RED_EN_MSB = 25; //LED_CONTROL:CH3_TRX1_LED_RED_EN
localparam CH3_TRX1_LED_RED_EN = 25; //LED_CONTROL:CH3_TRX1_LED_RED_EN
localparam CH3_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH3_TRX1_LED_GR_EN
localparam CH3_TRX1_LED_GR_EN_MSB = 26; //LED_CONTROL:CH3_TRX1_LED_GR_EN
localparam CH3_TRX1_LED_GR_EN = 26; //LED_CONTROL:CH3_TRX1_LED_GR_EN
top/x400/cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh
+36
View File
@@ -0,0 +1,36 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: mb_cpld_pl_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// PL_REGISTERS : 0x0 (mb_cpld.v)
// PL_DB0_LED_REGISTERS : 0x50 (mb_cpld.v)
// PL_DB1_LED_REGISTERS : 0x60 (mb_cpld.v)
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group MB_CPLD_PL_WINDOWS
//===============================================================================
// PL_REGISTERS Window (from mb_cpld.v)
localparam PL_REGISTERS = 'h0; // Window Offset
localparam PL_REGISTERS_SIZE = 'h40; // size in bytes
// PL_DB0_LED_REGISTERS Window (from mb_cpld.v)
localparam PL_DB0_LED_REGISTERS = 'h50; // Window Offset
localparam PL_DB0_LED_REGISTERS_SIZE = 'h10; // size in bytes
// PL_DB1_LED_REGISTERS Window (from mb_cpld.v)
localparam PL_DB1_LED_REGISTERS = 'h60; // Window Offset
localparam PL_DB1_LED_REGISTERS_SIZE = 'h10; // size in bytes
top/x400/cpld_interface.v
+46 -156
View File
@@ -30,11 +30,6 @@ module cpld_interface (
// Reset (domain: pll_ref_clk)
input wire ctrlport_rst,
// Timestamp (domain: radio_clk)
input wire [63:0] radio_time,
input wire radio_time_stb,
input wire [ 3:0] time_ignore_bits,
// AXI4-Lite: Write address port (domain: s_axi_aclk)
input wire [16:0] s_axi_awaddr,
input wire s_axi_awvalid,
@@ -64,8 +59,6 @@ module cpld_interface (
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
input wire [ 3:0] s_ctrlport_req_byte_en,
input wire s_ctrlport_req_has_time,
input wire [63:0] s_ctrlport_req_time,
output wire s_ctrlport_resp_ack,
output wire [ 1:0] s_ctrlport_resp_status,
output wire [31:0] s_ctrlport_resp_data,
@@ -91,7 +84,8 @@ module cpld_interface (
`include "../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/pl_cpld_regmap_utils.vh"
`include "cpld/regmap/mb_cpld_pl_regmap_utils.vh"
// Variant-dependent register map.
`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
//---------------------------------------------------------------------------
@@ -103,28 +97,6 @@ module cpld_interface (
assign s_axi_areset = ~s_axi_aresetn;
assign ctrlport_clk = pll_ref_clk;
//---------------------------------------------------------------------------
// Timestamp synchronization
//---------------------------------------------------------------------------
reg [ 3:0] radio_time_stb_shift_reg;
wire radio_time_stb_prc;
reg [63:0] radio_time_prc;
// radio_clk and pll_ref_clk are synchronous clocks with an integer
// multiplier <= 4.
//
// A simple register can be used to capture the latest timestamp the strobe
// pulse is preserved for up to 4 clock cycles and used in pll_ref_clk domain
// to driver timers.
always @(posedge radio_clk) begin
radio_time_stb_shift_reg <= {radio_time_stb_shift_reg[2:0], radio_time_stb};
if (radio_time_stb) begin
radio_time_prc <= radio_time;
end
end
assign radio_time_stb_prc = | radio_time_stb_shift_reg;
//---------------------------------------------------------------------------
// MPM Endpoint connection
//---------------------------------------------------------------------------
@@ -134,12 +106,10 @@ module cpld_interface (
wire [19:0] mpm_endpoint_ctrlport_axi_clk_req_addr;
wire [ 3:0] mpm_endpoint_ctrlport_axi_clk_req_byte_en;
wire [31:0] mpm_endpoint_ctrlport_axi_clk_req_data;
wire mpm_endpoint_ctrlport_axi_clk_req_has_time;
wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_portid;
wire mpm_endpoint_ctrlport_axi_clk_req_rd;
wire [15:0] mpm_endpoint_ctrlport_axi_clk_req_rem_epid;
wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_rem_portid;
wire [63:0] mpm_endpoint_ctrlport_axi_clk_req_time;
wire mpm_endpoint_ctrlport_axi_clk_req_wr;
wire mpm_endpoint_ctrlport_axi_clk_resp_ack;
wire [31:0] mpm_endpoint_ctrlport_axi_clk_resp_data;
@@ -177,8 +147,8 @@ module cpld_interface (
.m_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
.m_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
.m_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
.m_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
.m_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data)
@@ -186,16 +156,14 @@ module cpld_interface (
// Transfer AXI clock based MPM endpoint control port request to pll_ref_clk
// domain.
wire [19:0] mpm_endpoint_ctrlport_pll_clk_req_addr;
wire [ 3:0] mpm_endpoint_ctrlport_pll_clk_req_byte_en;
wire [31:0] mpm_endpoint_ctrlport_pll_clk_req_data;
wire mpm_endpoint_ctrlport_pll_clk_req_has_time;
wire mpm_endpoint_ctrlport_pll_clk_req_rd;
wire [63:0] mpm_endpoint_ctrlport_pll_clk_req_time;
wire mpm_endpoint_ctrlport_pll_clk_req_wr;
wire mpm_endpoint_ctrlport_pll_clk_resp_ack;
wire [31:0] mpm_endpoint_ctrlport_pll_clk_resp_data;
wire [ 1:0] mpm_endpoint_ctrlport_pll_clk_resp_status;
wire [19:0] mpm_endpoint_ctrlport_req_addr;
wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en;
wire [31:0] mpm_endpoint_ctrlport_req_data;
wire mpm_endpoint_ctrlport_req_rd;
wire mpm_endpoint_ctrlport_req_wr;
wire mpm_endpoint_ctrlport_resp_ack;
wire [31:0] mpm_endpoint_ctrlport_resp_data;
wire [ 1:0] mpm_endpoint_ctrlport_resp_status;
ctrlport_clk_cross ctrlport_clk_cross_mpm (
.rst (s_axi_areset),
@@ -208,63 +176,25 @@ module cpld_interface (
.s_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
.s_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
.s_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
.s_ctrlport_req_has_time (1'b0),
.s_ctrlport_req_time (64'b0),
.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
.s_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
.s_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data),
.m_ctrlport_clk (ctrlport_clk),
.m_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
.m_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
.m_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
.m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr),
.m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd),
.m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
.m_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
.m_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
.m_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data)
);
// Apply time of ControlPort request to MPM endpoint request.
wire [19:0] mpm_endpoint_ctrlport_req_addr;
wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en;
wire [31:0] mpm_endpoint_ctrlport_req_data;
wire mpm_endpoint_ctrlport_req_rd;
wire mpm_endpoint_ctrlport_req_wr;
wire mpm_endpoint_ctrlport_resp_ack;
wire [31:0] mpm_endpoint_ctrlport_resp_data;
wire [ 1:0] mpm_endpoint_ctrlport_resp_status;
ctrlport_timer #(
.EXEC_LATE_CMDS (1)
) ctrlport_timer_mpm (
.clk (ctrlport_clk),
.rst (ctrlport_rst),
.time_now (radio_time_prc),
.time_now_stb (radio_time_stb_prc),
.time_ignore_bits (time_ignore_bits),
.s_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
.s_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
.s_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
.s_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
.s_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
.s_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
.s_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data),
.m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr),
.m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd),
.m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr),
.m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data),
.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en),
.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack),
.m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status),
.m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data)
.m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data),
.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack),
.m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status),
.m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data)
);
//---------------------------------------------------------------------------
@@ -272,16 +202,14 @@ module cpld_interface (
//---------------------------------------------------------------------------
// Transfer request to pll_ref_clk domain.
wire [19:0] app_ctrlport_pll_clk_req_addr;
wire [ 3:0] app_ctrlport_pll_clk_req_byte_en;
wire [31:0] app_ctrlport_pll_clk_req_data;
wire app_ctrlport_pll_clk_req_has_time;
wire app_ctrlport_pll_clk_req_rd;
wire [63:0] app_ctrlport_pll_clk_req_time;
wire app_ctrlport_pll_clk_req_wr;
wire app_ctrlport_pll_clk_resp_ack;
wire [31:0] app_ctrlport_pll_clk_resp_data;
wire [ 1:0] app_ctrlport_pll_clk_resp_status;
wire [19:0] app_ctrlport_req_addr;
wire [ 3:0] app_ctrlport_req_byte_en;
wire [31:0] app_ctrlport_req_data;
wire app_ctrlport_req_rd;
wire app_ctrlport_req_wr;
wire app_ctrlport_resp_ack;
wire [31:0] app_ctrlport_resp_data;
wire [ 1:0] app_ctrlport_resp_status;
ctrlport_clk_cross ctrlport_clk_cross_app (
.rst (ctrlport_rst),
@@ -294,63 +222,25 @@ module cpld_interface (
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data (s_ctrlport_req_data),
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
.s_ctrlport_req_time (s_ctrlport_req_time),
.s_ctrlport_req_has_time (1'b0),
.s_ctrlport_req_time (64'b0),
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
.s_ctrlport_resp_status (s_ctrlport_resp_status),
.s_ctrlport_resp_data (s_ctrlport_resp_data),
.m_ctrlport_clk (ctrlport_clk),
.m_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
.m_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
.m_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
.m_ctrlport_req_wr (app_ctrlport_req_wr),
.m_ctrlport_req_rd (app_ctrlport_req_rd),
.m_ctrlport_req_addr (app_ctrlport_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
.m_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
.m_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
.m_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
.m_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
.m_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
.m_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data)
);
// Apply timing to application based ControlPort request.
wire [19:0] app_ctrlport_req_addr;
wire [ 3:0] app_ctrlport_req_byte_en;
wire [31:0] app_ctrlport_req_data;
wire app_ctrlport_req_rd;
wire app_ctrlport_req_wr;
wire app_ctrlport_resp_ack;
wire [31:0] app_ctrlport_resp_data;
wire [ 1:0] app_ctrlport_resp_status;
ctrlport_timer #(
.EXEC_LATE_CMDS (1)
) ctrlport_timer_app (
.clk (ctrlport_clk),
.rst (ctrlport_rst),
.time_now (radio_time_prc),
.time_now_stb (radio_time_stb_prc),
.time_ignore_bits (time_ignore_bits),
.s_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
.s_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
.s_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
.s_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
.s_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
.s_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
.s_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
.s_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
.s_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
.s_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data),
.m_ctrlport_req_wr (app_ctrlport_req_wr),
.m_ctrlport_req_rd (app_ctrlport_req_rd),
.m_ctrlport_req_addr (app_ctrlport_req_addr),
.m_ctrlport_req_data (app_ctrlport_req_data),
.m_ctrlport_req_byte_en (app_ctrlport_req_byte_en),
.m_ctrlport_resp_ack (app_ctrlport_resp_ack),
.m_ctrlport_resp_status (app_ctrlport_resp_status),
.m_ctrlport_resp_data (app_ctrlport_resp_data)
.m_ctrlport_req_data (app_ctrlport_req_data),
.m_ctrlport_req_byte_en (app_ctrlport_req_byte_en),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (app_ctrlport_resp_ack),
.m_ctrlport_resp_status (app_ctrlport_resp_status),
.m_ctrlport_resp_data (app_ctrlport_resp_data)
);
//---------------------------------------------------------------------------
@@ -440,8 +330,8 @@ module cpld_interface (
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data ({ipass_ctrlport_req_data, led_ctrlport_req_data, mpm_endpoint_ctrlport_req_data, app_ctrlport_req_data}),
.s_ctrlport_req_byte_en ({ipass_ctrlport_req_byte_en, led_ctrlport_req_byte_en, mpm_endpoint_ctrlport_req_byte_en, app_ctrlport_req_byte_en}),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_req_has_time ({4{1'b0}}),
.s_ctrlport_req_time ({4{64'b0}}),
.s_ctrlport_resp_ack ({ipass_ctrlport_resp_ack, led_ctrlport_resp_ack, mpm_endpoint_ctrlport_resp_ack, app_ctrlport_resp_ack}),
.s_ctrlport_resp_status ({ipass_ctrlport_resp_status, led_ctrlport_resp_status, mpm_endpoint_ctrlport_resp_status, app_ctrlport_resp_status}),
.s_ctrlport_resp_data ({ipass_ctrlport_resp_data, led_ctrlport_resp_data, mpm_endpoint_ctrlport_resp_data, app_ctrlport_resp_data}),
top/x400/cpld_interface_regs.v
+4 -2
View File
@@ -45,9 +45,11 @@ module cpld_interface_regs #(
output wire [95:0] version_info
);
`include "regmap/cpld_interface_regmap_utils.vh"
`include "regmap/versioning_regs_regmap_utils.vh"
// Variant-dependent register map.
`include "regmap/x410/versioning_regs_regmap_utils.vh"
`include "regmap/versioning_utils.vh"
`include "regmap/cpld_interface_regmap_utils.vh"
`include "../../lib/rfnoc/core/ctrlport.vh"
//----------------------------------------------------------
top/x400/dboards/ctrlport_clk_crossing_derived.v
+130
View File
@@ -0,0 +1,130 @@
//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_clk_crossing_derived
//
// Description:
// Performs a simplified clk crossing for a ctrlport interface.
// i_clk must be derived from o_clk by an integer multiplier and
// originate from the same PLL. This ensures the clock crossing
// can be achieved by using simple registers, as STA will be able
// to meet setup and hold requirements on them.
//
`default_nettype none
module ctrlport_clk_crossing_derived (
// Clocks
input wire i_clk,
input wire o_clk,
// Request (domain: i_clk)
input wire i_ctrlport_rst,
input wire i_ctrlport_req_wr,
input wire i_ctrlport_req_rd,
input wire [19:0] i_ctrlport_req_addr,
input wire [31:0] i_ctrlport_req_data,
// Response (domain: i_clk)
output wire i_ctrlport_resp_ack,
output reg [ 1:0] i_ctrlport_resp_status,
output reg [31:0] i_ctrlport_resp_data,
// Request (domain: o_clk)
output reg o_ctrlport_rst,
output reg o_ctrlport_req_wr,
output reg o_ctrlport_req_rd,
output reg [19:0] o_ctrlport_req_addr,
output reg [31:0] o_ctrlport_req_data,
// Response (domain: o_clk)
input wire o_ctrlport_resp_ack,
input wire [ 1:0] o_ctrlport_resp_status,
input wire [31:0] o_ctrlport_resp_data
);
// holding read and write flags for multiple i_clk cycles
reg ctrlport_req_wr_hold = 1'b0;
reg ctrlport_req_rd_hold = 1'b0;
reg ctrlport_req_rd_fall = 1'b0;
reg ctrlport_req_wr_fall = 1'b0;
reg [31:0] ctrlport_resp_data_fall = 32'b0;
reg [ 1:0] ctrlport_resp_status_fall = 2'b0;
reg ctrlport_resp_ack_fall = 1'b0;
// Retime signals to falling edge of i_clk. By sampling on the falling edge of
// i_clk, we provide (nominally) half a i_clk period of hold, while
// reducing setup time by half. The late arrival of i_clk adds back some
// of the lost setup margin.
always @(negedge i_clk) begin
ctrlport_req_rd_fall <= o_ctrlport_req_rd;
ctrlport_req_wr_fall <= o_ctrlport_req_wr;
ctrlport_resp_ack_fall <= o_ctrlport_resp_ack;
ctrlport_resp_status_fall <= o_ctrlport_resp_status;
ctrlport_resp_data_fall <= o_ctrlport_resp_data;
end
always @(posedge i_clk) begin
if (ctrlport_req_wr_fall) begin
ctrlport_req_wr_hold <= 1'b0;
end else if (i_ctrlport_req_wr) begin
ctrlport_req_wr_hold <= 1'b1;
end
if (ctrlport_req_rd_fall) begin
ctrlport_req_rd_hold <= 1'b0;
end else if (i_ctrlport_req_rd) begin
ctrlport_req_rd_hold <= 1'b1;
end
// capture request address and data
if (i_ctrlport_req_wr || i_ctrlport_req_rd) begin
o_ctrlport_req_addr <= i_ctrlport_req_addr;
o_ctrlport_req_data <= i_ctrlport_req_data;
end
end
// capture extended flags in o_clk domain
always @(posedge o_clk) begin
o_ctrlport_req_wr <= ctrlport_req_wr_hold;
o_ctrlport_req_rd <= ctrlport_req_rd_hold;
end
// search for rising edge in response
reg [1:0] ctrlport_resp_ack_reg = 2'b0;
always @(posedge i_clk) begin
ctrlport_resp_ack_reg = {ctrlport_resp_ack_reg[0], ctrlport_resp_ack_fall};
end
assign i_ctrlport_resp_ack = ctrlport_resp_ack_reg[0] & ~ctrlport_resp_ack_reg[1];
// capture response data
always @(posedge i_clk) begin
if (ctrlport_resp_ack_fall) begin
i_ctrlport_resp_status <= ctrlport_resp_status_fall;
i_ctrlport_resp_data <= ctrlport_resp_data_fall;
end
end
// transfer reset
reg ctrlport_rst_hold = 1'b0;
reg ctrlport_rst_fall = 1'b0;
always @(posedge i_clk) begin
if (i_ctrlport_rst) begin
ctrlport_rst_hold <= 1'b1;
end else if (ctrlport_rst_fall) begin
ctrlport_rst_hold <= 1'b0;
end
end
always @(posedge o_clk) begin
o_ctrlport_rst <= ctrlport_rst_hold;
end
always @(negedge i_clk) begin
ctrlport_rst_fall <= o_ctrlport_rst;
end
endmodule
`default_nettype wire
top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf
+4 -4
View File
@@ -827,14 +827,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED
set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v
set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc
set_global_assignment -name SDC_FILE ../../../../cpld/db_spi_shared_constants.sdc
set_global_assignment -name SDC_FILE ../../../../cpld/x410/db_spi_shared_constants.sdc
set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v
set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave.v
set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave_to_ctrlport_master.v
set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave.v
set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave_to_ctrlport_master.v
set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v
set_global_assignment -name VERILOG_FILE ../register_endpoints/power_regs.v
set_global_assignment -name VERILOG_FILE ../register_endpoints/switch_control.v
@@ -847,7 +847,7 @@ set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v
set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v
set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v
set_global_assignment -name VERILOG_FILE ../../../../cpld/reconfig_engine.v
set_global_assignment -name VERILOG_FILE ../../../../cpld/common/reconfig_engine.v
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v
set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v
set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh
top/x400/dboards/zbx/db_gpio_interface.v
+214
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@@ -0,0 +1,214 @@
//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: db_gpio_interface
//
// Description:
// Interface for GPIO interface towards daughterboards.
//
// A ControlPort interface is serialized into bytes along with a valid signal.
// The ControlPort supports write requests only. Byte enables are not supported.
// There is support for timed commands.
// Furthermore there are 4 state wires towards the DB. Ensure an appropriate
// hold time on the states as the transmission happens in pll_ref_clk, which is
// slower than radio_clk. Pulses of e.g. just a single clock cycle may not get
// transferred to the DB.
//
// The 20 available GPIO lines are assigned with
// - 5x empty
// - bytestream direction
// - bytestream valid
// - bytestream data (8 bits)
// - 1x empty
// - db_state (4 bits)
//
`default_nettype none
module db_gpio_interface (
// Clocks and reset
input wire radio_clk,
input wire pll_ref_clk,
// DB state lines (domain: radio_clk)
input wire [ 3:0] db_state,
// Request (domain: radio_clk)
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response (domain: radio_clk)
output wire s_ctrlport_resp_ack,
output wire [ 1:0] s_ctrlport_resp_status,
output wire [31:0] s_ctrlport_resp_data,
// GPIO interface (domain: pll_ref_clk)
input wire [19:0] gpio_in,
output wire [19:0] gpio_out,
output wire [19:0] gpio_out_en,
// Version (Constant)
output wire [95:0] version_info
);
`include "../../regmap/x410/versioning_regs_regmap_utils.vh"
`include "../../regmap/versioning_utils.vh"
//----------------------------------------------------------------------------
// Clock domain crossing (radio_clk -> pll_ref_clk)
//----------------------------------------------------------------------------
// Radio_clk is derived from pll_ref_clk by an integer multiplier and
// originate from the same PLL.
// Therefore the clock crossing can be achieved by using simple registers.
// Static timing analysis will be able to meet setup and hold requirements on
// them.
wire ctrlport_rst_prc;
wire ctrlport_req_wr_prc;
wire ctrlport_req_rd_prc;
wire [19:0] ctrlport_req_addr_prc;
wire [31:0] ctrlport_req_data_prc;
wire ctrlport_resp_ack_prc;
wire [ 1:0] ctrlport_resp_status_prc;
wire [31:0] ctrlport_resp_data_prc;
ctrlport_clk_crossing_derived ctrlport_clk_crossing_derived_i(
.i_clk (radio_clk),
.o_clk (pll_ref_clk),
.i_ctrlport_rst (ctrlport_rst),
.i_ctrlport_req_wr (s_ctrlport_req_wr),
.i_ctrlport_req_rd (s_ctrlport_req_rd),
.i_ctrlport_req_addr (s_ctrlport_req_addr),
.i_ctrlport_req_data (s_ctrlport_req_data),
.i_ctrlport_resp_ack (s_ctrlport_resp_ack),
.i_ctrlport_resp_status (s_ctrlport_resp_status),
.i_ctrlport_resp_data (s_ctrlport_resp_data),
.o_ctrlport_rst (ctrlport_rst_prc),
.o_ctrlport_req_wr (ctrlport_req_wr_prc),
.o_ctrlport_req_rd (ctrlport_req_rd_prc),
.o_ctrlport_req_addr (ctrlport_req_addr_prc),
.o_ctrlport_req_data (ctrlport_req_data_prc),
.o_ctrlport_resp_ack (ctrlport_resp_ack_prc),
.o_ctrlport_resp_status (ctrlport_resp_status_prc),
.o_ctrlport_resp_data (ctrlport_resp_data_prc)
);
// transfer state lines
reg [3:0] db_state_prc = 4'b0;
reg [3:0] db_state_prc_fe = 4'b0;
always @(posedge pll_ref_clk) begin
db_state_prc <= db_state;
end
always @(negedge pll_ref_clk) begin
db_state_prc_fe <= db_state_prc;
end
//----------------------------------------------------------------------------
// Ctrlport serializer
//----------------------------------------------------------------------------
wire [7:0] bytestream_data_in;
wire [7:0] bytestream_data_out;
wire bytestream_direction;
wire bytestream_output_enable;
wire bytestream_valid_in;
wire bytestream_valid_out;
ctrlport_byte_serializer serializer_i (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (ctrlport_req_wr_prc),
.s_ctrlport_req_rd (ctrlport_req_rd_prc),
.s_ctrlport_req_addr (ctrlport_req_addr_prc),
.s_ctrlport_req_data (ctrlport_req_data_prc),
.s_ctrlport_resp_ack (ctrlport_resp_ack_prc),
.s_ctrlport_resp_status (ctrlport_resp_status_prc),
.s_ctrlport_resp_data (ctrlport_resp_data_prc),
.bytestream_data_in (bytestream_data_in),
.bytestream_valid_in (bytestream_valid_in),
.bytestream_data_out (bytestream_data_out),
.bytestream_valid_out (bytestream_valid_out),
.bytestream_direction (bytestream_direction),
.bytestream_output_enable (bytestream_output_enable)
);
// IOB registers to drive data on the falling edge
reg [7:0] bytestream_data_out_fe;
reg bytestream_direction_fe;
reg bytestream_output_enable_fe;
reg bytestream_valid_out_fe;
// Signals are shifted into a falling edge domain to help meet
// hold requirements at CPLD
always @(negedge pll_ref_clk) begin
if (ctrlport_rst_prc) begin
bytestream_data_out_fe <= 8'b0;
bytestream_valid_out_fe <= 1'b0;
bytestream_direction_fe <= 1'b0;
bytestream_output_enable_fe <= 1'b1;
end else begin
bytestream_data_out_fe <= bytestream_data_out;
bytestream_valid_out_fe <= bytestream_valid_out;
bytestream_direction_fe <= bytestream_direction;
bytestream_output_enable_fe <= bytestream_output_enable;
end
end
//----------------------------------------------------------------------------
// wire assignment
//----------------------------------------------------------------------------
// 5 unused, 10 used, 1 unused and 4 used signals
assign gpio_out = {5'b0, bytestream_direction_fe, bytestream_valid_out_fe, bytestream_data_out_fe, 1'b0, db_state_prc_fe};
assign gpio_out_en = {5'b0, 1'b1, {9 {bytestream_output_enable_fe}}, 1'b0, {4 {1'b1}} };
assign bytestream_valid_in = gpio_in[13];
assign bytestream_data_in = gpio_in[12:5];
//----------------------------------------------------------------------------
// version_info
//----------------------------------------------------------------------------
// Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh
assign version_info = build_component_versions(
DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME,
build_version(
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD),
build_version(
DB_GPIO_IFC_CURRENT_VERSION_MAJOR,
DB_GPIO_IFC_CURRENT_VERSION_MINOR,
DB_GPIO_IFC_CURRENT_VERSION_BUILD));
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="VERSIONING_REGS_REGMAP">
// <group name="VERSIONING_CONSTANTS">
// <enumeratedtype name="DB_GPIO_IFC_VERSION" showhex="true">
// <info>
// Daughterboard GPIO interface.{BR/}
// For guidance on when to update these revision numbers,
// please refer to the register map documentation accordingly:
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x20110616"/>
// </enumeratedtype>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/doc/X410/X410_FPGA.htm
+10
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@@ -0,0 +1,10 @@
<HTML>
<HEAD>
<title>X410_FPGA</title>
<FRAMESET COLS="20%,*" onload=window.frames[1].location.hash=window.location.href.split("#")[1];>
<FRAME name="leftframe" SRC="X410_FPGA_left.htm">
<FRAME name="rightframe" SRC="X410_FPGA_right.htm">
</FRAMESET>
</HEAD>
</HTML>
top/x400/doc/X410/X410_FPGA_left.htm
+743
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@@ -0,0 +1,743 @@
<html>
<head>
<meta http-equiv="Content-Type" content="text/html;charset=utf-8"/>
<style type="text/css">
body {
margin: 5px;
font-family: verdana, "Trebuchet MS", arial, helvetica, sans-serif;
font-size: 80%;
line-height: 1.3;
}
pre, code {
font-family: "courier new", courier, monospace;
font-size: 12px;
}
@media print {
body {
margin: 0px;
font-family: arial, helvetica, sans-serif;
font-size: 80%;
line-height: 1;
}
} div.nav {
font-size: 95%;
}
div.sh {
display: none;
margin-left: 15px;
}
div.shr {
display: block;
margin-left: 15px;
}
div.nav span.pm, div.nav span.pm_2 {
color: black;
font-family: courier new, courier;
margin-right: 5px;
}
div.nav span.pm {
cursor: pointer;
}
div.nav p {
margin: 0px;
padding: 0px;
white-space: nowrap;
}
div.nav span {
cursor: pointer;
}
div.nav span.regmap {
color: #000080;
}
div.nav span.group {
color: #006000;
}
div.nav span.enum {
color: #800000;
margin-left: 10px;
}
div.nav span.register {
color: #004040;
margin-left: 10px;
}
</style>
<script type="text/javascript">
function toggleText( id, sign ) {
if (sign == "nochange") return;
if ( document.getElementById )
elem = document.getElementById( id );
else if ( document.all )
elem = eval( "document.all." + id );
if (elem) {
elemStyle = elem.style;
if (sign=="+") {
elemStyle.display = "block"
} else {
elemStyle.display = "none"
}
/*if ( elemStyle.display == "block" ) {
elemStyle.display = "none"
} else {
elemStyle.display = "block"
}*/
}
}
function changePm( id ) {
if ( document.getElementById )
elem = document.getElementById( id );
else if ( document.all )
elem = eval( "document.all." + id );
else
return "nochange";
var val = elem.innerHTML;
if (val == "+") {
elem.innerHTML = "-";
} else {
elem.innerHTML = "+";
}
return val;
}
function pm( id ) {
var sign = changePm("pm_" + id);
toggleText("div_" + id, sign);
}
function a( id ) {
var currentURL= document.URL;
var targetURL = currentURL.replace("_left", "_right");
parent.frames[1].location = targetURL + '#' + id;
}
</script>
</head><body>
<div class="nav">
<p>
<span class="pm" id="pm_X410_FPGA" onclick="pm('X410_FPGA');">+</span>
<span class="regmap" id="a_X410_FPGA" onclick="a('X410_FPGA');">X410_FPGA</span>
</p>
<div class="sh" id="div_X410_FPGA">
<p>
<span class="pm" id="pm_P5 Content" onclick="pm('P5 Content');">+</span>
<span class="group" id="a_P5 Content" onclick="a('P5 Content');">P5 Content</span>
</p>
<div class="sh" id="div_P5 Content">
</div>
<p>
<span class="pm" id="pm_ports" onclick="pm('ports');">+</span>
<span class="group" id="a_ports" onclick="a('ports');">ports</span>
</p>
<div class="sh" id="div_ports">
<p><span class="register" id="a_X410_FPGA|ARM_M_AXI_HPM0" onclick="a('X410_FPGA|ARM_M_AXI_HPM0');">ARM_M_AXI_HPM0</span></p>
<p><span class="register" id="a_X410_FPGA|ARM_S_AXI_HPC0" onclick="a('X410_FPGA|ARM_S_AXI_HPC0');">ARM_S_AXI_HPC0</span></p>
<p><span class="register" id="a_X410_FPGA|ARM_S_AXI_HPC1" onclick="a('X410_FPGA|ARM_S_AXI_HPC1');">ARM_S_AXI_HPC1</span></p>
<p><span class="register" id="a_X410_FPGA|ARM_SPI1_CS3" onclick="a('X410_FPGA|ARM_SPI1_CS3');">ARM_SPI1_CS3</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_AXI_HPM0_REGMAP" onclick="pm('AXI_HPM0_REGMAP');">+</span>
<span class="regmap" id="a_AXI_HPM0_REGMAP" onclick="a('AXI_HPM0_REGMAP');">AXI_HPM0_REGMAP</span>
</p> <div class="sh" id="div_AXI_HPM0_REGMAP">
<p>
<span class="pm" id="pm_AXI_HPM0_REGMAP|COMMON" onclick="pm('AXI_HPM0_REGMAP|COMMON');">+</span>
<span class="group" id="a_AXI_HPM0_REGMAP|COMMON" onclick="a('AXI_HPM0_REGMAP|COMMON');">COMMON</span>
</p>
<div class="sh" id="div_AXI_HPM0_REGMAP|COMMON">
<p><span class="register" id="a_AXI_HPM0_REGMAP|RPU" onclick="a('AXI_HPM0_REGMAP|RPU');">RPU</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|JTAG_ENGINE" onclick="a('AXI_HPM0_REGMAP|JTAG_ENGINE');">JTAG_ENGINE</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|RESERVED" onclick="a('AXI_HPM0_REGMAP|RESERVED');">RESERVED</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|MPM_ENDPOINT" onclick="a('AXI_HPM0_REGMAP|MPM_ENDPOINT');">MPM_ENDPOINT</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|CORE_REGS" onclick="a('AXI_HPM0_REGMAP|CORE_REGS');">CORE_REGS</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|INT_ETH_DMA" onclick="a('AXI_HPM0_REGMAP|INT_ETH_DMA');">INT_ETH_DMA</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|INT_ETH_REGS" onclick="a('AXI_HPM0_REGMAP|INT_ETH_REGS');">INT_ETH_REGS</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|RFDC" onclick="a('AXI_HPM0_REGMAP|RFDC');">RFDC</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|RFDC_REGS" onclick="a('AXI_HPM0_REGMAP|RFDC_REGS');">RFDC_REGS</span></p>
</div>
<p>
<span class="pm" id="pm_AXI_HPM0_REGMAP|UHD_ONLY" onclick="pm('AXI_HPM0_REGMAP|UHD_ONLY');">+</span>
<span class="group" id="a_AXI_HPM0_REGMAP|UHD_ONLY" onclick="a('AXI_HPM0_REGMAP|UHD_ONLY');">UHD_ONLY</span>
</p>
<div class="sh" id="div_AXI_HPM0_REGMAP|UHD_ONLY">
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_0" onclick="a('AXI_HPM0_REGMAP|QSFP_0_0');">QSFP_0_0</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_1" onclick="a('AXI_HPM0_REGMAP|QSFP_0_1');">QSFP_0_1</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_2" onclick="a('AXI_HPM0_REGMAP|QSFP_0_2');">QSFP_0_2</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_3" onclick="a('AXI_HPM0_REGMAP|QSFP_0_3');">QSFP_0_3</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_0" onclick="a('AXI_HPM0_REGMAP|QSFP_1_0');">QSFP_1_0</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_1" onclick="a('AXI_HPM0_REGMAP|QSFP_1_1');">QSFP_1_1</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_2" onclick="a('AXI_HPM0_REGMAP|QSFP_1_2');">QSFP_1_2</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_3" onclick="a('AXI_HPM0_REGMAP|QSFP_1_3');">QSFP_1_3</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_MB_CPLD_PS_REGMAP" onclick="pm('MB_CPLD_PS_REGMAP');">+</span>
<span class="regmap" id="a_MB_CPLD_PS_REGMAP" onclick="a('MB_CPLD_PS_REGMAP');">MB_CPLD_PS_REGMAP</span>
</p> <div class="sh" id="div_MB_CPLD_PS_REGMAP">
<p>
<span class="pm" id="pm_MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS" onclick="pm('MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS');">+</span>
<span class="group" id="a_MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS" onclick="a('MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS');">MB_CPLD_PS_WINDOWS</span>
</p>
<div class="sh" id="div_MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS">
<p><span class="register" id="a_MB_CPLD_PS_REGMAP|PS_REGISTERS" onclick="a('MB_CPLD_PS_REGMAP|PS_REGISTERS');">PS_REGISTERS</span></p>
<p><span class="register" id="a_MB_CPLD_PS_REGMAP|RECONFIG" onclick="a('MB_CPLD_PS_REGMAP|RECONFIG');">RECONFIG</span></p>
<p><span class="register" id="a_MB_CPLD_PS_REGMAP|POWER_REGISTERS" onclick="a('MB_CPLD_PS_REGMAP|POWER_REGISTERS');">POWER_REGISTERS</span></p>
</div>
<p>
<span class="pm" id="pm_MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS" onclick="pm('MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS');">+</span>
<span class="group" id="a_MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS" onclick="a('MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS');">PS_SPI_ENDPOINTS</span>
</p>
<div class="sh" id="div_MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS">
<p><span class="enum" id="a_MB_CPLD_PS_REGMAP|SPI_ENDPOINT" onclick="a('MB_CPLD_PS_REGMAP|SPI_ENDPOINT');">enum SPI_ENDPOINT</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CMAC_REGMAP" onclick="pm('CMAC_REGMAP');">+</span>
<span class="regmap" id="a_CMAC_REGMAP" onclick="a('CMAC_REGMAP');">CMAC_REGMAP</span>
</p> <div class="sh" id="div_CMAC_REGMAP">
<p>
<span class="pm" id="pm_CMAC_REGMAP|XILINX_CMAC_REGISTERS" onclick="pm('CMAC_REGMAP|XILINX_CMAC_REGISTERS');">+</span>
<span class="group" id="a_CMAC_REGMAP|XILINX_CMAC_REGISTERS" onclick="a('CMAC_REGMAP|XILINX_CMAC_REGISTERS');">XILINX_CMAC_REGISTERS</span>
</p>
<div class="sh" id="div_CMAC_REGMAP|XILINX_CMAC_REGISTERS">
</div>
</div>
<p>
<span class="pm" id="pm_CONSTANTS_REGMAP" onclick="pm('CONSTANTS_REGMAP');">+</span>
<span class="regmap" id="a_CONSTANTS_REGMAP" onclick="a('CONSTANTS_REGMAP');">CONSTANTS_REGMAP</span>
</p> <div class="sh" id="div_CONSTANTS_REGMAP">
<p>
<span class="pm" id="pm_CONSTANTS_REGMAP|CONSTANTS_GROUP" onclick="pm('CONSTANTS_REGMAP|CONSTANTS_GROUP');">+</span>
<span class="group" id="a_CONSTANTS_REGMAP|CONSTANTS_GROUP" onclick="a('CONSTANTS_REGMAP|CONSTANTS_GROUP');">CONSTANTS_GROUP</span>
</p>
<div class="sh" id="div_CONSTANTS_REGMAP|CONSTANTS_GROUP">
<p><span class="enum" id="a_CONSTANTS_REGMAP|CONSTANTS_ENUM" onclick="a('CONSTANTS_REGMAP|CONSTANTS_ENUM');">enum CONSTANTS_ENUM</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CORE_REGS_REGMAP" onclick="pm('CORE_REGS_REGMAP');">+</span>
<span class="regmap" id="a_CORE_REGS_REGMAP" onclick="a('CORE_REGS_REGMAP');">CORE_REGS_REGMAP</span>
</p> <div class="sh" id="div_CORE_REGS_REGMAP">
<p>
<span class="pm" id="pm_CORE_REGS_REGMAP|CORE_REGS" onclick="pm('CORE_REGS_REGMAP|CORE_REGS');">+</span>
<span class="group" id="a_CORE_REGS_REGMAP|CORE_REGS" onclick="a('CORE_REGS_REGMAP|CORE_REGS');">CORE_REGS</span>
</p>
<div class="sh" id="div_CORE_REGS_REGMAP|CORE_REGS">
<p><span class="register" id="a_CORE_REGS_REGMAP|GLOBAL_REGS" onclick="a('CORE_REGS_REGMAP|GLOBAL_REGS');">GLOBAL_REGS</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|VERSIONING_REGS" onclick="a('CORE_REGS_REGMAP|VERSIONING_REGS');">VERSIONING_REGS</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|TIMEKEEPER_A" onclick="a('CORE_REGS_REGMAP|TIMEKEEPER_A');">TIMEKEEPER_A</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|TIMEKEEPER_B" onclick="a('CORE_REGS_REGMAP|TIMEKEEPER_B');">TIMEKEEPER_B</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|DIO" onclick="a('CORE_REGS_REGMAP|DIO');">DIO</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP" onclick="pm('CPLD_INTERFACE_REGMAP');">+</span>
<span class="regmap" id="a_CPLD_INTERFACE_REGMAP" onclick="a('CPLD_INTERFACE_REGMAP');">CPLD_INTERFACE_REGMAP</span>
</p> <div class="sh" id="div_CPLD_INTERFACE_REGMAP">
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS" onclick="pm('CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS');">+</span>
<span class="group" id="a_CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS" onclick="a('CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS');">CPLD_INTERFACE_REGS</span>
</p>
<div class="sh" id="div_CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS">
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER" onclick="a('CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER');">SIGNATURE_REGISTER</span></p>
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER" onclick="a('CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER');">SCRATCH_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS" onclick="pm('CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS');">+</span>
<span class="group" id="a_CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS" onclick="a('CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS');">CPLD_SPI_CONTROL_REGS</span>
</p>
<div class="sh" id="div_CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS">
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER" onclick="a('CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER');">MOTHERBOARD_CPLD_DIVIDER</span></p>
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER" onclick="a('CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER');">DAUGHTERBOARD_CPLD_DIVIDER</span></p>
</div>
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP|IPASS_REGS" onclick="pm('CPLD_INTERFACE_REGMAP|IPASS_REGS');">+</span>
<span class="group" id="a_CPLD_INTERFACE_REGMAP|IPASS_REGS" onclick="a('CPLD_INTERFACE_REGMAP|IPASS_REGS');">IPASS_REGS</span>
</p>
<div class="sh" id="div_CPLD_INTERFACE_REGMAP|IPASS_REGS">
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|IPASS_CONTROL" onclick="a('CPLD_INTERFACE_REGMAP|IPASS_CONTROL');">IPASS_CONTROL</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_DIG_IFC_REGMAP" onclick="pm('DIG_IFC_REGMAP');">+</span>
<span class="regmap" id="a_DIG_IFC_REGMAP" onclick="a('DIG_IFC_REGMAP');">DIG_IFC_REGMAP</span>
</p> <div class="sh" id="div_DIG_IFC_REGMAP">
<p>
<span class="pm" id="pm_DIG_IFC_REGMAP|SPI_OVER_GPIO_REGS" onclick="pm('DIG_IFC_REGMAP|SPI_OVER_GPIO_REGS');">+</span>
<span class="group" id="a_DIG_IFC_REGMAP|SPI_OVER_GPIO_REGS" onclick="a('DIG_IFC_REGMAP|SPI_OVER_GPIO_REGS');">SPI_OVER_GPIO_REGS</span>
</p>
<div class="sh" id="div_DIG_IFC_REGMAP|SPI_OVER_GPIO_REGS">
<p><span class="register" id="a_DIG_IFC_REGMAP|SPI_SLAVE_CONFIG" onclick="a('DIG_IFC_REGMAP|SPI_SLAVE_CONFIG');">SPI_SLAVE_CONFIG</span></p>
<p><span class="register" id="a_DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG" onclick="a('DIG_IFC_REGMAP|SPI_TRANSACTION_CONFIG');">SPI_TRANSACTION_CONFIG</span></p>
<p><span class="register" id="a_DIG_IFC_REGMAP|SPI_TRANSACTION_GO" onclick="a('DIG_IFC_REGMAP|SPI_TRANSACTION_GO');">SPI_TRANSACTION_GO</span></p>
<p><span class="register" id="a_DIG_IFC_REGMAP|SPI_STATUS" onclick="a('DIG_IFC_REGMAP|SPI_STATUS');">SPI_STATUS</span></p>
<p><span class="register" id="a_DIG_IFC_REGMAP|CONTROLLER_INFO" onclick="a('DIG_IFC_REGMAP|CONTROLLER_INFO');">CONTROLLER_INFO</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_DIO_REGMAP" onclick="pm('DIO_REGMAP');">+</span>
<span class="regmap" id="a_DIO_REGMAP" onclick="a('DIO_REGMAP');">DIO_REGMAP</span>
</p> <div class="sh" id="div_DIO_REGMAP">
<p>
<span class="pm" id="pm_DIO_REGMAP|DIO_REGS" onclick="pm('DIO_REGMAP|DIO_REGS');">+</span>
<span class="group" id="a_DIO_REGMAP|DIO_REGS" onclick="a('DIO_REGMAP|DIO_REGS');">DIO_REGS</span>
</p>
<div class="sh" id="div_DIO_REGMAP|DIO_REGS">
<p><span class="register" id="a_DIO_REGMAP|DIO_MASTER_REGISTER" onclick="a('DIO_REGMAP|DIO_MASTER_REGISTER');">DIO_MASTER_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_DIRECTION_REGISTER" onclick="a('DIO_REGMAP|DIO_DIRECTION_REGISTER');">DIO_DIRECTION_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_INPUT_REGISTER" onclick="a('DIO_REGMAP|DIO_INPUT_REGISTER');">DIO_INPUT_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_OUTPUT_REGISTER" onclick="a('DIO_REGMAP|DIO_OUTPUT_REGISTER');">DIO_OUTPUT_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_SOURCE_REGISTER" onclick="a('DIO_REGMAP|DIO_SOURCE_REGISTER');">DIO_SOURCE_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|RADIO_SOURCE_REGISTER" onclick="a('DIO_REGMAP|RADIO_SOURCE_REGISTER');">RADIO_SOURCE_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|INTERFACE_DIO_SELECT" onclick="a('DIO_REGMAP|INTERFACE_DIO_SELECT');">INTERFACE_DIO_SELECT</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_OVERRIDE" onclick="a('DIO_REGMAP|DIO_OVERRIDE');">DIO_OVERRIDE</span></p>
<p><span class="register" id="a_DIO_REGMAP|SW_DIO_CONTROL" onclick="a('DIO_REGMAP|SW_DIO_CONTROL');">SW_DIO_CONTROL</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_DMA_REGMAP" onclick="pm('DMA_REGMAP');">+</span>
<span class="regmap" id="a_DMA_REGMAP" onclick="a('DMA_REGMAP');">DMA_REGMAP</span>
</p> <div class="sh" id="div_DMA_REGMAP">
<p>
<span class="pm" id="pm_DMA_REGMAP|XILINX_DMA_REGISTERS" onclick="pm('DMA_REGMAP|XILINX_DMA_REGISTERS');">+</span>
<span class="group" id="a_DMA_REGMAP|XILINX_DMA_REGISTERS" onclick="a('DMA_REGMAP|XILINX_DMA_REGISTERS');">XILINX_DMA_REGISTERS</span>
</p>
<div class="sh" id="div_DMA_REGMAP|XILINX_DMA_REGISTERS">
</div>
</div>
<p>
<span class="pm" id="pm_ETH_DMA_CTRL_REGMAP" onclick="pm('ETH_DMA_CTRL_REGMAP');">+</span>
<span class="regmap" id="a_ETH_DMA_CTRL_REGMAP" onclick="a('ETH_DMA_CTRL_REGMAP');">ETH_DMA_CTRL_REGMAP</span>
</p> <div class="sh" id="div_ETH_DMA_CTRL_REGMAP">
<p>
<span class="pm" id="pm_ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL" onclick="pm('ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL');">+</span>
<span class="group" id="a_ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL" onclick="a('ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL');">ETH_DMA_CTRL</span>
</p>
<div class="sh" id="div_ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL">
<p><span class="register" id="a_ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL" onclick="a('ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL');">AXI_DMA_CTRL</span></p>
<p><span class="register" id="a_ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL" onclick="a('ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL');">ETH_IO_CTRL</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_GLOBAL_REGS_REGMAP" onclick="pm('GLOBAL_REGS_REGMAP');">+</span>
<span class="regmap" id="a_GLOBAL_REGS_REGMAP" onclick="a('GLOBAL_REGS_REGMAP');">GLOBAL_REGS_REGMAP</span>
</p> <div class="sh" id="div_GLOBAL_REGS_REGMAP">
<p>
<span class="pm" id="pm_GLOBAL_REGS_REGMAP|GLOBAL_REGS" onclick="pm('GLOBAL_REGS_REGMAP|GLOBAL_REGS');">+</span>
<span class="group" id="a_GLOBAL_REGS_REGMAP|GLOBAL_REGS" onclick="a('GLOBAL_REGS_REGMAP|GLOBAL_REGS');">GLOBAL_REGS</span>
</p>
<div class="sh" id="div_GLOBAL_REGS_REGMAP|GLOBAL_REGS">
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|COMPAT_NUM_REG" onclick="a('GLOBAL_REGS_REGMAP|COMPAT_NUM_REG');">COMPAT_NUM_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DATESTAMP_REG" onclick="a('GLOBAL_REGS_REGMAP|DATESTAMP_REG');">DATESTAMP_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GIT_HASH_REG" onclick="a('GLOBAL_REGS_REGMAP|GIT_HASH_REG');">GIT_HASH_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|SCRATCH_REG" onclick="a('GLOBAL_REGS_REGMAP|SCRATCH_REG');">SCRATCH_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_ID_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_ID_REG');">DEVICE_ID_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|RFNOC_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|RFNOC_INFO_REG');">RFNOC_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG');">CLOCK_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CTRL_REG');">PPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG');">DBOARD_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG" onclick="a('GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG');">NUM_TIMEKEEPERS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG" onclick="a('GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG');">SERIAL_NUM_LOW_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG" onclick="a('GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG');">SERIAL_NUM_HIGH_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG');">MFG_TEST_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG');">MFG_TEST_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG');">QSFP_PORT_0_0_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG');">QSFP_PORT_0_1_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG');">QSFP_PORT_0_2_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG');">QSFP_PORT_0_3_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG');">QSFP_PORT_1_0_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG');">QSFP_PORT_1_1_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG');">QSFP_PORT_1_2_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_GPIO_ATR_REGMAP" onclick="pm('GPIO_ATR_REGMAP');">+</span>
<span class="regmap" id="a_GPIO_ATR_REGMAP" onclick="a('GPIO_ATR_REGMAP');">GPIO_ATR_REGMAP</span>
</p> <div class="sh" id="div_GPIO_ATR_REGMAP">
<p>
<span class="pm" id="pm_GPIO_ATR_REGMAP|GPIO_ATR_REGS" onclick="pm('GPIO_ATR_REGMAP|GPIO_ATR_REGS');">+</span>
<span class="group" id="a_GPIO_ATR_REGMAP|GPIO_ATR_REGS" onclick="a('GPIO_ATR_REGMAP|GPIO_ATR_REGS');">GPIO_ATR_REGS</span>
</p>
<div class="sh" id="div_GPIO_ATR_REGMAP|GPIO_ATR_REGS">
<p><span class="register" id="a_GPIO_ATR_REGMAP|ATR_STATE" onclick="a('GPIO_ATR_REGMAP|ATR_STATE');">ATR_STATE</span></p>
<p><span class="register" id="a_GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG" onclick="a('GPIO_ATR_REGMAP|CLASSIC_ATR_CONFIG');">CLASSIC_ATR_CONFIG</span></p>
<p><span class="register" id="a_GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER" onclick="a('GPIO_ATR_REGMAP|ATR_OPTION_REGISTRER');">ATR_OPTION_REGISTRER</span></p>
<p><span class="register" id="a_GPIO_ATR_REGMAP|GPIO_DIR" onclick="a('GPIO_ATR_REGMAP|GPIO_DIR');">GPIO_DIR</span></p>
<p><span class="register" id="a_GPIO_ATR_REGMAP|GPIO_DISABLED" onclick="a('GPIO_ATR_REGMAP|GPIO_DISABLED');">GPIO_DISABLED</span></p>
<p><span class="register" id="a_GPIO_ATR_REGMAP|GPIO_IN" onclick="a('GPIO_ATR_REGMAP|GPIO_IN');">GPIO_IN</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_JTAG_REGMAP" onclick="pm('JTAG_REGMAP');">+</span>
<span class="regmap" id="a_JTAG_REGMAP" onclick="a('JTAG_REGMAP');">JTAG_REGMAP</span>
</p> <div class="sh" id="div_JTAG_REGMAP">
<p>
<span class="pm" id="pm_JTAG_REGMAP|JTAG_REGS" onclick="pm('JTAG_REGMAP|JTAG_REGS');">+</span>
<span class="group" id="a_JTAG_REGMAP|JTAG_REGS" onclick="a('JTAG_REGMAP|JTAG_REGS');">JTAG_REGS</span>
</p>
<div class="sh" id="div_JTAG_REGMAP|JTAG_REGS">
<p><span class="register" id="a_JTAG_REGMAP|TX_DATA" onclick="a('JTAG_REGMAP|TX_DATA');">TX_DATA</span></p>
<p><span class="register" id="a_JTAG_REGMAP|STB_DATA" onclick="a('JTAG_REGMAP|STB_DATA');">STB_DATA</span></p>
<p><span class="register" id="a_JTAG_REGMAP|CONTROL" onclick="a('JTAG_REGMAP|CONTROL');">CONTROL</span></p>
<p><span class="register" id="a_JTAG_REGMAP|RX_DATA" onclick="a('JTAG_REGMAP|RX_DATA');">RX_DATA</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_MB_CPLD_PL_REGMAP" onclick="pm('MB_CPLD_PL_REGMAP');">+</span>
<span class="regmap" id="a_MB_CPLD_PL_REGMAP" onclick="a('MB_CPLD_PL_REGMAP');">MB_CPLD_PL_REGMAP</span>
</p> <div class="sh" id="div_MB_CPLD_PL_REGMAP">
<p>
<span class="pm" id="pm_MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS" onclick="pm('MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS');">+</span>
<span class="group" id="a_MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS" onclick="a('MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS');">MB_CPLD_PL_WINDOWS</span>
</p>
<div class="sh" id="div_MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS">
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|PL_REGISTERS" onclick="a('MB_CPLD_PL_REGMAP|PL_REGISTERS');">PL_REGISTERS</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|JTAG_DB0" onclick="a('MB_CPLD_PL_REGMAP|JTAG_DB0');">JTAG_DB0</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|JTAG_DB1" onclick="a('MB_CPLD_PL_REGMAP|JTAG_DB1');">JTAG_DB1</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_NIXGE_REGMAP" onclick="pm('NIXGE_REGMAP');">+</span>
<span class="regmap" id="a_NIXGE_REGMAP" onclick="a('NIXGE_REGMAP');">NIXGE_REGMAP</span>
</p> <div class="sh" id="div_NIXGE_REGMAP">
<p>
<span class="pm" id="pm_NIXGE_REGMAP|XGE_MAC_REGS" onclick="pm('NIXGE_REGMAP|XGE_MAC_REGS');">+</span>
<span class="group" id="a_NIXGE_REGMAP|XGE_MAC_REGS" onclick="a('NIXGE_REGMAP|XGE_MAC_REGS');">XGE_MAC_REGS</span>
</p>
<div class="sh" id="div_NIXGE_REGMAP|XGE_MAC_REGS">
<p><span class="register" id="a_NIXGE_REGMAP|PORT_INFO" onclick="a('NIXGE_REGMAP|PORT_INFO');">PORT_INFO</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|MAC_CTRL_STATUS" onclick="a('NIXGE_REGMAP|MAC_CTRL_STATUS');">MAC_CTRL_STATUS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|MAC_PHY_STATUS" onclick="a('NIXGE_REGMAP|MAC_PHY_STATUS');">MAC_PHY_STATUS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|MAC_LED_CTL" onclick="a('NIXGE_REGMAP|MAC_LED_CTL');">MAC_LED_CTL</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|ETH_MDIO_BASE" onclick="a('NIXGE_REGMAP|ETH_MDIO_BASE');">ETH_MDIO_BASE</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_OVERRUNS" onclick="a('NIXGE_REGMAP|AURORA_OVERRUNS');">AURORA_OVERRUNS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS" onclick="a('NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS');">AURORA_CHECKSUM_ERRORS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS" onclick="a('NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS');">AURORA_BIST_CHECKER_SAMPS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS" onclick="a('NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS');">AURORA_BIST_CHECKER_ERRORS</span></p>
</div>
<p>
<span class="pm" id="pm_NIXGE_REGMAP|XGE_MAC_WINDOW" onclick="pm('NIXGE_REGMAP|XGE_MAC_WINDOW');">+</span>
<span class="group" id="a_NIXGE_REGMAP|XGE_MAC_WINDOW" onclick="a('NIXGE_REGMAP|XGE_MAC_WINDOW');">XGE_MAC_WINDOW</span>
</p>
<div class="sh" id="div_NIXGE_REGMAP|XGE_MAC_WINDOW">
<p><span class="register" id="a_NIXGE_REGMAP|XGE_MAC" onclick="a('NIXGE_REGMAP|XGE_MAC');">XGE_MAC</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP" onclick="pm('PL_CPLD_BASE_REGMAP');">+</span>
<span class="regmap" id="a_PL_CPLD_BASE_REGMAP" onclick="a('PL_CPLD_BASE_REGMAP');">PL_CPLD_BASE_REGMAP</span>
</p> <div class="sh" id="div_PL_CPLD_BASE_REGMAP">
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS" onclick="pm('PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS');">+</span>
<span class="group" id="a_PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS" onclick="a('PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS');">MB_CPLD_LED_REGS</span>
</p>
<div class="sh" id="div_PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS">
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|LED_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|LED_REGISTER');">LED_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP|PL_CMI_REGS" onclick="pm('PL_CPLD_BASE_REGMAP|PL_CMI_REGS');">+</span>
<span class="group" id="a_PL_CPLD_BASE_REGMAP|PL_CMI_REGS" onclick="a('PL_CPLD_BASE_REGMAP|PL_CMI_REGS');">PL_CMI_REGS</span>
</p>
<div class="sh" id="div_PL_CPLD_BASE_REGMAP|PL_CMI_REGS">
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG" onclick="a('PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG');">CABLE_PRESENT_REG</span></p>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS" onclick="pm('PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS');">+</span>
<span class="group" id="a_PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS" onclick="a('PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS');">PL_CPLD_BASE_REGS</span>
</p>
<div class="sh" id="div_PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS">
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER');">SIGNATURE_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|REVISION_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|REVISION_REGISTER');">REVISION_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER');">OLDEST_COMPATIBLE_REVISION_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER');">SCRATCH_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER');">GIT_HASH_REGISTER</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_REGMAP" onclick="pm('PL_CPLD_REGMAP');">+</span>
<span class="regmap" id="a_PL_CPLD_REGMAP" onclick="a('PL_CPLD_REGMAP');">PL_CPLD_REGMAP</span>
</p> <div class="sh" id="div_PL_CPLD_REGMAP">
<p>
<span class="pm" id="pm_PL_CPLD_REGMAP|PL_CPLD_WINDOWS" onclick="pm('PL_CPLD_REGMAP|PL_CPLD_WINDOWS');">+</span>
<span class="group" id="a_PL_CPLD_REGMAP|PL_CPLD_WINDOWS" onclick="a('PL_CPLD_REGMAP|PL_CPLD_WINDOWS');">PL_CPLD_WINDOWS</span>
</p>
<div class="sh" id="div_PL_CPLD_REGMAP|PL_CPLD_WINDOWS">
<p><span class="register" id="a_PL_CPLD_REGMAP|BASE" onclick="a('PL_CPLD_REGMAP|BASE');">BASE</span></p>
<p><span class="register" id="a_PL_CPLD_REGMAP|MB_CPLD" onclick="a('PL_CPLD_REGMAP|MB_CPLD');">MB_CPLD</span></p>
<p><span class="register" id="a_PL_CPLD_REGMAP|DB0_CPLD" onclick="a('PL_CPLD_REGMAP|DB0_CPLD');">DB0_CPLD</span></p>
<p><span class="register" id="a_PL_CPLD_REGMAP|DB1_CPLD" onclick="a('PL_CPLD_REGMAP|DB1_CPLD');">DB1_CPLD</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PL_DMA_MASTER_REGMAP" onclick="pm('PL_DMA_MASTER_REGMAP');">+</span>
<span class="regmap" id="a_PL_DMA_MASTER_REGMAP" onclick="a('PL_DMA_MASTER_REGMAP');">PL_DMA_MASTER_REGMAP</span>
</p> <div class="sh" id="div_PL_DMA_MASTER_REGMAP">
<p>
<span class="pm" id="pm_PL_DMA_MASTER_REGMAP|HPC0_DMA" onclick="pm('PL_DMA_MASTER_REGMAP|HPC0_DMA');">+</span>
<span class="group" id="a_PL_DMA_MASTER_REGMAP|HPC0_DMA" onclick="a('PL_DMA_MASTER_REGMAP|HPC0_DMA');">HPC0_DMA</span>
</p>
<div class="sh" id="div_PL_DMA_MASTER_REGMAP|HPC0_DMA">
<p><span class="register" id="a_PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW" onclick="a('PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW');">AXI_HPC0_WINDOW</span></p>
</div>
<p>
<span class="pm" id="pm_PL_DMA_MASTER_REGMAP|HPC1_DMA" onclick="pm('PL_DMA_MASTER_REGMAP|HPC1_DMA');">+</span>
<span class="group" id="a_PL_DMA_MASTER_REGMAP|HPC1_DMA" onclick="a('PL_DMA_MASTER_REGMAP|HPC1_DMA');">HPC1_DMA</span>
</p>
<div class="sh" id="div_PL_DMA_MASTER_REGMAP|HPC1_DMA">
<p><span class="register" id="a_PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW" onclick="a('PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW');">AXI_HPC1_WINDOW</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP" onclick="pm('PS_CPLD_BASE_REGMAP');">+</span>
<span class="regmap" id="a_PS_CPLD_BASE_REGMAP" onclick="a('PS_CPLD_BASE_REGMAP');">PS_CPLD_BASE_REGMAP</span>
</p> <div class="sh" id="div_PS_CPLD_BASE_REGMAP">
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|DIO_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|DIO_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|DIO_REGS" onclick="a('PS_CPLD_BASE_REGMAP|DIO_REGS');">DIO_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|DIO_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER');">DIO_DIRECTION_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|PS_CMI_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|PS_CMI_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|PS_CMI_REGS" onclick="a('PS_CPLD_BASE_REGMAP|PS_CMI_REGS');">PS_CMI_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|PS_CMI_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG" onclick="a('PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG');">SERIAL_NUM_LOW_REG</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG" onclick="a('PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG');">SERIAL_NUM_HIGH_REG</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS" onclick="a('PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS');">CMI_CONTROL_STATUS</span></p>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS" onclick="a('PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS');">PS_CONTROL_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|PL_DB_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|PL_DB_REGISTER');">PL_DB_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS" onclick="a('PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS');">PS_CPLD_BASE_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER');">SIGNATURE_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|REVISION_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|REVISION_REGISTER');">REVISION_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER');">OLDEST_COMPATIBLE_REVISION_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER');">SCRATCH_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER');">GIT_HASH_REGISTER</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PS_POWER_REGMAP" onclick="pm('PS_POWER_REGMAP');">+</span>
<span class="regmap" id="a_PS_POWER_REGMAP" onclick="a('PS_POWER_REGMAP');">PS_POWER_REGMAP</span>
</p> <div class="sh" id="div_PS_POWER_REGMAP">
<p>
<span class="pm" id="pm_PS_POWER_REGMAP|PS_POWER_REGS" onclick="pm('PS_POWER_REGMAP|PS_POWER_REGS');">+</span>
<span class="group" id="a_PS_POWER_REGMAP|PS_POWER_REGS" onclick="a('PS_POWER_REGMAP|PS_POWER_REGS');">PS_POWER_REGS</span>
</p>
<div class="sh" id="div_PS_POWER_REGMAP|PS_POWER_REGS">
<p><span class="register" id="a_PS_POWER_REGMAP|IPASS_POWER_REG" onclick="a('PS_POWER_REGMAP|IPASS_POWER_REG');">IPASS_POWER_REG</span></p>
<p><span class="register" id="a_PS_POWER_REGMAP|OSC_POWER_REG" onclick="a('PS_POWER_REGMAP|OSC_POWER_REG');">OSC_POWER_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_QSFP_REGMAP" onclick="pm('QSFP_REGMAP');">+</span>
<span class="regmap" id="a_QSFP_REGMAP" onclick="a('QSFP_REGMAP');">QSFP_REGMAP</span>
</p> <div class="sh" id="div_QSFP_REGMAP">
<p>
<span class="pm" id="pm_QSFP_REGMAP|QSFP_WINDOWS" onclick="pm('QSFP_REGMAP|QSFP_WINDOWS');">+</span>
<span class="group" id="a_QSFP_REGMAP|QSFP_WINDOWS" onclick="a('QSFP_REGMAP|QSFP_WINDOWS');">QSFP_WINDOWS</span>
</p>
<div class="sh" id="div_QSFP_REGMAP|QSFP_WINDOWS">
<p><span class="register" id="a_QSFP_REGMAP|ETH_DMA" onclick="a('QSFP_REGMAP|ETH_DMA');">ETH_DMA</span></p>
<p><span class="register" id="a_QSFP_REGMAP|NIXGE" onclick="a('QSFP_REGMAP|NIXGE');">NIXGE</span></p>
<p><span class="register" id="a_QSFP_REGMAP|UIO" onclick="a('QSFP_REGMAP|UIO');">UIO</span></p>
<p><span class="register" id="a_QSFP_REGMAP|CMAC" onclick="a('QSFP_REGMAP|CMAC');">CMAC</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RADIO_CTRLPORT_REGMAP" onclick="pm('RADIO_CTRLPORT_REGMAP');">+</span>
<span class="regmap" id="a_RADIO_CTRLPORT_REGMAP" onclick="a('RADIO_CTRLPORT_REGMAP');">RADIO_CTRLPORT_REGMAP</span>
</p> <div class="sh" id="div_RADIO_CTRLPORT_REGMAP">
<p>
<span class="pm" id="pm_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS" onclick="pm('RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS');">+</span>
<span class="group" id="a_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS" onclick="a('RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS');">RADIO_CTRLPORT_WINDOWS</span>
</p>
<div class="sh" id="div_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS">
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|DB_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|DB_WINDOW');">DB_WINDOW</span></p>
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW');">RFDC_TIMING_WINDOW</span></p>
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|DIO_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|DIO_WINDOW');">DIO_WINDOW</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RADIO_DIO_REGMAP" onclick="pm('RADIO_DIO_REGMAP');">+</span>
<span class="regmap" id="a_RADIO_DIO_REGMAP" onclick="a('RADIO_DIO_REGMAP');">RADIO_DIO_REGMAP</span>
</p> <div class="sh" id="div_RADIO_DIO_REGMAP">
<p>
<span class="pm" id="pm_RADIO_DIO_REGMAP|DIO_SOURCES" onclick="pm('RADIO_DIO_REGMAP|DIO_SOURCES');">+</span>
<span class="group" id="a_RADIO_DIO_REGMAP|DIO_SOURCES" onclick="a('RADIO_DIO_REGMAP|DIO_SOURCES');">DIO_SOURCES</span>
</p>
<div class="sh" id="div_RADIO_DIO_REGMAP|DIO_SOURCES">
<p><span class="register" id="a_RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS" onclick="a('RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS');">RADIO_GPIO_ATR_REGS</span></p>
<p><span class="register" id="a_RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL" onclick="a('RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL');">DIO_SOURCE_CONTROL</span></p>
<p><span class="register" id="a_RADIO_DIO_REGMAP|DIGITAL_IFC_REGS" onclick="a('RADIO_DIO_REGMAP|DIGITAL_IFC_REGS');">DIGITAL_IFC_REGS</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RECONFIG_REGMAP" onclick="pm('RECONFIG_REGMAP');">+</span>
<span class="regmap" id="a_RECONFIG_REGMAP" onclick="a('RECONFIG_REGMAP');">RECONFIG_REGMAP</span>
</p> <div class="sh" id="div_RECONFIG_REGMAP">
<p>
<span class="pm" id="pm_RECONFIG_REGMAP|RECONFIG_REGS" onclick="pm('RECONFIG_REGMAP|RECONFIG_REGS');">+</span>
<span class="group" id="a_RECONFIG_REGMAP|RECONFIG_REGS" onclick="a('RECONFIG_REGMAP|RECONFIG_REGS');">RECONFIG_REGS</span>
</p>
<div class="sh" id="div_RECONFIG_REGMAP|RECONFIG_REGS">
<p><span class="enum" id="a_RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM" onclick="a('RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM');">enum FLASH_PRIMARY_IMAGE_ADDR_ENUM</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_STATUS_REG" onclick="a('RECONFIG_REGMAP|FLASH_STATUS_REG');">FLASH_STATUS_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CONTROL_REG" onclick="a('RECONFIG_REGMAP|FLASH_CONTROL_REG');">FLASH_CONTROL_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_ADDR_REG');">FLASH_ADDR_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_WRITE_DATA_REG" onclick="a('RECONFIG_REGMAP|FLASH_WRITE_DATA_REG');">FLASH_WRITE_DATA_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_READ_DATA_REG" onclick="a('RECONFIG_REGMAP|FLASH_READ_DATA_REG');">FLASH_READ_DATA_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG');">FLASH_CFM0_START_ADDR_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG');">FLASH_CFM0_END_ADDR_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RFDC_REGS_REGMAP" onclick="pm('RFDC_REGS_REGMAP');">+</span>
<span class="regmap" id="a_RFDC_REGS_REGMAP" onclick="a('RFDC_REGS_REGMAP');">RFDC_REGS_REGMAP</span>
</p> <div class="sh" id="div_RFDC_REGS_REGMAP">
<p>
<span class="pm" id="pm_RFDC_REGS_REGMAP|RFDC_REGS" onclick="pm('RFDC_REGS_REGMAP|RFDC_REGS');">+</span>
<span class="group" id="a_RFDC_REGS_REGMAP|RFDC_REGS" onclick="a('RFDC_REGS_REGMAP|RFDC_REGS');">RFDC_REGS</span>
</p>
<div class="sh" id="div_RFDC_REGS_REGMAP|RFDC_REGS">
<p><span class="enum" id="a_RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM" onclick="a('RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM');">enum FABRIC_DSP_BW_ENUM</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|MMCM" onclick="a('RFDC_REGS_REGMAP|MMCM');">MMCM</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|INVERT_DB0_IQ_REG" onclick="a('RFDC_REGS_REGMAP|INVERT_DB0_IQ_REG');">INVERT_DB0_IQ_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|INVERT_DB1_IQ_REG" onclick="a('RFDC_REGS_REGMAP|INVERT_DB1_IQ_REG');">INVERT_DB1_IQ_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|MMCM_RESET_REG" onclick="a('RFDC_REGS_REGMAP|MMCM_RESET_REG');">MMCM_RESET_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG');">RF_RESET_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_RESET_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_RESET_STATUS_REG');">RF_RESET_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_AXI_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_AXI_STATUS_REG');">RF_AXI_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|FABRIC_DSP_REG" onclick="a('RFDC_REGS_REGMAP|FABRIC_DSP_REG');">FABRIC_DSP_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|CALIBRATION_DATA" onclick="a('RFDC_REGS_REGMAP|CALIBRATION_DATA');">CALIBRATION_DATA</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|CALIBRATION_ENABLE" onclick="a('RFDC_REGS_REGMAP|CALIBRATION_ENABLE');">CALIBRATION_ENABLE</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|THRESHOLD_STATUS" onclick="a('RFDC_REGS_REGMAP|THRESHOLD_STATUS');">THRESHOLD_STATUS</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG');">RF_PLL_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_PLL_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_PLL_STATUS_REG');">RF_PLL_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|ADC_TILEMAP_REG" onclick="a('RFDC_REGS_REGMAP|ADC_TILEMAP_REG');">ADC_TILEMAP_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|DAC_TILEMAP_REG" onclick="a('RFDC_REGS_REGMAP|DAC_TILEMAP_REG');">DAC_TILEMAP_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RFDC_INFO_REG" onclick="a('RFDC_REGS_REGMAP|RFDC_INFO_REG');">RFDC_INFO_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RFDC_TIMING_REGMAP" onclick="pm('RFDC_TIMING_REGMAP');">+</span>
<span class="regmap" id="a_RFDC_TIMING_REGMAP" onclick="a('RFDC_TIMING_REGMAP');">RFDC_TIMING_REGMAP</span>
</p> <div class="sh" id="div_RFDC_TIMING_REGMAP">
<p>
<span class="pm" id="pm_RFDC_TIMING_REGMAP|RFDC_TIMING_REGS" onclick="pm('RFDC_TIMING_REGMAP|RFDC_TIMING_REGS');">+</span>
<span class="group" id="a_RFDC_TIMING_REGMAP|RFDC_TIMING_REGS" onclick="a('RFDC_TIMING_REGMAP|RFDC_TIMING_REGS');">RFDC_TIMING_REGS</span>
</p>
<div class="sh" id="div_RFDC_TIMING_REGMAP|RFDC_TIMING_REGS">
<p><span class="register" id="a_RFDC_TIMING_REGMAP|NCO_RESET_REG" onclick="a('RFDC_TIMING_REGMAP|NCO_RESET_REG');">NCO_RESET_REG</span></p>
<p><span class="register" id="a_RFDC_TIMING_REGMAP|GEARBOX_RESET_REG" onclick="a('RFDC_TIMING_REGMAP|GEARBOX_RESET_REG');">GEARBOX_RESET_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_SPI_REGMAP" onclick="pm('SPI_REGMAP');">+</span>
<span class="regmap" id="a_SPI_REGMAP" onclick="a('SPI_REGMAP');">SPI_REGMAP</span>
</p> <div class="sh" id="div_SPI_REGMAP">
<p>
<span class="pm" id="pm_SPI_REGMAP|SPI_REGS" onclick="pm('SPI_REGMAP|SPI_REGS');">+</span>
<span class="group" id="a_SPI_REGMAP|SPI_REGS" onclick="a('SPI_REGMAP|SPI_REGS');">SPI_REGS</span>
</p>
<div class="sh" id="div_SPI_REGMAP|SPI_REGS">
<p><span class="register" id="a_SPI_REGMAP|RX_DATA_LOW" onclick="a('SPI_REGMAP|RX_DATA_LOW');">RX_DATA_LOW</span></p>
<p><span class="register" id="a_SPI_REGMAP|RX_DATA_HIGH" onclick="a('SPI_REGMAP|RX_DATA_HIGH');">RX_DATA_HIGH</span></p>
<p><span class="register" id="a_SPI_REGMAP|TX_DATA_LOW" onclick="a('SPI_REGMAP|TX_DATA_LOW');">TX_DATA_LOW</span></p>
<p><span class="register" id="a_SPI_REGMAP|TX_DATA_HIGH" onclick="a('SPI_REGMAP|TX_DATA_HIGH');">TX_DATA_HIGH</span></p>
<p><span class="register" id="a_SPI_REGMAP|CONTROL" onclick="a('SPI_REGMAP|CONTROL');">CONTROL</span></p>
<p><span class="register" id="a_SPI_REGMAP|CLOCK_DIVIDER" onclick="a('SPI_REGMAP|CLOCK_DIVIDER');">CLOCK_DIVIDER</span></p>
<p><span class="register" id="a_SPI_REGMAP|SLAVE_SELECT" onclick="a('SPI_REGMAP|SLAVE_SELECT');">SLAVE_SELECT</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_UIO_REGMAP" onclick="pm('UIO_REGMAP');">+</span>
<span class="regmap" id="a_UIO_REGMAP" onclick="a('UIO_REGMAP');">UIO_REGMAP</span>
</p> <div class="sh" id="div_UIO_REGMAP">
<p>
<span class="pm" id="pm_UIO_REGMAP|UIO_REGS" onclick="pm('UIO_REGMAP|UIO_REGS');">+</span>
<span class="group" id="a_UIO_REGMAP|UIO_REGS" onclick="a('UIO_REGMAP|UIO_REGS');">UIO_REGS</span>
</p>
<div class="sh" id="div_UIO_REGMAP|UIO_REGS">
<p><span class="register" id="a_UIO_REGMAP|IP" onclick="a('UIO_REGMAP|IP');">IP</span></p>
<p><span class="register" id="a_UIO_REGMAP|UDP" onclick="a('UIO_REGMAP|UDP');">UDP</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_MAC_LSB" onclick="a('UIO_REGMAP|BRIDGE_MAC_LSB');">BRIDGE_MAC_LSB</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_MAC_MSB" onclick="a('UIO_REGMAP|BRIDGE_MAC_MSB');">BRIDGE_MAC_MSB</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_IP" onclick="a('UIO_REGMAP|BRIDGE_IP');">BRIDGE_IP</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_UDP" onclick="a('UIO_REGMAP|BRIDGE_UDP');">BRIDGE_UDP</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_ENABLE" onclick="a('UIO_REGMAP|BRIDGE_ENABLE');">BRIDGE_ENABLE</span></p>
<p><span class="register" id="a_UIO_REGMAP|CHDR_DROPPED" onclick="a('UIO_REGMAP|CHDR_DROPPED');">CHDR_DROPPED</span></p>
<p><span class="register" id="a_UIO_REGMAP|CPU_DROPPED" onclick="a('UIO_REGMAP|CPU_DROPPED');">CPU_DROPPED</span></p>
<p><span class="register" id="a_UIO_REGMAP|PAUSE" onclick="a('UIO_REGMAP|PAUSE');">PAUSE</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_VERSIONING_REGS_REGMAP" onclick="pm('VERSIONING_REGS_REGMAP');">+</span>
<span class="regmap" id="a_VERSIONING_REGS_REGMAP" onclick="a('VERSIONING_REGS_REGMAP');">VERSIONING_REGS_REGMAP</span>
</p> <div class="sh" id="div_VERSIONING_REGS_REGMAP">
<p>
<span class="pm" id="pm_VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS" onclick="pm('VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS');">+</span>
<span class="group" id="a_VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS" onclick="a('VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS');">VERSIONING_CONSTANTS</span>
</p>
<div class="sh" id="div_VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS">
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION" onclick="a('VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION');">enum CPLD_IFC_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION" onclick="a('VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION');">enum DB_GPIO_IFC_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|FPGA_VERSION" onclick="a('VERSIONING_REGS_REGMAP|FPGA_VERSION');">enum FPGA_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION" onclick="a('VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION');">enum RF_CORE_100M_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION" onclick="a('VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION');">enum RF_CORE_400M_VERSION</span></p>
</div>
<p>
<span class="pm" id="pm_VERSIONING_REGS_REGMAP|VERSIONING_REGS" onclick="pm('VERSIONING_REGS_REGMAP|VERSIONING_REGS');">+</span>
<span class="group" id="a_VERSIONING_REGS_REGMAP|VERSIONING_REGS" onclick="a('VERSIONING_REGS_REGMAP|VERSIONING_REGS');">VERSIONING_REGS</span>
</p>
<div class="sh" id="div_VERSIONING_REGS_REGMAP|VERSIONING_REGS">
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES" onclick="a('VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES');">enum COMPONENTS_INDEXES</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|CURRENT_VERSION" onclick="a('VERSIONING_REGS_REGMAP|CURRENT_VERSION');">CURRENT_VERSION</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION" onclick="a('VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION');">OLDEST_COMPATIBLE_VERSION</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED" onclick="a('VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED');">VERSION_LAST_MODIFIED</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|RESERVED" onclick="a('VERSIONING_REGS_REGMAP|RESERVED');">RESERVED</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_XGE_MAC_REGMAP" onclick="pm('XGE_MAC_REGMAP');">+</span>
<span class="regmap" id="a_XGE_MAC_REGMAP" onclick="a('XGE_MAC_REGMAP');">XGE_MAC_REGMAP</span>
</p> <div class="sh" id="div_XGE_MAC_REGMAP">
<p>
<span class="pm" id="pm_XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS" onclick="pm('XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS');">+</span>
<span class="group" id="a_XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS" onclick="a('XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS');">OPENCORE_XGE_REGISTERS</span>
</p>
<div class="sh" id="div_XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS">
</div>
</div>
</div>
</body>
</HTML>
top/x400/doc/X410/X410_FPGA_right.htm
+25951
View File
File diff suppressed because one or more lines are too long
top/x400/ip/Makefile.inc
+48 -20
View File
@@ -5,7 +5,6 @@
#
include $(IP_DIR)/xge_pcs_pma/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
@@ -14,11 +13,9 @@ include $(IP_DIR)/axi_inter_2x64_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_4x64_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_1x128_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_2x128_512_bd/Makefile.inc
include $(IP_DIR)/ddr4_64bits/Makefile.inc
include $(IP_DIR)/adc_100m_bd/Makefile.inc
include $(IP_DIR)/adc_400m_bd/Makefile.inc
include $(IP_DIR)/dac_100m_bd/Makefile.inc
include $(IP_DIR)/dac_400m_bd/Makefile.inc
include $(IP_DIR)/axi_inter_4x128_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_1x512_512_bd/Makefile.inc
include $(IP_DIR)/axi_inter_2x512_512_bd/Makefile.inc
include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
include $(IP_DIR)/fifo_short_2clk/Makefile.inc
include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
@@ -27,6 +24,15 @@ include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc
include $(IP_DIR)/hb47_1to2/Makefile.inc
include $(IP_DIR)/hb47_2to1/Makefile.inc
ifdef X410
include $(IP_DIR)/ddr4_64bits/Makefile.inc
include $(IP_DIR)/adc_100m_bd/Makefile.inc
include $(IP_DIR)/adc_400m_bd/Makefile.inc
include $(IP_DIR)/dac_100m_bd/Makefile.inc
include $(IP_DIR)/dac_400m_bd/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
endif
BD_SRCS = \
$(IP_X4XX_PS_RFDC_BD_SRCS) \
$(IP_X4XX_PS_RFDC_HDL_SRCS) \
@@ -40,21 +46,27 @@ $(IP_AXI_INTER_2X64_512_BD_SRCS) \
$(IP_AXI_INTER_4X64_512_BD_SRCS) \
$(IP_AXI_INTER_1X128_512_BD_SRCS) \
$(IP_AXI_INTER_2X128_512_BD_SRCS) \
$(IP_ADC_100M_BD_SRCS) \
$(IP_ADC_100M_HDL_SRCS) \
$(IP_DAC_100M_BD_SRCS) \
$(IP_DAC_100M_HDL_SRCS) \
$(IP_ADC_400M_BD_SRCS) \
$(IP_ADC_400M_HDL_SRCS) \
$(IP_DAC_400M_BD_SRCS) \
$(IP_DAC_400M_HDL_SRCS) \
$(IP_AXI_INTER_4X128_512_BD_SRCS) \
$(IP_AXI_INTER_1X512_512_BD_SRCS) \
$(IP_AXI_INTER_2X512_512_BD_SRCS) \
$(IP_100G_BD_SRCS) \
$(IP_100G_HDL_SRCS) \
$(IP_AXI_ETH_DMA_BD_SRCS) \
$(IP_AXI_ETH_DMA_BD_HDL_SRCS)
ifdef X410
BD_SRCS += \
$(IP_ADC_100M_BD_SRCS) \
$(IP_ADC_100M_HDL_SRCS) \
$(IP_DAC_100M_BD_SRCS) \
$(IP_DAC_100M_HDL_SRCS) \
$(IP_ADC_400M_BD_SRCS) \
$(IP_ADC_400M_HDL_SRCS) \
$(IP_DAC_400M_BD_SRCS) \
$(IP_DAC_400M_HDL_SRCS)
endif
IP_XCI_SRCS = \
$(IP_DDR4_64BITS_SRCS) \
$(IP_XGE_PCS_PMA_SRCS) \
$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
@@ -62,6 +74,11 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_HB47_1TO2_SRCS) \
$(IP_HB47_2TO1_SRCS) \
ifdef X410
IP_XCI_SRCS += \
$(IP_DDR4_64BITS_SRCS)
endif
BD_OUTPUTS = \
$(BD_X4XX_PS_RFDC_BD_OUTS) \
$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
@@ -72,15 +89,21 @@ $(BD_AXI_INTER_2x64_512_BD_OUTS) \
$(BD_AXI_INTER_4x64_512_BD_OUTS) \
$(BD_AXI_INTER_1X128_512_BD_OUTS) \
$(BD_AXI_INTER_2X128_512_BD_OUTS) \
$(BD_ADC_100M_BD_OUTS) \
$(BD_ADC_400M_BD_OUTS) \
$(BD_DAC_100M_BD_OUTS) \
$(BD_DAC_400M_BD_OUTS) \
$(BD_AXI_INTER_4x128_512_BD_OUTS) \
$(BD_AXI_INTER_1X512_512_BD_OUTS) \
$(BD_AXI_INTER_2X512_512_BD_OUTS) \
$(BD_100G_BD_OUTS) \
$(BD_AXI_ETH_DMA_BD_OUTS)
ifdef X410
BD_OUTPUTS += \
$(BD_ADC_100M_BD_OUTS) \
$(BD_ADC_400M_BD_OUTS) \
$(BD_DAC_100M_BD_OUTS) \
$(BD_DAC_400M_BD_OUTS)
endif
IP_SYNTH_OUTPUTS = \
$(IP_DDR4_64BITS_OUTS) \
$(IP_XGE_PCS_PMA_OUTS) \
$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
$(IP_FIFO_SHORT_2CLK_OUTS) \
@@ -88,6 +111,11 @@ $(IP_FIFO_4K_2CLK_OUTS) \
$(IP_HB47_1TO2_OUTS) \
$(IP_HB47_2TO1_OUTS) \
ifdef X410
IP_SYNTH_OUTPUTS += \
$(IP_DDR4_64BITS_OUTS)
endif
IP_HDL_SIM_SRCS = \
$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \
$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \
top/x400/ip/axi_inter_1x512_512_bd/Makefile.inc
+32
View File
@@ -0,0 +1,32 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_1X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd.tcl \
)
IP_AXI_INTER_1X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd.tcl \
)
IP_AXI_INTER_1X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.bd \
)
BD_AXI_INTER_1X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
axi_inter_1x512_512_bd.bd.out \
axi_inter_1x512_512_bd/axi_inter_1x512_512_bd_ooc.xdc \
axi_inter_1x512_512_bd/synth/axi_inter_1x512_512_bd.v \
)
.INTERMEDIATE: IP_AXI_INTER_1X512_512_BD_TRGT
$(IP_AXI_INTER_1X512_512_BD_SRCS) $(BD_AXI_INTER_1X512_512_BD_OUTS) $(IP_AXI_INTER_1X512_512_BDTCL_SRCS): IP_AXI_INTER_1X512_512_BD_TRGT
@:
IP_AXI_INTER_1X512_512_BD_TRGT: $(IP_AXI_INTER_1X512_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_1x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.tcl
+314
View File
@@ -0,0 +1,314 @@
################################################################
# This is a generated script based on design: axi_inter_1x512_512_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_inter_1x512_512_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_inter_1x512_512_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_data_fifo:2.1\
xilinx.com:ip:axi_register_slice:2.1\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4} \
] $M_AXI
set S_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S_AXI
# Create ports
set M_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M_AXI} \
CONFIG.ASSOCIATED_RESET {M_AXI_ARESETN} \
] $M_AXI_ACLK
set M_AXI_ARESETN [ create_bd_port -dir I -type rst M_AXI_ARESETN ]
set S_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {S_AXI} \
CONFIG.ASSOCIATED_RESET {S_AXI_ARESETN} \
] $S_AXI_ACLK
set S_AXI_ARESETN [ create_bd_port -dir I -type rst S_AXI_ARESETN ]
# Create instance: axi_clock_converter_0, and set properties
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: axi_data_fifo_0, and set properties
set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_0
# Create instance: axi_data_fifo_1, and set properties
set axi_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_1
# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
] $axi_register_slice_0
# Create instance: axi_register_slice_2, and set properties
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {2} \
] $axi_register_slice_2
# Create interface connections
connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_data_fifo_0/S_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_1_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_data_fifo_1/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_data_fifo_1/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_ports M_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
# Create port connections
connect_bd_net -net m_axi_aclk_0_1 [get_bd_ports M_AXI_ACLK] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_register_slice_2/aclk]
connect_bd_net -net m_axi_aresetn_0_1 [get_bd_ports M_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axi_register_slice_2/aresetn]
connect_bd_net -net s_axi_aclk_0_1 [get_bd_ports S_AXI_ACLK] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_data_fifo_1/aclk] [get_bd_pins axi_register_slice_0/aclk]
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_ports S_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_data_fifo_1/aresetn] [get_bd_pins axi_register_slice_0/aresetn]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/axi_inter_2x512_512_bd/Makefile.inc
+32
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@@ -0,0 +1,32 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_2X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd.tcl \
)
IP_AXI_INTER_2X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd.tcl \
)
IP_AXI_INTER_2X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.bd \
)
BD_AXI_INTER_2X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \
axi_inter_2x512_512_bd.bd.out \
axi_inter_2x512_512_bd/axi_inter_2x512_512_bd_ooc.xdc \
axi_inter_2x512_512_bd/synth/axi_inter_2x512_512_bd.v \
)
.INTERMEDIATE: IP_AXI_INTER_2X512_512_BD_TRGT
$(IP_AXI_INTER_2X512_512_BD_SRCS) $(BD_AXI_INTER_2X512_512_BD_OUTS) $(IP_AXI_INTER_2X512_512_BDTCL_SRCS): IP_AXI_INTER_2X512_512_BD_TRGT
@:
IP_AXI_INTER_2X512_512_BD_TRGT: $(IP_AXI_INTER_2X512_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_2x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.tcl
+380
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@@ -0,0 +1,380 @@
################################################################
# This is a generated script based on design: axi_inter_2x512_512_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_inter_2x512_512_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_inter_2x512_512_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_crossbar:2.1\
xilinx.com:ip:axi_data_fifo:2.1\
xilinx.com:ip:axi_register_slice:2.1\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4} \
] $M0_AXI
set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S0_AXI
set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S1_AXI
# Create ports
set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
] $M0_AXI_ACLK
set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_LOW} \
] $M0_AXI_ARESETN
set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \
CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN:S0_AXI_ARESETN} \
] $S0_AXI_ACLK
set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
# Create instance: axi_clock_converter_0, and set properties
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: axi_crossbar_0, and set properties
set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {2} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {2} \
] $axi_crossbar_0
# Create instance: axi_data_fifo_0, and set properties
set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_0
# Create instance: axi_data_fifo_1, and set properties
set axi_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_1
# Create instance: axi_data_fifo_2, and set properties
set axi_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.READ_FIFO_DEPTH {512} \
CONFIG.WRITE_FIFO_DEPTH {512} \
] $axi_data_fifo_2
# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
] $axi_register_slice_0
# Create instance: axi_register_slice_1, and set properties
set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
] $axi_register_slice_1
# Create instance: axi_register_slice_2, and set properties
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {2} \
] $axi_register_slice_2
# Create interface connections
connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_data_fifo_0/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_crossbar_0/M00_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_1_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_data_fifo_1/M_AXI]
connect_bd_intf_net -intf_net axi_data_fifo_2_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_data_fifo_2/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_data_fifo_1/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_data_fifo_2/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
# Create port connections
connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_register_slice_2/aclk]
connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axi_register_slice_2/aresetn]
connect_bd_net -net s_axi_aclk_0_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_data_fifo_1/aclk] [get_bd_pins axi_data_fifo_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk]
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_data_fifo_1/aresetn] [get_bd_pins axi_data_fifo_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/axi_inter_4x128_512_bd/Makefile.inc
+32
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@@ -0,0 +1,32 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTER_4X128_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd.tcl \
)
IP_AXI_INTER_4X128_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd.tcl \
)
IP_AXI_INTER_4X128_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.bd \
)
BD_AXI_INTER_4X128_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \
axi_inter_4x128_512_bd.bd.out \
axi_inter_4x128_512_bd/axi_inter_4x128_512_bd_ooc.xdc \
axi_inter_4x128_512_bd/synth/axi_inter_4x128_512_bd.v \
)
.INTERMEDIATE: IP_AXI_INTER_4X128_512_BD_TRGT
$(IP_AXI_INTER_4X128_512_BD_SRCS) $(BD_AXI_INTER_4X128_512_BD_OUTS) $(IP_AXI_INTER_4X128_512_BDTCL_SRCS): IP_AXI_INTER_4X128_512_BD_TRGT
@:
IP_AXI_INTER_4X128_512_BD_TRGT: $(IP_AXI_INTER_4X128_512_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_inter_4x128_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.tcl
+823
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@@ -0,0 +1,823 @@
################################################################
# This is a generated script based on design: axi_inter_4x128_512_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_inter_4x128_512_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffve1156-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_inter_4x128_512_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_crossbar:2.1\
xilinx.com:ip:axi_dwidth_converter:2.1\
xilinx.com:ip:axi_register_slice:2.1\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {512} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4} \
] $M0_AXI
set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S0_AXI
set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S1_AXI
set S2_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S2_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S2_AXI
set S3_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S3_AXI ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {350000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {1} \
CONFIG.MAX_BURST_LENGTH {256} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {1} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $S3_AXI
# Create ports
set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
] $M0_AXI_ACLK
set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_LOW} \
] $M0_AXI_ARESETN
set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI:S2_AXI:S3_AXI} \
CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
] $S0_AXI_ACLK
set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
# Create instance: axi_crossbar_0, and set properties
set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {4} \
CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A00_ADDR_WIDTH {0} \
CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A00_ADDR_WIDTH {0} \
CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A00_ADDR_WIDTH {0} \
CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A00_ADDR_WIDTH {0} \
CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A00_ADDR_WIDTH {0} \
CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A00_ADDR_WIDTH {0} \
CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A00_ADDR_WIDTH {0} \
CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A00_ADDR_WIDTH {0} \
CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A00_ADDR_WIDTH {0} \
CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A00_ADDR_WIDTH {0} \
CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A00_ADDR_WIDTH {0} \
CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A00_ADDR_WIDTH {0} \
CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A00_ADDR_WIDTH {0} \
CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A00_ADDR_WIDTH {0} \
CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A00_ADDR_WIDTH {0} \
CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {4} \
CONFIG.S01_BASE_ID {0x00000004} \
CONFIG.S02_BASE_ID {0x00000008} \
CONFIG.S03_BASE_ID {0x0000000c} \
CONFIG.S04_BASE_ID {0x00000010} \
CONFIG.S05_BASE_ID {0x00000014} \
CONFIG.S06_BASE_ID {0x00000018} \
CONFIG.S07_BASE_ID {0x0000001c} \
CONFIG.S08_BASE_ID {0x00000020} \
CONFIG.S09_BASE_ID {0x00000024} \
CONFIG.S10_BASE_ID {0x00000028} \
CONFIG.S11_BASE_ID {0x0000002c} \
CONFIG.S12_BASE_ID {0x00000030} \
CONFIG.S13_BASE_ID {0x00000034} \
CONFIG.S14_BASE_ID {0x00000038} \
CONFIG.S15_BASE_ID {0x0000003c} \
] $axi_crossbar_0
# Create instance: axi_dwidth_converter_0, and set properties
set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_0
# Create instance: axi_dwidth_converter_1, and set properties
set axi_dwidth_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_1 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_1
# Create instance: axi_dwidth_converter_2, and set properties
set axi_dwidth_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_2 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_2
# Create instance: axi_dwidth_converter_3, and set properties
set axi_dwidth_converter_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_3 ]
set_property -dict [ list \
CONFIG.ACLK_ASYNC {1} \
CONFIG.FIFO_MODE {2} \
CONFIG.MI_DATA_WIDTH {512} \
CONFIG.SI_DATA_WIDTH {128} \
CONFIG.SI_ID_WIDTH {1} \
CONFIG.SYNCHRONIZATION_STAGES {3} \
] $axi_dwidth_converter_3
# Create instance: axi_register_slice_0, and set properties
set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_0
# Create instance: axi_register_slice_1, and set properties
set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_1
# Create instance: axi_register_slice_2, and set properties
set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_2
# Create instance: axi_register_slice_3, and set properties
set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {128} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_3
# Create instance: axi_register_slice_4, and set properties
set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_4
# Create instance: axi_register_slice_5, and set properties
set axi_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_5 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_5
# Create instance: axi_register_slice_6, and set properties
set axi_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_6 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_6
# Create instance: axi_register_slice_7, and set properties
set axi_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_7 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ID_WIDTH {1} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_7
# Create instance: axi_register_slice_8, and set properties
set axi_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_8 ]
set_property -dict [ list \
CONFIG.ID_WIDTH {4} \
CONFIG.REG_AR {1} \
CONFIG.REG_AW {1} \
CONFIG.REG_B {1} \
] $axi_register_slice_8
# Create interface connections
connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
connect_bd_intf_net -intf_net S_AXI_2_1 [get_bd_intf_ports S2_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI]
connect_bd_intf_net -intf_net S_AXI_3_1 [get_bd_intf_ports S3_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI]
connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_register_slice_8/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins axi_register_slice_4/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/M_AXI] [get_bd_intf_pins axi_register_slice_5/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/M_AXI] [get_bd_intf_pins axi_register_slice_6/S_AXI]
connect_bd_intf_net -intf_net axi_dwidth_converter_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_3/M_AXI] [get_bd_intf_pins axi_register_slice_7/S_AXI]
connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_3/S_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_4_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_register_slice_4/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_5_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_register_slice_5/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_6_M_AXI [get_bd_intf_pins axi_crossbar_0/S02_AXI] [get_bd_intf_pins axi_register_slice_6/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_7_M_AXI [get_bd_intf_pins axi_crossbar_0/S03_AXI] [get_bd_intf_pins axi_register_slice_7/M_AXI]
connect_bd_intf_net -intf_net axi_register_slice_8_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_8/M_AXI]
# Create port connections
connect_bd_net -net S0_AXI_ACLK [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_dwidth_converter_1/s_axi_aclk] [get_bd_pins axi_dwidth_converter_2/s_axi_aclk] [get_bd_pins axi_dwidth_converter_3/s_axi_aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk]
connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn]
connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins axi_dwidth_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_2/m_axi_aclk] [get_bd_pins axi_dwidth_converter_3/m_axi_aclk] [get_bd_pins axi_register_slice_4/aclk] [get_bd_pins axi_register_slice_5/aclk] [get_bd_pins axi_register_slice_6/aclk] [get_bd_pins axi_register_slice_7/aclk] [get_bd_pins axi_register_slice_8/aclk]
connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/m_axi_aresetn] [get_bd_pins axi_register_slice_4/aresetn] [get_bd_pins axi_register_slice_5/aresetn] [get_bd_pins axi_register_slice_6/aresetn] [get_bd_pins axi_register_slice_8/aresetn]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v
+509
View File
@@ -0,0 +1,509 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: common_regs
// Description:
// Common registers definition within the x4xx_ps_rfdc_bd between
// different x4xx variants.
//XmlParse xml_on
//<regmap name="AXI_HPM0_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <info>
// This is the map for the register space that the Processing System's
// M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
// This port has a 40-bit address bus.
// </info>
// <group name="COMMON">
// <window name="RPU" offset="0x0080000000" size="0x00010000">
// <info>Space reserved for RPU access</info>
// </window>
// <window name="JTAG_ENGINE" offset="0x1000000000" size="0x1000">
// <info>Register space for the JTAG engine for MB CPLD programming.</info>
// </window>
// <window name="RESERVED" offset="0x100003F000" size="0x1000">
// <info>Register space reserved for future use.</info>
// </window>
// <window name="MPM_ENDPOINT" offset="0x1000080000" size="0x20000"
// targetregmap="PL_CPLD_REGMAP">
// <info>MPM endpoint fro MB/DB communication.</info>
// </window>
// <window name="CORE_REGS" offset="0x10000A0000" size="0x4000"
// targetregmap="CORE_REGS_REGMAP">
// <info>Register space reserved for mboard-regs (Core).</info>
// </window>
// <window name="INT_ETH_DMA" offset="0x10000A4000" size="0x6000"
// targetregmap="ETH_DMA_CTRL_REGMAP">
// <info>AXI DMA engine for internal Ethernet interface.</info>
// </window>
// <window name="INT_ETH_REGS" offset="0x10000AA000" size="0x2000">
// <info>Misc. registers for internal Ethernet.</info>
// </window>
// <window name="RFDC" offset="0x1000100000" size="0x40000">
// <info>Register space occupied by the Xilinx RFDC IP block.</info>
// </window>
// <window name="RFDC_REGS" offset="0x1000140000" size="0x20000"
// targetregmap="RFDC_REGS_REGMAP">
// <info>Register space for RFDC control/status registers.</info>
// </window>
// </group>
//</regmap>
//
//<regmap name="ETH_DMA_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is the map that the nixge driver uses in Ethernet DMA to
// move data between the Processing System's architecture and the fabric.
// This map is a combination of two main components: a Xilix AXI DMA engine
// and some registers for MAC/PHY control.
// </info>
// <group name="ETH_DMA_CTRL">
// <window name="AXI_DMA_CTRL" offset="0x0" size="0x4000">
// <info>
// Refer to Xilinx' AXI DMA v7.1 IP product guide for further
// information on this register map:
// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
// </info>
// </window>
// <window name="ETH_IO_CTRL" offset="0x4000" size="0x2000">
// <info>MAC/PHY control for the Ethernet interface.</info>
// </window>
// </group>
//</regmap>
//<regmap name="PL_DMA_MASTER_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is a regmap to document the different ports that have access to the PS system memory.
// Each port may have different restrictions on system memory. See the corresponding window
// for details
// </info>
// <group name="HPC0_DMA">
// <window name="AXI_HPC0_WINDOW" offset="0x0" size="0x10000000000">
// <info>
// The HPC0 port of the PS is used for general purpose cache-coherent accesses
// to the PS system memory. Different applications may use it for different
// purposes. Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
// <group name="HPC1_DMA">
// <window name="AXI_HPC1_WINDOW" offset="0x0" size="0x1000000000">
// <info>
// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
// Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
//</regmap>
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <regtype name="RF_RESET_CONTROL_REGTYPE" size="32">
// <info>
// Control register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
// Assert either the *_RESET or *_ENABLE bitfields.
// Wait until DB*_DONE is asserted to release the trigger.
// The DB*_DONE signal should then de-assert.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET" range="0">
// <info>
// Write a '1' to this bit to reset the RF reset controller.
// Write a '0' once db0_fsm_reset_done asserts.
// </info>
// </bitfield>
// <bitfield name="ADC_RESET" range="4">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="ADC_ENABLE" range="5">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 ADC chain. Write a '0' once
// db0_adc_seq_done is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_RESET" range="8">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_ENABLE" range="9">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 DAC chain. Write a '0' once
// db0_dac_seq_done is asserted.
// </info>
// </bitfield>
// </regtype>
//
// <regtype name="RF_RESET_STATUS_REGTYPE" size="32" writable="false">
// <info>
// Status register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// Refer to RF*_RESET_CONTROL_REG for instructions on how to use
// the status bits in this register.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET_DONE" range="3">
// <info>
// This bit asserts ('1') when the DB0 RF reset controller FSM
// reset sequence is completed. The bitfield deasserts ('0')
// after deasserting db0_fsm_reset.
// </info>
// </bitfield>
// <bitfield name="ADC_SEQ_DONE" range="7">
// <info>
// This bit asserts ('1') when the DB0 ADC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// <bitfield name="DAC_SEQ_DONE" range="11">
// <info>
// This bit asserts ('1') when the DB0 DAC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// </regtype>
//
// <regtype name="RF_AXI_STATUS_REGTYPE" size="32" writable="false">
// <info>
// Status register for the RF AXI-Stream interfaces.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="RFDC_DAC_TREADY" range="1..0">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID" range="3..2">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY" range="5..4">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY" range="7..6">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID" range="9..8">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID" range="11..10">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID" range="13..12">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY" range="15..14">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TREADY_DB1" range="17..16">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID_DB1" range="19..18">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY_DB1" range="21..20">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY_DB1" range="23..22">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID_DB1" range="25..24">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID_DB1" range="27..26">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID_DB1" range="29..28">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY_DB1" range="31..30">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// </regtype>
//
// <enumeratedtype name="FABRIC_DSP_BW_ENUM" showhex="true">
// <value name="FABRIC_DSP_BW_NONE" integer="0"/>
// <value name="FABRIC_DSP_BW_100M" integer="100"/>
// <value name="FABRIC_DSP_BW_200M" integer="200"/>
// <value name="FABRIC_DSP_BW_400M" integer="400"/>
// <value name="FABRIC_DSP_BW_FULL" integer="1000"/>
// </enumeratedtype>
//
// <regtype name="FABRIC_DSP_REGTYPE" size="32" writable="false">
// <info>
// This register provides information to the driver on the type
// of DSP that is instantiated in the fabric.{BR/}
// The X410 platform supports multiple RF daughterboards, each requiring
// a different fabric RF DSP chain that works with specific RFDC settings.
// Each bandwidth DSP chain has a unique identifier (BW in MHz), this
// information is conveyed in this register to let the driver
// configure the RFDC with the proper settings.
// Also, channel count for the DSP module is included.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FABRIC_DSP_RX_CNT" range="3..0" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT" range="7..4" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RESERVED" range="9..8" initialvalue="0">
// <info>Reserved for future use.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RX_CNT_DB1" range="13..10" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT_DB1" range="17..14" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RESERVED_DB1" range="19..18" initialvalue="0">
// <info>Reserved for future use.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_BW" range="31..20" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
// <info>Fabric DSP BW in MHz for both daughterboards.</info>
// </bitfield>
// </regtype>
//
// <regtype name="RFDC_INFO_REGTYPE" size="32" writable="false">
// <info>
// This register provides information about how the RFDC is connected to
// the rest of the fabric.{BR/}
// Specifically, between the actual RFDC and the RFNoC infrastructure,
// there may be additional resampling (if the RFDC resampler cannot handle
// all the resampling itself) and it is important to know how wide the
// connection from the RFDC gearbox FIFO to the rest of the design is.
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="RFDC_INFO_XTRA_RESAMP" range="3..0" initialvalue="1">
// <info>Additional resampling happening outside the RFDC for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_RX" range="6..4" initialvalue="1">
// <info>Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_TX" range="9..7" initialvalue="1">
// <info>Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_XTRA_RESAMP_DB1" range="19..16" initialvalue="1">
// <info>Additional resampling happening outside the RFDC for daughterboard 0.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_RX_DB1" range="22..20" initialvalue="1">
// <info>Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.</info>
// </bitfield>
// <bitfield name="RFDC_INFO_SPC_TX_DB1" range="25..23" initialvalue="1">
// <info>Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.</info>
// </bitfield>
// </regtype>
//
// <regtype name="ADC_TILEMAP_REGTYPE" size="32" writable="false">
// <info>
// This register describes how the ADCs map to the respective tiles. It
// lets us designate an ADC as channel 0, channel 1, etc. depending on
// how those channels are externally connected to the RFSoC.{BR/}
//
// For every channel, this register stores the tile number and the block
// number of the converter. This can be used to then address the correct
// converter in the various Xilinx interfaces/APIs.
// </info>
// <bitfield name="ADC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
// <info>Tile number of the ADC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
// <info>Tile number of the ADC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
// <info>Tile number of the ADC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
// <info>Tile number of the ADC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
// <info>Tile number of the ADC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
// <info>Tile number of the ADC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
// <info>Tile number of the ADC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
// <info>Tile number of the ADC for channel 3, daughterboard 1.</info>
// </bitfield>
// <bitfield name="ADC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 1.</info>
// </bitfield>
// </regtype>
// <regtype name="DAC_TILEMAP_REGTYPE" size="32" writable="false">
// <info>
// This register describes how the DACs map to the respective tiles. It
// lets us designate an DAC as channel 0, channel 1, etc. depending on
// how those channels are externally connected to the RFSoC.{BR/}
//
// For every channel, this register stores the tile number and the block
// number of the converter. This can be used to then address the correct
// converter in the various Xilinx interfaces/APIs.
// </info>
// <bitfield name="DAC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
// <info>Tile number of the DAC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
// <info>Tile number of the DAC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
// <info>Tile number of the DAC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
// <info>Tile number of the DAC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 0.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
// <info>Tile number of the DAC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
// <info>Tile number of the DAC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
// <info>Tile number of the DAC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
// <info>Tile number of the DAC for channel 3, daughterboard 1.</info>
// </bitfield>
// <bitfield name="DAC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 1.</info>
// </bitfield>
// </regtype>
//
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/uhd_regs.v
+336
View File
@@ -0,0 +1,336 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: uhd_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<regmap name="CMAC_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_CMAC_REGISTERS">
// <info>
// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.
//
// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
//
// </info>
// </group>
//</regmap>
//XmlParse xml_on
//<regmap name="XGE_MAC_REGMAP" markdown="true" generateverilog="false">
// <group name="OPENCORE_XGE_REGISTERS">
// <info>
//
// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="DMA_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_DMA_REGISTERS">
// <info>
// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
//
// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="NIXGE_REGMAP" markdown="true" generateverilog="false">
// <group name="XGE_MAC_WINDOW">
// <window name="XGE_MAC" offset="0x1000" size="0x1000" targetregmap="XGE_MAC_REGMAP"/>
// </group>
// <group name="XGE_MAC_REGS">
// <info>
// nixge (maps to 10g mac if present)
// </info>
// <register name="PORT_INFO" offset="0x0000">
// <bitfield name="COMPAT_NUM" range="31..24">
// <info>
// Constant indicating version for this space.
// Not used by the NIXGE driver (12/4/2020)
// </info>
// </bitfield>
// <bitfield name="ACTIVITY" range="17">
// <info>
// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="LINK_UP" range="16">
// <info>
// Generically means that a connection with a peer has been established. Specific
// meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="MGT_PROTOCOL" range="15..8">
// <info>
// Constant indicating what flavor of communication this port is using
//
// - 0 = NONE
// - 1 = 1GbE
// - 2 = 10GbE
// - 3 = Aurora
// - 4 = WhiteRabbit
// - 5 = 100GbE
//
// </info>
// </bitfield>
// <bitfield name="PORTNUM" range="7..0">
// <info>
// Constant indicating which port this register is hooked to
//
// - 0 = QSFP0
// - 1 = QSFP1
//
// </info>
// </bitfield>
// </register>
// <register name="MAC_CTRL_STATUS" offset="0x0004">
// <info>
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status*
//
// - 0 = status_crc_error
// - 1 = status_fragment_error
// - 2 = status_txdfifo_ovflow
// - 3 = status_txdfifo_udflow
// - 4 = status_rxdfifo_ovflow
// - 5 = status_rxdfifo_udflow
// - 6 = status_pause_frame_rx
// - 7 = status_local_fault
// - 8 = status_remote_fault
//
// *WRITE - Ctl*
//
// - 0 = ctrl_tx_enable
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 1 = tx_unfout - Sets if TX underflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 2 = stat_rx_aligned - goes high when CMAC has finished
// alignment, and is ready to start reception of traffic.
// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
// but upstream is trying to hold(TREADY)off we drop a packet.
// Upstream circuitry should detect this when traffic is forked
// between CHDR and CPU, so this bit will only set if there is a
// HW design error.
// - 4 = auto_config_done - This bit goes high when the auto_config
// state machine finishes operation. It is very similiar to
// stat_rx_alligned, but waits for extra writes which occur
// after allignement to complete.
// - 24:16 = pause_mask - readable version of pause_mask bellow.
//
// *WRITE - Ctl*
//
// - 0 = auto_enable - Defaults to ON after reset - Enables a
// state machine that performs CMAC register writes to
// bring up the MAC without SW intervention.
// - 24:16 = pause_mask - A second layer of enables(the first being
// register in the CMAC) on the pause_request mechanic. Bits
// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
// request (not priority controlled). The mask is used for TX
// and RX.
// </info>
// </register>
// <register name="MAC_PHY_STATUS" offset="0x0008">
// <info>
//
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status *
//
// - 0 = core_status 0 - link_up
// - 1 = core_status 1
// - 2 = core_status 2
// - 3 = core_status 3
// - 4 = core_status 4
// - 5 = core_status 5
// - 6 = core_status 6
// - 7 = core_status 7
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
// - 1 = usr_rx_reset - RX PLL's have locked
//
// </info>
// </register>
// <register name="MAC_LED_CTL" offset="0x000C">
// <bitfield name="identify_enable" range="0">
// <info>
// When set identify_value is used to control the activity LED.
// When clear the activity LED set on any TX or RX traffic to the mgt
// </info>
// </bitfield>
// <bitfield name="identify_value" range="1">
// <info>
// When identify_enable is set, this value controls the activity LED.
// </info>
// </bitfield>
// </register>
// <register name="ETH_MDIO_BASE" offset="0x0010">
// <info>
// The x4xx family of products does not use MDIO.
// </info>
// </register>
// <register name="AURORA_OVERRUNS" offset="0x0020">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_CHECKSUM_ERRORS" offset="0x0024">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_SAMPS" offset="0x0028">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_ERRORS" offset="0x002C">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// </group>
//</regmap>
//
//<regmap name="UIO_REGMAP" markdown="true" generateverilog="false">
// <group name="UIO_REGS">
// <info>
// UIO
// </info>
// <register name="IP" offset="0x0000">
// <info>
// Set this port's IP address
// </info>
// </register>
// <register name="UDP" offset="0x0004">
// <info>
// Set the UDP port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_MAC_LSB" offset="0x0010">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_MAC_MSB" offset="0x0014">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_IP" offset="0x0018">
// <info>
// If BRIDGE_ENABLE is set use this IP Address
// </info>
// </register>
// <register name="BRIDGE_UDP" offset="0x001C">
// <info>
// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_ENABLE" offset="0x0020">
// <info>
// Bit 0 Controls the following logic
//
//```verilog
// always_comb begin : bridge_mux
// my_mac = bridge_en ? bridge_mac_reg : mac_reg;
// my_ip = bridge_en ? bridge_ip_reg : ip_reg;
// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
// end
//```
//
// </info>
// </register>
// <register name="CHDR_DROPPED" offset="0x0030">
// <info>
// Count the number of Packets dropped that were addressed to the CHDR section.
// </info>
// </register>
// <register name="CPU_DROPPED" offset="0x0034">
// <info>
// Count the number of Packets dropped that were addressed to us, but not to the CHDR section.
// </info>
// </register>
// <register name="PAUSE" offset="0x0038">
// <bitfield name="pause_set" range="15..0">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// <bitfield name="pause_clear" range="31..16">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
// *Pause clear must be less than pause set or terrible things will happen.*
// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// </register>
// </group>
//</regmap>
//<regmap name="QSFP_REGMAP" markdown="true" generateverilog="false">
// <group name="QSFP_WINDOWS">
// <info>
// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations
//
// - 1X10GB Ethernet - Using OpenCore XGE MAC
// - 1x100GB Ethernet - Using Xilinx CMAC
// - (future possible) - Xilinx Aurora (various rates and lane widths)
// - (future possible) - 4X10GB Ethernet
//
// </info>
// <window name="ETH_DMA" offset="0x000" size="0x4000" targetregmap="DMA_REGMAP"/>
// <window name="NIXGE" offset="0x8000" size="0x2000" targetregmap="NIXGE_REGMAP"/>
// <window name="UIO" offset="0xA000" size="0x2000" targetregmap="UIO_REGMAP"/>
// <window name="CMAC" offset="0xC000" size="0x2000" targetregmap="CMAC_REGMAP"/>
// </group>
//</regmap>
//<regmap name="AXI_HPM0_REGMAP" markdown="true" generateverilog="false">
// <group name="UHD_ONLY">
// <info>
// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
// - 0_1 indicates QSFP0 - Lane1
// - 0_2 indicates QSFP0 - Lane2
// - 0_3 indicates QSFP0 - Lane3
// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
// - 1_1 indicates QSFP1 - Lane1
// - 1_2 indicates QSFP1 - Lane2
// - 1_3 indicates QSFP1 - Lane3
// </info>
// <window name="QSFP_0_0" offset="0x1200000000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_1" offset="0x1200010000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_2" offset="0x1200020000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_3" offset="0x1200030000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_0" offset="0x1200040000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_1" offset="0x1200050000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_2" offset="0x1200060000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_3" offset="0x1200070000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
+52
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
capture_sysref.v \
rf_nco_reset.vhd \
rf_reset.vhd \
sync_wrapper.v \
axis_mux.vhd \
gpio_to_axis_mux.vhd \
) \
$(addprefix $(BASE_DIR)/x400/rf/x410/, \
x410_rf_reset_controller.vhd \
x410_clock_gates.vhd \
) \
$(addprefix $(BASE_DIR)/../lib/control/, \
synchronizer.v \
synchronizer_impl.v \
) \
$(addprefix $(BASE_DIR)/x400/regmap/x410/, PkgRFDC_REGS_REGMAP.vhd )
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd/x410_ps_rfdc_bd.bd \
)
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \
x410_ps_rfdc_bd.bd.out \
x410_ps_rfdc_bd/x410_ps_rfdc_bd_ooc.xdc \
x410_ps_rfdc_bd/synth/x410_ps_rfdc_bd.v \
)
EMPTY_IP_SRCS =
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
@:
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,x410_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/hdl_sources.tcl
+14
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set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd
read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap/x410_rfdc_regs.v
+224
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//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x410_rfdc_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<top name="X410_FPGA">
// <ports>
// <info>
// This section lists all common Processing System ports through
// which the register maps in this project are accessed. Each input
// port to the fabric will point to a regmap.
// </info>
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
// <info>
// This is the main AXI4-Lite master interface that the PS
// exposes to the kernel to interact with the FPGA fabric.
// There are multiple endpoints connected to this interface.
// </info>
// </port>
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
// <info>
// This is the SPI1 interface
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
// of the PS.
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
// The request format on SPI is defined as.{br}
// {b}Write request:{/b}
// {ul}
// {li}1'b1 = write
// {li}15 bit address
// {li}32 bit data (MOSI)
// {li}8 bit processing gap
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// {b}Read request:{/b}
// {ul}
// {li}1'b0 = read
// {li}15 bit address
// {li}8 bit processing gap
// {li}32 bit data (MISO)
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// </info>
// </port>
// </ports>
// <regmapcfg readablestrobes="false">
// <map name="AXI_HPM0_REGMAP"/>
// <map name="MB_CPLD_PS_REGMAP"/>
// </regmapcfg>
//</top>
//
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <info>
// These are the registers located within the RFDC block design
// that provide control and status support for the RF chain.
// </info>
//
// <window name="MMCM" offset="0x0" size="0x10000">
// <info>
// Register space for controlling the data clock MMCM instance
// within the RFDC block design.
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
// regiter space description in chapter 2.
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
// </info>
// </window>
//
// <register name="INVERT_DB0_IQ_REG" offset="0x10000" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
// </register>
//
// <register name="INVERT_DB1_IQ_REG" offset="0x10800" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB1_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB1_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB1_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB1_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB1_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB1_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB1_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB1_DAC3_IQ" range="11"/>
// </register>
//
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
// <info>Control register for resetting the data clock MMCM.</info>
// <bitfield name="RESET_MMCM" range="0">
// <info>
// Write a '1' to this bit to reset the MMCM. Then write a
// '0' to place the MMCM out of reset.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_RESET_CONTROL_REG" offset="0x12000" typename="RF_RESET_CONTROL_REGTYPE"/>
// <register name="RF_RESET_STATUS_REG" offset="0x12008" typename="RF_RESET_STATUS_REGTYPE"/>
//
// <register name="RF_AXI_STATUS_REG" offset="0x13000" typename="RF_AXI_STATUS_REGTYPE"/>
//
// <register name="CALIBRATION_DATA" offset="0x014000">
// <info>
// The fields of this register provide data to all the DAC channels when enabled
// by the CALIBRATION_ENABLE register.
// </info>
// <bitfield name="Q_DATA" range="31..16">
// </bitfield>
// <bitfield name="I_DATA" range="15..00">
// </bitfield>
// </register>
//
// <register name="CALIBRATION_ENABLE" offset="0x014008">
// <info>
// This register enables calibration data in the DAC data path for each of the
// four channels. Each of these bits is normally '0'. When written '1', DAC data
// for the corresponding channel will be constantly driven with the contents of
// the CALIBRATION_DATA register.
// </info>
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
// <info>
// Enables calibration data for channel 0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
// <info>
// Enables calibration data for channel 1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="4">
// <info>
// Enables calibration data for channel 2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="5">
// <info>
// Enables calibration data for channel 3.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
// <info>
// Enable RF MMCM outputs.
// </info>
// <bitfield name="ENABLE_DATA_CLK" range="0"/>
// <bitfield name="ENABLE_DATA_CLK_2X" range="4"/>
// <bitfield name="ENABLE_RF_CLK" range="8"/>
// <bitfield name="ENABLE_RF_CLK_2X" range="12"/>
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
// </register>
//
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
// <info>
// Data Clk Pll Status Register
// </info>
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
// </register>
//
// <register name="THRESHOLD_STATUS" offset="0x015000">
// <info>
// This register shows threshold status for the ADCs. Each bit reflects the
// RFDC's real-time ADC status signals, which will assert when the ADC input
// signal exceeds the programmed threshold value. The status will remain
// asserted until cleared by software.
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
// the location of the tile in the converter column and ZZ is either 01 (the
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
// See also the Xilinx document PG269.
// </info>
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
// </bitfield>
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
// </bitfield>
// </register>
//
// <register name="FABRIC_DSP_REG" offset="0x13008" typename="FABRIC_DSP_REGTYPE"/>
// <register name="ADC_TILEMAP_REG" offset="0x17000" typename="ADC_TILEMAP_REGTYPE"/>
// <register name="DAC_TILEMAP_REG" offset="0x17008" typename="DAC_TILEMAP_REGTYPE"/>
// <register name="RFDC_INFO_REG" offset="0x18000" typename="RFDC_INFO_REGTYPE"/>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/synthstub/x410_ps_rfdc_bd.vhd
+411
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------------------------------------------------------------------------------------------
--
-- File: x410_ps_rfdc_bd.vhd
-- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools
-- Date: 27 September 2021
--
------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation
-- All Rights Reserved
-- National Instruments Internal Information
------------------------------------------------------------------------------------------
--
-- Purpose: This is an automatically generated stub file to match the entity
-- declaration for 'x410_ps_rfdc_bd'. This file was created using niBdExportStub
-- Do not modify this file directly!
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity x410_ps_rfdc_bd is
port (
adc_data_out_resetn_dclk : out STD_LOGIC;
adc_enable_data_rclk : out STD_LOGIC;
adc_reset_pulse_dclk : in STD_LOGIC;
adc_rfdc_axi_resetn_rclk : out STD_LOGIC;
bus_clk : in STD_LOGIC;
bus_rstn : in STD_LOGIC;
clk40 : in STD_LOGIC;
clk40_rstn : in STD_LOGIC;
dac_data_in_resetn_dclk : out STD_LOGIC;
dac_data_in_resetn_dclk2x : out STD_LOGIC;
dac_data_in_resetn_rclk : out STD_LOGIC;
dac_data_in_resetn_rclk2x : out STD_LOGIC;
dac_reset_pulse_dclk : in STD_LOGIC;
data_clk : out STD_LOGIC;
data_clk_2x : out STD_LOGIC;
data_clock_locked : out STD_LOGIC;
enable_gated_clocks_clk40 : in STD_LOGIC;
enable_sysref_rclk : in STD_LOGIC;
fir_resetn_rclk2x : out STD_LOGIC;
gated_base_clks_valid_clk40 : out STD_LOGIC;
invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
irq0_lpd_rpu_n : in STD_LOGIC;
irq1_lpd_rpu_n : in STD_LOGIC;
jtag0_tck : inout STD_LOGIC;
jtag0_tdi : inout STD_LOGIC;
jtag0_tdo : in STD_LOGIC;
jtag0_tms : inout STD_LOGIC;
nco_reset_done_dclk : out STD_LOGIC;
pl_clk40 : out STD_LOGIC;
pl_clk100 : out STD_LOGIC;
pl_clk166 : out STD_LOGIC;
pl_clk200 : out STD_LOGIC;
pl_ps_irq0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
pl_ps_irq1 : in STD_LOGIC_VECTOR ( 5 downto 0 );
pl_resetn0 : out STD_LOGIC;
pl_resetn1 : out STD_LOGIC;
pl_resetn2 : out STD_LOGIC;
pl_resetn3 : out STD_LOGIC;
pll_ref_clk_in : in STD_LOGIC;
pll_ref_clk_out : out STD_LOGIC;
rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_irq : out STD_LOGIC;
s_axi_hp0_aclk : in STD_LOGIC;
s_axi_hp1_aclk : in STD_LOGIC;
s_axi_hpc0_aclk : in STD_LOGIC;
start_nco_reset_dclk : in STD_LOGIC;
sysref_out_pclk : out STD_LOGIC;
sysref_out_rclk : out STD_LOGIC;
sysref_pl_in : in STD_LOGIC;
s_axi_hp0_aruser : in STD_LOGIC;
s_axi_hp0_awuser : in STD_LOGIC;
s_axi_hp0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_awlock : in STD_LOGIC;
s_axi_hp0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_awvalid : in STD_LOGIC;
s_axi_hp0_awready : out STD_LOGIC;
s_axi_hp0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hp0_wlast : in STD_LOGIC;
s_axi_hp0_wvalid : in STD_LOGIC;
s_axi_hp0_wready : out STD_LOGIC;
s_axi_hp0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_bvalid : out STD_LOGIC;
s_axi_hp0_bready : in STD_LOGIC;
s_axi_hp0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_arlock : in STD_LOGIC;
s_axi_hp0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp0_arvalid : in STD_LOGIC;
s_axi_hp0_arready : out STD_LOGIC;
s_axi_hp0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp0_rlast : out STD_LOGIC;
s_axi_hp0_rvalid : out STD_LOGIC;
s_axi_hp0_rready : in STD_LOGIC;
s_axi_hp0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_eth_dma_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_eth_dma_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_eth_dma_tlast : in STD_LOGIC;
s_axis_eth_dma_tready : out STD_LOGIC;
s_axis_eth_dma_tvalid : in STD_LOGIC;
s_axi_hp1_aruser : in STD_LOGIC;
s_axi_hp1_awuser : in STD_LOGIC;
s_axi_hp1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_awlock : in STD_LOGIC;
s_axi_hp1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_awvalid : in STD_LOGIC;
s_axi_hp1_awready : out STD_LOGIC;
s_axi_hp1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hp1_wlast : in STD_LOGIC;
s_axi_hp1_wvalid : in STD_LOGIC;
s_axi_hp1_wready : out STD_LOGIC;
s_axi_hp1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_bvalid : out STD_LOGIC;
s_axi_hp1_bready : in STD_LOGIC;
s_axi_hp1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hp1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hp1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_arlock : in STD_LOGIC;
s_axi_hp1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hp1_arvalid : in STD_LOGIC;
s_axi_hp1_arready : out STD_LOGIC;
s_axi_hp1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hp1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hp1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hp1_rlast : out STD_LOGIC;
s_axi_hp1_rvalid : out STD_LOGIC;
s_axi_hp1_rready : in STD_LOGIC;
s_axi_hp1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hp1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_aruser : in STD_LOGIC;
s_axi_hpc0_awuser : in STD_LOGIC;
s_axi_hpc0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_awlock : in STD_LOGIC;
s_axi_hpc0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_awvalid : in STD_LOGIC;
s_axi_hpc0_awready : out STD_LOGIC;
s_axi_hpc0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hpc0_wlast : in STD_LOGIC;
s_axi_hpc0_wvalid : in STD_LOGIC;
s_axi_hpc0_wready : out STD_LOGIC;
s_axi_hpc0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_bvalid : out STD_LOGIC;
s_axi_hpc0_bready : in STD_LOGIC;
s_axi_hpc0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_arlock : in STD_LOGIC;
s_axi_hpc0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc0_arvalid : in STD_LOGIC;
s_axi_hpc0_arready : out STD_LOGIC;
s_axi_hpc0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc0_rlast : out STD_LOGIC;
s_axi_hpc0_rvalid : out STD_LOGIC;
s_axi_hpc0_rready : in STD_LOGIC;
s_axi_hpc0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
adc0_clk_clk_n : in STD_LOGIC;
adc0_clk_clk_p : in STD_LOGIC;
adc2_clk_clk_n : in STD_LOGIC;
adc2_clk_clk_p : in STD_LOGIC;
m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_app_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_app_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_app_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_app_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_app_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_app_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_app_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_app_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
dac0_clk_clk_n : in STD_LOGIC;
dac0_clk_clk_p : in STD_LOGIC;
dac1_clk_clk_n : in STD_LOGIC;
dac1_clk_clk_p : in STD_LOGIC;
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_eth_internal_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_eth_internal_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_eth_internal_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_eth_internal_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_eth_internal_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_eth_internal_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_eth_internal_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_eth_internal_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_eth_dma_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_eth_dma_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_eth_dma_tlast : out STD_LOGIC;
m_axis_eth_dma_tready : in STD_LOGIC;
m_axis_eth_dma_tvalid : out STD_LOGIC;
m_axi_rpu_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_rpu_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rpu_awvalid : out STD_LOGIC;
m_axi_rpu_awready : in STD_LOGIC;
m_axi_rpu_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rpu_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rpu_wvalid : out STD_LOGIC;
m_axi_rpu_wready : in STD_LOGIC;
m_axi_rpu_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rpu_bvalid : in STD_LOGIC;
m_axi_rpu_bready : out STD_LOGIC;
m_axi_rpu_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_rpu_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rpu_arvalid : out STD_LOGIC;
m_axi_rpu_arready : in STD_LOGIC;
m_axi_rpu_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rpu_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rpu_rvalid : in STD_LOGIC;
m_axi_rpu_rready : out STD_LOGIC;
m_axi_core_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_core_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_core_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_core_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_core_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_core_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_core_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_core_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_core_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_core_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_core_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_mpm_ep_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mpm_ep_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mpm_ep_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mpm_ep_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mpm_ep_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_mpm_ep_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mpm_ep_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch0_dout_i_tready : in STD_LOGIC;
adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile224_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch0_dout_q_tready : in STD_LOGIC;
adc_tile224_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile224_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch1_dout_i_tready : in STD_LOGIC;
adc_tile224_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch1_dout_q_tready : in STD_LOGIC;
adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC;
adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch0_dout_i_tready : in STD_LOGIC;
adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile226_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch0_dout_q_tready : in STD_LOGIC;
adc_tile226_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile226_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch1_dout_i_tready : in STD_LOGIC;
adc_tile226_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch1_dout_q_tready : in STD_LOGIC;
adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC;
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch0_din_tvalid : in STD_LOGIC;
dac_tile228_ch0_din_tready : out STD_LOGIC;
dac_tile228_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch1_din_tvalid : in STD_LOGIC;
dac_tile228_ch1_din_tready : out STD_LOGIC;
dac_tile229_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch0_din_tvalid : in STD_LOGIC;
dac_tile229_ch0_din_tready : out STD_LOGIC;
dac_tile229_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch1_din_tvalid : in STD_LOGIC;
dac_tile229_ch1_din_tready : out STD_LOGIC;
s_axi_hpc1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_hpc1_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 );
s_axi_hpc1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_hpc1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_hpc1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_hpc1_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_hpc1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_hpc1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_hpc1_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sysref_rf_in_diff_n : in STD_LOGIC;
sysref_rf_in_diff_p : in STD_LOGIC;
adc_tile224_ch0_vin_v_n : in STD_LOGIC;
adc_tile224_ch0_vin_v_p : in STD_LOGIC;
adc_tile224_ch1_vin_v_n : in STD_LOGIC;
adc_tile224_ch1_vin_v_p : in STD_LOGIC;
adc_tile226_ch0_vin_v_n : in STD_LOGIC;
adc_tile226_ch0_vin_v_p : in STD_LOGIC;
adc_tile226_ch1_vin_v_n : in STD_LOGIC;
adc_tile226_ch1_vin_v_p : in STD_LOGIC;
s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end entity x410_ps_rfdc_bd;
architecture stub of x410_ps_rfdc_bd is
begin
end architecture stub;
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl
+3825
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File diff suppressed because it is too large Load Diff
top/x400/ip/xge_pcs_pma/Makefile.inc
+1 -1
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@@ -38,4 +38,4 @@ $(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS): IP_XGE_PCS_PMA_TRGT
@:
IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci
$(call BUILD_VIVADO_IP,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
$(call BUILD_VIVADO_IP_WITH_SUBCORES,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
top/x400/ipass_present_controller.v
+1 -1
View File
@@ -40,7 +40,7 @@ module ipass_present_controller (
);
`include "regmap/pl_cpld_regmap_utils.vh"
`include "cpld/regmap/mb_cpld_pl_regmap_utils.vh"
`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
`include "../../lib/rfnoc/core/ctrlport.vh"
top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd
-663
View File
@@ -1,663 +0,0 @@
---------------------------------------------------------------------
--
-- Copyright 2022 Ettus Research, A National Instruments Brand
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: PkgRFDC_REGS_REGMAP.vhd
--
-- Purpose:
-- The constants in this file are autogenerated by XmlParse.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgRFDC_REGS_REGMAP is
--===============================================================================
-- A numerically ordered list of registers and their HDL source files
--===============================================================================
-- MMCM : 0x0 (common_regs.v)
-- INVERT_IQ_REG : 0x10000 (common_regs.v)
-- MMCM_RESET_REG : 0x11000 (common_regs.v)
-- RF_RESET_CONTROL_REG : 0x12000 (common_regs.v)
-- RF_RESET_STATUS_REG : 0x12008 (common_regs.v)
-- RF_AXI_STATUS_REG : 0x13000 (common_regs.v)
-- FABRIC_DSP_REG : 0x13008 (common_regs.v)
-- CALIBRATION_DATA : 0x14000 (common_regs.v)
-- CALIBRATION_ENABLE : 0x14008 (common_regs.v)
-- THRESHOLD_STATUS : 0x15000 (common_regs.v)
-- RF_PLL_CONTROL_REG : 0x16000 (common_regs.v)
-- RF_PLL_STATUS_REG : 0x16008 (common_regs.v)
--===============================================================================
-- RegTypes
--===============================================================================
--===============================================================================
-- Register Group RFDC_REGS
--===============================================================================
-- Enumerated type FABRIC_DSP_BW_ENUM
constant kFABRIC_DSP_BW_ENUMSize : integer := 4;
constant kFABRIC_DSP_BW_NONE : integer := 0; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE
constant kFABRIC_DSP_BW_100M : integer := 100; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M
constant kFABRIC_DSP_BW_200M : integer := 200; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M
constant kFABRIC_DSP_BW_400M : integer := 400; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M
-- MMCM Window (from common_regs.v)
constant kMMCM : integer := 16#0#; -- Window Offset
constant kMMCMSize: integer := 16#10000#; -- size in bytes
--function kMMCMRec return XReg2_t; -- Window Record function commented out due to programmable attributes
-- INVERT_IQ_REG Register (from common_regs.v)
constant kINVERT_IQ_REG : integer := 16#10000#; -- Register Offset
constant kINVERT_IQ_REGSize: integer := 32; -- register width in bits
constant kINVERT_IQ_REGMask : std_logic_vector(31 downto 0) := X"0000ffff";
constant kINVERT_DB0_ADC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
constant kINVERT_DB0_ADC0_IQMsb : integer := 0; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
constant kINVERT_DB0_ADC0_IQ : integer := 0; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
constant kINVERT_DB0_ADC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
constant kINVERT_DB0_ADC1_IQMsb : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
constant kINVERT_DB0_ADC1_IQ : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
constant kINVERT_DB0_ADC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
constant kINVERT_DB0_ADC2_IQMsb : integer := 2; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
constant kINVERT_DB0_ADC2_IQ : integer := 2; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
constant kINVERT_DB0_ADC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
constant kINVERT_DB0_ADC3_IQMsb : integer := 3; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
constant kINVERT_DB0_ADC3_IQ : integer := 3; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
constant kINVERT_DB1_ADC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
constant kINVERT_DB1_ADC0_IQMsb : integer := 4; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
constant kINVERT_DB1_ADC0_IQ : integer := 4; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
constant kINVERT_DB1_ADC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
constant kINVERT_DB1_ADC1_IQMsb : integer := 5; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
constant kINVERT_DB1_ADC1_IQ : integer := 5; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
constant kINVERT_DB1_ADC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
constant kINVERT_DB1_ADC2_IQMsb : integer := 6; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
constant kINVERT_DB1_ADC2_IQ : integer := 6; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
constant kINVERT_DB1_ADC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
constant kINVERT_DB1_ADC3_IQMsb : integer := 7; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
constant kINVERT_DB1_ADC3_IQ : integer := 7; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
constant kINVERT_DB0_DAC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
constant kINVERT_DB0_DAC0_IQMsb : integer := 8; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
constant kINVERT_DB0_DAC0_IQ : integer := 8; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
constant kINVERT_DB0_DAC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
constant kINVERT_DB0_DAC1_IQMsb : integer := 9; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
constant kINVERT_DB0_DAC1_IQ : integer := 9; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
constant kINVERT_DB0_DAC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
constant kINVERT_DB0_DAC2_IQMsb : integer := 10; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
constant kINVERT_DB0_DAC2_IQ : integer := 10; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
constant kINVERT_DB0_DAC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
constant kINVERT_DB0_DAC3_IQMsb : integer := 11; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
constant kINVERT_DB0_DAC3_IQ : integer := 11; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
constant kINVERT_DB1_DAC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
constant kINVERT_DB1_DAC0_IQMsb : integer := 12; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
constant kINVERT_DB1_DAC0_IQ : integer := 12; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
constant kINVERT_DB1_DAC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
constant kINVERT_DB1_DAC1_IQMsb : integer := 13; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
constant kINVERT_DB1_DAC1_IQ : integer := 13; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
constant kINVERT_DB1_DAC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
constant kINVERT_DB1_DAC2_IQMsb : integer := 14; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
constant kINVERT_DB1_DAC2_IQ : integer := 14; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
constant kINVERT_DB1_DAC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
constant kINVERT_DB1_DAC3_IQMsb : integer := 15; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
constant kINVERT_DB1_DAC3_IQ : integer := 15; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
--function kINVERT_IQ_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- MMCM_RESET_REG Register (from common_regs.v)
constant kMMCM_RESET_REG : integer := 16#11000#; -- Register Offset
constant kMMCM_RESET_REGSize: integer := 32; -- register width in bits
constant kMMCM_RESET_REGMask : std_logic_vector(31 downto 0) := X"00000001";
constant kRESET_MMCMSize : integer := 1; --MMCM_RESET_REG:RESET_MMCM
constant kRESET_MMCMMsb : integer := 0; --MMCM_RESET_REG:RESET_MMCM
constant kRESET_MMCM : integer := 0; --MMCM_RESET_REG:RESET_MMCM
--function kMMCM_RESET_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_RESET_CONTROL_REG Register (from common_regs.v)
constant kRF_RESET_CONTROL_REG : integer := 16#12000#; -- Register Offset
constant kRF_RESET_CONTROL_REGSize: integer := 32; -- register width in bits
constant kRF_RESET_CONTROL_REGMask : std_logic_vector(31 downto 0) := X"00000331";
constant kFSM_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:FSM_RESET
constant kFSM_RESETMsb : integer := 0; --RF_RESET_CONTROL_REG:FSM_RESET
constant kFSM_RESET : integer := 0; --RF_RESET_CONTROL_REG:FSM_RESET
constant kADC_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:ADC_RESET
constant kADC_RESETMsb : integer := 4; --RF_RESET_CONTROL_REG:ADC_RESET
constant kADC_RESET : integer := 4; --RF_RESET_CONTROL_REG:ADC_RESET
constant kADC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REG:ADC_ENABLE
constant kADC_ENABLEMsb : integer := 5; --RF_RESET_CONTROL_REG:ADC_ENABLE
constant kADC_ENABLE : integer := 5; --RF_RESET_CONTROL_REG:ADC_ENABLE
constant kDAC_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:DAC_RESET
constant kDAC_RESETMsb : integer := 8; --RF_RESET_CONTROL_REG:DAC_RESET
constant kDAC_RESET : integer := 8; --RF_RESET_CONTROL_REG:DAC_RESET
constant kDAC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REG:DAC_ENABLE
constant kDAC_ENABLEMsb : integer := 9; --RF_RESET_CONTROL_REG:DAC_ENABLE
constant kDAC_ENABLE : integer := 9; --RF_RESET_CONTROL_REG:DAC_ENABLE
--function kRF_RESET_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_RESET_STATUS_REG Register (from common_regs.v)
constant kRF_RESET_STATUS_REG : integer := 16#12008#; -- Register Offset
constant kRF_RESET_STATUS_REGSize: integer := 32; -- register width in bits
constant kRF_RESET_STATUS_REGMask : std_logic_vector(31 downto 0) := X"00000888";
constant kFSM_RESET_DONESize : integer := 1; --RF_RESET_STATUS_REG:FSM_RESET_DONE
constant kFSM_RESET_DONEMsb : integer := 3; --RF_RESET_STATUS_REG:FSM_RESET_DONE
constant kFSM_RESET_DONE : integer := 3; --RF_RESET_STATUS_REG:FSM_RESET_DONE
constant kADC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REG:ADC_SEQ_DONE
constant kADC_SEQ_DONEMsb : integer := 7; --RF_RESET_STATUS_REG:ADC_SEQ_DONE
constant kADC_SEQ_DONE : integer := 7; --RF_RESET_STATUS_REG:ADC_SEQ_DONE
constant kDAC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REG:DAC_SEQ_DONE
constant kDAC_SEQ_DONEMsb : integer := 11; --RF_RESET_STATUS_REG:DAC_SEQ_DONE
constant kDAC_SEQ_DONE : integer := 11; --RF_RESET_STATUS_REG:DAC_SEQ_DONE
--function kRF_RESET_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_AXI_STATUS_REG Register (from common_regs.v)
constant kRF_AXI_STATUS_REG : integer := 16#13000#; -- Register Offset
constant kRF_AXI_STATUS_REGSize: integer := 32; -- register width in bits
constant kRF_AXI_STATUS_REGMask : std_logic_vector(31 downto 0) := X"ffffffff";
constant kRFDC_DAC_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY
constant kRFDC_DAC_TREADYMsb : integer := 1; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY
constant kRFDC_DAC_TREADY : integer := 0; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY
constant kRFDC_DAC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID
constant kRFDC_DAC_TVALIDMsb : integer := 3; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID
constant kRFDC_DAC_TVALID : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID
constant kRFDC_ADC_Q_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
constant kRFDC_ADC_Q_TREADYMsb : integer := 5; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
constant kRFDC_ADC_Q_TREADY : integer := 4; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
constant kRFDC_ADC_I_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
constant kRFDC_ADC_I_TREADYMsb : integer := 7; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
constant kRFDC_ADC_I_TREADY : integer := 6; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
constant kRFDC_ADC_Q_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
constant kRFDC_ADC_Q_TVALIDMsb : integer := 9; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
constant kRFDC_ADC_Q_TVALID : integer := 8; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
constant kRFDC_ADC_I_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
constant kRFDC_ADC_I_TVALIDMsb : integer := 11; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
constant kRFDC_ADC_I_TVALID : integer := 10; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
constant kUSER_ADC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TVALID
constant kUSER_ADC_TVALIDMsb : integer := 13; --RF_AXI_STATUS_REG:USER_ADC_TVALID
constant kUSER_ADC_TVALID : integer := 12; --RF_AXI_STATUS_REG:USER_ADC_TVALID
constant kUSER_ADC_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TREADY
constant kUSER_ADC_TREADYMsb : integer := 15; --RF_AXI_STATUS_REG:USER_ADC_TREADY
constant kUSER_ADC_TREADY : integer := 14; --RF_AXI_STATUS_REG:USER_ADC_TREADY
constant kRFDC_DAC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
constant kRFDC_DAC_TREADY_DB1Msb : integer := 17; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
constant kRFDC_DAC_TREADY_DB1 : integer := 16; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
constant kRFDC_DAC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
constant kRFDC_DAC_TVALID_DB1Msb : integer := 19; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
constant kRFDC_DAC_TVALID_DB1 : integer := 18; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
constant kRFDC_ADC_Q_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
constant kRFDC_ADC_Q_TREADY_DB1Msb : integer := 21; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
constant kRFDC_ADC_Q_TREADY_DB1 : integer := 20; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
constant kRFDC_ADC_I_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
constant kRFDC_ADC_I_TREADY_DB1Msb : integer := 23; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
constant kRFDC_ADC_I_TREADY_DB1 : integer := 22; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
constant kRFDC_ADC_Q_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
constant kRFDC_ADC_Q_TVALID_DB1Msb : integer := 25; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
constant kRFDC_ADC_Q_TVALID_DB1 : integer := 24; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
constant kRFDC_ADC_I_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
constant kRFDC_ADC_I_TVALID_DB1Msb : integer := 27; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
constant kRFDC_ADC_I_TVALID_DB1 : integer := 26; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
constant kUSER_ADC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
constant kUSER_ADC_TVALID_DB1Msb : integer := 29; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
constant kUSER_ADC_TVALID_DB1 : integer := 28; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
constant kUSER_ADC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
constant kUSER_ADC_TREADY_DB1Msb : integer := 31; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
constant kUSER_ADC_TREADY_DB1 : integer := 30; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
--function kRF_AXI_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- FABRIC_DSP_REG Register (from common_regs.v)
constant kFABRIC_DSP_REG : integer := 16#13008#; -- Register Offset
constant kFABRIC_DSP_REGSize: integer := 32; -- register width in bits
constant kFABRIC_DSP_REGMask : std_logic_vector(31 downto 0) := X"ffffffff";
constant kFABRIC_DSP_BWSize : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_BW
constant kFABRIC_DSP_BWMsb : integer := 11; --FABRIC_DSP_REG:FABRIC_DSP_BW
constant kFABRIC_DSP_BW : integer := 0; --FABRIC_DSP_REG:FABRIC_DSP_BW
constant kFABRIC_DSP_RX_CNTSize : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
constant kFABRIC_DSP_RX_CNTMsb : integer := 13; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
constant kFABRIC_DSP_RX_CNT : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
constant kFABRIC_DSP_TX_CNTSize : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
constant kFABRIC_DSP_TX_CNTMsb : integer := 15; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
constant kFABRIC_DSP_TX_CNT : integer := 14; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
constant kFABRIC_DSP_BW_DB1Size : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
constant kFABRIC_DSP_BW_DB1Msb : integer := 27; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
constant kFABRIC_DSP_BW_DB1 : integer := 16; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
constant kFABRIC_DSP_RX_CNT_DB1Size : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
constant kFABRIC_DSP_RX_CNT_DB1Msb : integer := 29; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
constant kFABRIC_DSP_RX_CNT_DB1 : integer := 28; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
constant kFABRIC_DSP_TX_CNT_DB1Size : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
constant kFABRIC_DSP_TX_CNT_DB1Msb : integer := 31; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
constant kFABRIC_DSP_TX_CNT_DB1 : integer := 30; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
--function kFABRIC_DSP_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- CALIBRATION_DATA Register (from common_regs.v)
constant kCALIBRATION_DATA : integer := 16#14000#; -- Register Offset
constant kCALIBRATION_DATASize: integer := 32; -- register width in bits
constant kCALIBRATION_DATAMask : std_logic_vector(31 downto 0) := X"ffffffff";
constant kI_DATASize : integer := 16; --CALIBRATION_DATA:I_DATA
constant kI_DATAMsb : integer := 15; --CALIBRATION_DATA:I_DATA
constant kI_DATA : integer := 0; --CALIBRATION_DATA:I_DATA
constant kQ_DATASize : integer := 16; --CALIBRATION_DATA:Q_DATA
constant kQ_DATAMsb : integer := 31; --CALIBRATION_DATA:Q_DATA
constant kQ_DATA : integer := 16; --CALIBRATION_DATA:Q_DATA
--function kCALIBRATION_DATARec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- CALIBRATION_ENABLE Register (from common_regs.v)
constant kCALIBRATION_ENABLE : integer := 16#14008#; -- Register Offset
constant kCALIBRATION_ENABLESize: integer := 32; -- register width in bits
constant kCALIBRATION_ENABLEMask : std_logic_vector(31 downto 0) := X"00000033";
constant kENABLE_CALIBRATION_DATA_0Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
constant kENABLE_CALIBRATION_DATA_0Msb : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
constant kENABLE_CALIBRATION_DATA_0 : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
constant kENABLE_CALIBRATION_DATA_1Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
constant kENABLE_CALIBRATION_DATA_1Msb : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
constant kENABLE_CALIBRATION_DATA_1 : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
constant kENABLE_CALIBRATION_DATA_2Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
constant kENABLE_CALIBRATION_DATA_2Msb : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
constant kENABLE_CALIBRATION_DATA_2 : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
constant kENABLE_CALIBRATION_DATA_3Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
constant kENABLE_CALIBRATION_DATA_3Msb : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
constant kENABLE_CALIBRATION_DATA_3 : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
--function kCALIBRATION_ENABLERec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- THRESHOLD_STATUS Register (from common_regs.v)
constant kTHRESHOLD_STATUS : integer := 16#15000#; -- Register Offset
constant kTHRESHOLD_STATUSSize: integer := 32; -- register width in bits
constant kTHRESHOLD_STATUSMask : std_logic_vector(31 downto 0) := X"00000f0f";
constant kADC0_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1
constant kADC0_01_THRESHOLD1Msb : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1
constant kADC0_01_THRESHOLD1 : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1
constant kADC0_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2
constant kADC0_01_THRESHOLD2Msb : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2
constant kADC0_01_THRESHOLD2 : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2
constant kADC0_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1
constant kADC0_23_THRESHOLD1Msb : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1
constant kADC0_23_THRESHOLD1 : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1
constant kADC0_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2
constant kADC0_23_THRESHOLD2Msb : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2
constant kADC0_23_THRESHOLD2 : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2
constant kADC2_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1
constant kADC2_01_THRESHOLD1Msb : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1
constant kADC2_01_THRESHOLD1 : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1
constant kADC2_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2
constant kADC2_01_THRESHOLD2Msb : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2
constant kADC2_01_THRESHOLD2 : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2
constant kADC2_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1
constant kADC2_23_THRESHOLD1Msb : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1
constant kADC2_23_THRESHOLD1 : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1
constant kADC2_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2
constant kADC2_23_THRESHOLD2Msb : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2
constant kADC2_23_THRESHOLD2 : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2
--function kTHRESHOLD_STATUSRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_PLL_CONTROL_REG Register (from common_regs.v)
constant kRF_PLL_CONTROL_REG : integer := 16#16000#; -- Register Offset
constant kRF_PLL_CONTROL_REGSize: integer := 32; -- register width in bits
constant kRF_PLL_CONTROL_REGMask : std_logic_vector(31 downto 0) := X"00011111";
constant kENABLE_DATA_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
constant kENABLE_DATA_CLKMsb : integer := 0; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
constant kENABLE_DATA_CLK : integer := 0; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
constant kENABLE_DATA_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
constant kENABLE_DATA_CLK_2XMsb : integer := 4; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
constant kENABLE_DATA_CLK_2X : integer := 4; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
constant kENABLE_RF_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK
constant kENABLE_RF_CLKMsb : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK
constant kENABLE_RF_CLK : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK
constant kENABLE_RF_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
constant kENABLE_RF_CLK_2XMsb : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
constant kENABLE_RF_CLK_2X : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
constant kCLEAR_DATA_CLK_UNLOCKEDSize : integer := 1; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
constant kCLEAR_DATA_CLK_UNLOCKEDMsb : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
constant kCLEAR_DATA_CLK_UNLOCKED : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
--function kRF_PLL_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
-- RF_PLL_STATUS_REG Register (from common_regs.v)
constant kRF_PLL_STATUS_REG : integer := 16#16008#; -- Register Offset
constant kRF_PLL_STATUS_REGSize: integer := 32; -- register width in bits
constant kRF_PLL_STATUS_REGMask : std_logic_vector(31 downto 0) := X"00110000";
constant kDATA_CLK_PLL_UNLOCKED_STICKYSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
constant kDATA_CLK_PLL_UNLOCKED_STICKYMsb : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
constant kDATA_CLK_PLL_UNLOCKED_STICKY : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
constant kDATA_CLK_PLL_LOCKEDSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
constant kDATA_CLK_PLL_LOCKEDMsb : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
constant kDATA_CLK_PLL_LOCKED : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
--function kRF_PLL_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes
end package;
package body PkgRFDC_REGS_REGMAP is
-- function kMMCMRec not implemented because MMCM has programmable attributes
---- Return the record of window kMMCM
--function kMMCMRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"0");
-- Rec.size := kMMCMSize;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00");
-- Rec.rmask := XRegResize(X"00");
-- Rec.strobemask := XRegResize(X"00");
-- Rec.clearablemask := XRegResize(X"00");
-- Rec.iswin := true;
-- --synopsys translate_off
-- Rec.name := rs("MMCM");
-- --synopsys translate_on
-- return Rec;
--end function kMMCMRec;
-- function kINVERT_IQ_REGRec not implemented because INVERT_IQ_REG has programmable attributes
---- Return the record of register kINVERT_IQ_REG
--function kINVERT_IQ_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"10000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"0000ffff");
-- Rec.rmask := XRegResize(X"0000ffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("INVERT_IQ_REG");
-- --synopsys translate_on
-- return Rec;
--end function kINVERT_IQ_REGRec;
-- function kMMCM_RESET_REGRec not implemented because MMCM_RESET_REG has programmable attributes
---- Return the record of register kMMCM_RESET_REG
--function kMMCM_RESET_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"11000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000001");
-- Rec.rmask := XRegResize(X"00000001");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("MMCM_RESET_REG");
-- --synopsys translate_on
-- return Rec;
--end function kMMCM_RESET_REGRec;
-- function kRF_RESET_CONTROL_REGRec not implemented because RF_RESET_CONTROL_REG has programmable attributes
---- Return the record of register kRF_RESET_CONTROL_REG
--function kRF_RESET_CONTROL_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"12000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000331");
-- Rec.rmask := XRegResize(X"00000331");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_RESET_CONTROL_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_RESET_CONTROL_REGRec;
-- function kRF_RESET_STATUS_REGRec not implemented because RF_RESET_STATUS_REG has programmable attributes
---- Return the record of register kRF_RESET_STATUS_REG
--function kRF_RESET_STATUS_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"12008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"00000888");
-- Rec.rmask := XRegResize(X"00000888");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_RESET_STATUS_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_RESET_STATUS_REGRec;
-- function kRF_AXI_STATUS_REGRec not implemented because RF_AXI_STATUS_REG has programmable attributes
---- Return the record of register kRF_AXI_STATUS_REG
--function kRF_AXI_STATUS_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"13000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"ffffffff");
-- Rec.rmask := XRegResize(X"ffffffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.msblookupw(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb;
-- Rec.msblookupw(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb;
-- Rec.msblookupw(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb;
-- Rec.msblookupw(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb;
-- Rec.msblookupw(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb;
-- Rec.msblookupw(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb;
-- Rec.msblookupw(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb;
-- Rec.msblookupw(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb;
-- Rec.msblookupw(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb;
-- Rec.msblookupw(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb;
-- Rec.msblookupw(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb;
-- Rec.msblookupw(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb;
-- Rec.msblookupw(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb;
-- Rec.msblookupr(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb;
-- Rec.msblookupr(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb;
-- Rec.msblookupr(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb;
-- Rec.msblookupr(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb;
-- Rec.msblookupr(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb;
-- Rec.msblookupr(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb;
-- Rec.msblookupr(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb;
-- Rec.msblookupr(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb;
-- Rec.msblookupr(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb;
-- Rec.msblookupr(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb;
-- Rec.msblookupr(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb;
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_AXI_STATUS_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_AXI_STATUS_REGRec;
-- function kFABRIC_DSP_REGRec not implemented because FABRIC_DSP_REG has programmable attributes
---- Return the record of register kFABRIC_DSP_REG
--function kFABRIC_DSP_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"13008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"ffffffff");
-- Rec.rmask := XRegResize(X"ffffffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- Rec.initialvalue := XRegResize(X"00000000");
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.msblookupw(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb;
-- Rec.msblookupw(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb;
-- Rec.msblookupw(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb;
-- Rec.msblookupw(kFABRIC_DSP_BW_DB1) := kFABRIC_DSP_BW_DB1Msb;
-- Rec.msblookupw(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb;
-- Rec.msblookupw(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb;
-- Rec.msblookupr(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb;
-- Rec.msblookupr(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb;
-- Rec.msblookupr(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb;
-- Rec.msblookupr(kFABRIC_DSP_BW_DB1) := kFABRIC_DSP_BW_DB1Msb;
-- Rec.msblookupr(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb;
-- Rec.msblookupr(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb;
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("FABRIC_DSP_REG");
-- --synopsys translate_on
-- return Rec;
--end function kFABRIC_DSP_REGRec;
-- function kCALIBRATION_DATARec not implemented because CALIBRATION_DATA has programmable attributes
---- Return the record of register kCALIBRATION_DATA
--function kCALIBRATION_DATARec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"14000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"ffffffff");
-- Rec.rmask := XRegResize(X"ffffffff");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.msblookupw(kI_DATA) := kI_DATAMsb;
-- Rec.msblookupw(kQ_DATA) := kQ_DATAMsb;
-- Rec.msblookupr(kI_DATA) := kI_DATAMsb;
-- Rec.msblookupr(kQ_DATA) := kQ_DATAMsb;
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("CALIBRATION_DATA");
-- --synopsys translate_on
-- return Rec;
--end function kCALIBRATION_DATARec;
-- function kCALIBRATION_ENABLERec not implemented because CALIBRATION_ENABLE has programmable attributes
---- Return the record of register kCALIBRATION_ENABLE
--function kCALIBRATION_ENABLERec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"14008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000033");
-- Rec.rmask := XRegResize(X"00000033");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("CALIBRATION_ENABLE");
-- --synopsys translate_on
-- return Rec;
--end function kCALIBRATION_ENABLERec;
-- function kTHRESHOLD_STATUSRec not implemented because THRESHOLD_STATUS has programmable attributes
---- Return the record of register kTHRESHOLD_STATUS
--function kTHRESHOLD_STATUSRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"15000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00000f0f");
-- Rec.rmask := XRegResize(X"00000f0f");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("THRESHOLD_STATUS");
-- --synopsys translate_on
-- return Rec;
--end function kTHRESHOLD_STATUSRec;
-- function kRF_PLL_CONTROL_REGRec not implemented because RF_PLL_CONTROL_REG has programmable attributes
---- Return the record of register kRF_PLL_CONTROL_REG
--function kRF_PLL_CONTROL_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"16000");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := true;
-- Rec.wmask := XRegResize(X"00011111");
-- Rec.rmask := XRegResize(X"00011111");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_PLL_CONTROL_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_PLL_CONTROL_REGRec;
-- function kRF_PLL_STATUS_REGRec not implemented because RF_PLL_STATUS_REG has programmable attributes
---- Return the record of register kRF_PLL_STATUS_REG
--function kRF_PLL_STATUS_REGRec return XReg2_t is
-- variable Rec : XReg2_t;
--begin
-- Rec := kXRegDefault;
-- Rec.version := 1;
-- Rec.offset := XAddrResize(X"16008");
-- Rec.size := 32;
-- Rec.readable := true;
-- Rec.writable := false;
-- Rec.wmask := XRegResize(X"00110000");
-- Rec.rmask := XRegResize(X"00110000");
-- Rec.strobemask := XRegResize(X"00000000");
-- Rec.clearablemask := XRegResize(X"00000000");
-- -- no initial values specified
-- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb.
-- Rec.isreg := true;
-- --synopsys translate_off
-- Rec.name := rs("RF_PLL_STATUS_REG");
-- --synopsys translate_on
-- return Rec;
--end function kRF_PLL_STATUS_REGRec;
end package body;
top/x400/regmap/core_regs_regmap_utils.vh
+10 -5
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,7 +13,8 @@
// GLOBAL_REGS : 0x0 (x4xx_core_common.v)
// VERSIONING_REGS : 0xC00 (x4xx_core_common.v)
// TIMEKEEPER : 0x1000 (x4xx_core_common.v)
// TIMEKEEPER_A : 0x1000 (x4xx_core_common.v)
// TIMEKEEPER_B : 0x1100 (x4xx_core_common.v)
// DIO : 0x2000 (x4xx_core_common.v)
//===============================================================================
@@ -32,9 +33,13 @@
localparam VERSIONING_REGS = 'hC00; // Window Offset
localparam VERSIONING_REGS_SIZE = 'h400; // size in byte
// TIMEKEEPER Window (from x4xx_core_common.v)
localparam TIMEKEEPER = 'h1000; // Window Offset
localparam TIMEKEEPER_SIZE = 'h20; // size in bytes
// TIMEKEEPER_A Window (from x4xx_core_common.v)
localparam TIMEKEEPER_A = 'h1000; // Window Offset
localparam TIMEKEEPER_A_SIZE = 'h20; // size in bytes
// TIMEKEEPER_B Window (from x4xx_core_common.v)
localparam TIMEKEEPER_B = 'h1100; // Window Offset
localparam TIMEKEEPER_B_SIZE = 'h20; // size in bytes
// DIO Window (from x4xx_core_common.v)
localparam DIO = 'h2000; // Window Offset
top/x400/regmap/cpld_interface_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/dig_ifc_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/dio_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/global_regs_regmap_utils.vh
+7 -6
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@@ -156,13 +156,16 @@
// PPS_CTRL_REG Register (from x4xx_global_regs.v)
localparam PPS_CTRL_REG = 'h1C; // Register Offset
localparam PPS_CTRL_REG_SIZE = 32; // register width in bits
localparam PPS_CTRL_REG_MASK = 32'hB3FFFFFF;
localparam PPS_CTRL_REG_MASK = 32'hBFFFFFFF;
localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY
localparam PRC_RC_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC_DIVIDER
localparam PRC_RC_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC_DIVIDER
localparam PRC_RC_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC_DIVIDER
localparam PRC_RC1_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER_MSB = 27; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC1_DIVIDER = 26; //PPS_CTRL_REG:PRC_RC1_DIVIDER
localparam PRC_RC0_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PRC_RC0_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC0_DIVIDER
localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
@@ -174,8 +177,6 @@
localparam CHDR_CLK_SIZE = 32; //CHDR_CLK_RATE_REG:CHDR_CLK
localparam CHDR_CLK_MSB = 31; //CHDR_CLK_RATE_REG:CHDR_CLK
localparam CHDR_CLK = 0; //CHDR_CLK_RATE_REG:CHDR_CLK
localparam CHDR_CLK_ENUM_SIZE = 1;
localparam CHDR_CLK_VALUE = 'hBEBC200; // enum value
// CHDR_CLK_COUNT_REG Register (from x4xx_global_regs.v)
localparam CHDR_CLK_COUNT_REG = 'h24; // Register Offset
top/x400/regmap/gpio_atr_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/pl_cpld_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/radio_ctrlport_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/radio_dio_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/rfdc_timing_regmap_utils.vh
+1 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
top/x400/regmap/x410/PkgRFDC_REGS_REGMAP.vhd
+1004
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top/x400/regmap/x410/rfdc_regs_regmap_utils.vh
+466
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@@ -0,0 +1,466 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// MMCM : 0x0 (x410_rfdc_regs.v)
// INVERT_DB0_IQ_REG : 0x10000 (x410_rfdc_regs.v)
// INVERT_DB1_IQ_REG : 0x10800 (x410_rfdc_regs.v)
// MMCM_RESET_REG : 0x11000 (x410_rfdc_regs.v)
// RF_RESET_CONTROL_REG : 0x12000 (x410_rfdc_regs.v)
// RF_RESET_STATUS_REG : 0x12008 (x410_rfdc_regs.v)
// RF_AXI_STATUS_REG : 0x13000 (x410_rfdc_regs.v)
// FABRIC_DSP_REG : 0x13008 (x410_rfdc_regs.v)
// CALIBRATION_DATA : 0x14000 (x410_rfdc_regs.v)
// CALIBRATION_ENABLE : 0x14008 (x410_rfdc_regs.v)
// THRESHOLD_STATUS : 0x15000 (x410_rfdc_regs.v)
// RF_PLL_CONTROL_REG : 0x16000 (x410_rfdc_regs.v)
// RF_PLL_STATUS_REG : 0x16008 (x410_rfdc_regs.v)
// ADC_TILEMAP_REG : 0x17000 (x410_rfdc_regs.v)
// DAC_TILEMAP_REG : 0x17008 (x410_rfdc_regs.v)
// RFDC_INFO_REG : 0x18000 (x410_rfdc_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
// ADC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam ADC_TILEMAP_REGTYPE_SIZE = 32;
localparam ADC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam ADC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE = 0; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE = 4; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK = 6; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE = 8; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK = 10; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE = 12; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK = 14; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE = 16; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK = 18; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE = 20; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK = 22; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE = 24; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK = 26; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE = 28; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK = 30; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
// DAC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam DAC_TILEMAP_REGTYPE_SIZE = 32;
localparam DAC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam DAC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE = 0; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE = 4; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK = 6; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE = 8; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK = 10; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE = 12; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK = 14; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE = 16; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK = 18; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE = 20; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK = 22; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE = 24; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK = 26; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE = 28; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK = 30; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
// FABRIC_DSP_REGTYPE Type (from common_regs.v)
localparam FABRIC_DSP_REGTYPE_SIZE = 32;
localparam FABRIC_DSP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam FABRIC_DSP_RX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT_MSB = 3; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT = 0; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_TX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT_MSB = 7; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_RESERVED_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED_MSB = 9; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED = 8; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1_MSB = 13; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1 = 10; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_MSB = 17; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1 = 14; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_RESERVED_DB1_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1_MSB = 19; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1 = 18; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW_MSB = 31; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW = 20; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
// RF_AXI_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_AXI_STATUS_REGTYPE_SIZE = 32;
localparam RF_AXI_STATUS_REGTYPE_MASK = 32'hFFFFFFFF;
localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
// RF_RESET_CONTROL_REGTYPE Type (from common_regs.v)
localparam RF_RESET_CONTROL_REGTYPE_SIZE = 32;
localparam RF_RESET_CONTROL_REGTYPE_MASK = 32'h331;
localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
// RF_RESET_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_RESET_STATUS_REGTYPE_SIZE = 32;
localparam RF_RESET_STATUS_REGTYPE_MASK = 32'h888;
localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
// RFDC_INFO_REGTYPE Type (from common_regs.v)
localparam RFDC_INFO_REGTYPE_SIZE = 32;
localparam RFDC_INFO_REGTYPE_MASK = 32'h3FF03FF;
localparam RFDC_INFO_XTRA_RESAMP_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP_MSB = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP = 0; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_SPC_RX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX_MSB = 6; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_TX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX_MSB = 9; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX = 7; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_XTRA_RESAMP_DB1_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1_MSB = 19; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1 = 16; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_SPC_RX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1_MSB = 22; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1 = 20; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_TX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1_MSB = 25; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1 = 23; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
//===============================================================================
// Register Group RFDC_REGS
//===============================================================================
// Enumerated type FABRIC_DSP_BW_ENUM
localparam FABRIC_DSP_BW_ENUM_SIZE = 5;
localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE
localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M
localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M
localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M
localparam FABRIC_DSP_BW_FULL = 'h3E8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_FULL
// MMCM Window (from x410_rfdc_regs.v)
localparam MMCM = 'h0; // Window Offset
localparam MMCM_SIZE = 'h10000; // size in bytes
// INVERT_DB0_IQ_REG Register (from x410_rfdc_regs.v)
localparam INVERT_DB0_IQ_REG = 'h10000; // Register Offset
localparam INVERT_DB0_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB0_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
// INVERT_DB1_IQ_REG Register (from x410_rfdc_regs.v)
localparam INVERT_DB1_IQ_REG = 'h10800; // Register Offset
localparam INVERT_DB1_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB1_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ_MSB = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ_MSB = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ_MSB = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ_MSB = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ_MSB = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ_MSB = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ_MSB = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ_MSB = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
// MMCM_RESET_REG Register (from x410_rfdc_regs.v)
localparam MMCM_RESET_REG = 'h11000; // Register Offset
localparam MMCM_RESET_REG_SIZE = 32; // register width in bits
localparam MMCM_RESET_REG_MASK = 32'h1;
localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM
// RF_RESET_CONTROL_REG Register (from x410_rfdc_regs.v)
localparam RF_RESET_CONTROL_REG = 'h12000; // Register Offset
localparam RF_RESET_CONTROL_REG_SIZE = 32; // register width in bits
// RF_RESET_STATUS_REG Register (from x410_rfdc_regs.v)
localparam RF_RESET_STATUS_REG = 'h12008; // Register Offset
localparam RF_RESET_STATUS_REG_SIZE = 32; // register width in bits
// RF_AXI_STATUS_REG Register (from x410_rfdc_regs.v)
localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset
localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits
// FABRIC_DSP_REG Register (from x410_rfdc_regs.v)
localparam FABRIC_DSP_REG = 'h13008; // Register Offset
localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits
// CALIBRATION_DATA Register (from x410_rfdc_regs.v)
localparam CALIBRATION_DATA = 'h14000; // Register Offset
localparam CALIBRATION_DATA_SIZE = 32; // register width in bits
localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF;
localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA
localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA
localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA
localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA
// CALIBRATION_ENABLE Register (from x410_rfdc_regs.v)
localparam CALIBRATION_ENABLE = 'h14008; // Register Offset
localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits
localparam CALIBRATION_ENABLE_MASK = 32'h33;
localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
// THRESHOLD_STATUS Register (from x410_rfdc_regs.v)
localparam THRESHOLD_STATUS = 'h15000; // Register Offset
localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits
localparam THRESHOLD_STATUS_MASK = 32'hF0F;
localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
// RF_PLL_CONTROL_REG Register (from x410_rfdc_regs.v)
localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset
localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits
localparam RF_PLL_CONTROL_REG_MASK = 32'h11111;
localparam ENABLE_DATA_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK_MSB = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_DATA_CLK_2X_MSB = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_DATA_CLK_2X = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_RF_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam ENABLE_RF_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam ENABLE_RF_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
// RF_PLL_STATUS_REG Register (from x410_rfdc_regs.v)
localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset
localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits
localparam RF_PLL_STATUS_REG_MASK = 32'h110000;
localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
// ADC_TILEMAP_REG Register (from x410_rfdc_regs.v)
localparam ADC_TILEMAP_REG = 'h17000; // Register Offset
localparam ADC_TILEMAP_REG_SIZE = 32; // register width in bits
// DAC_TILEMAP_REG Register (from x410_rfdc_regs.v)
localparam DAC_TILEMAP_REG = 'h17008; // Register Offset
localparam DAC_TILEMAP_REG_SIZE = 32; // register width in bits
// RFDC_INFO_REG Register (from x410_rfdc_regs.v)
localparam RFDC_INFO_REG = 'h18000; // Register Offset
localparam RFDC_INFO_REG_SIZE = 32; // register width in bits
top/x400/regmap/x410/versioning_regs_regmap_utils.vh
+153
View File
@@ -0,0 +1,153 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: versioning_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// CURRENT_VERSION : 0x0 (x4xx_versioning_regs.v)
// OLDEST_COMPATIBLE_VERSION : 0x4 (x4xx_versioning_regs.v)
// VERSION_LAST_MODIFIED : 0x8 (x4xx_versioning_regs.v)
// RESERVED : 0xC (x4xx_versioning_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
// RESERVED_TYPE Type (from x4xx_versioning_regs.v)
localparam RESERVED_TYPE_SIZE = 32;
localparam RESERVED_TYPE_MASK = 32'h0;
// TIMESTAMP_TYPE Type (from x4xx_versioning_regs.v)
localparam TIMESTAMP_TYPE_SIZE = 32;
localparam TIMESTAMP_TYPE_MASK = 32'hFFFFFFFF;
localparam HH_SIZE = 8; //TIMESTAMP_TYPE:HH
localparam HH_MSB = 7; //TIMESTAMP_TYPE:HH
localparam HH = 0; //TIMESTAMP_TYPE:HH
localparam DD_SIZE = 8; //TIMESTAMP_TYPE:DD
localparam DD_MSB = 15; //TIMESTAMP_TYPE:DD
localparam DD = 8; //TIMESTAMP_TYPE:DD
localparam MM_SIZE = 8; //TIMESTAMP_TYPE:MM
localparam MM_MSB = 23; //TIMESTAMP_TYPE:MM
localparam MM = 16; //TIMESTAMP_TYPE:MM
localparam YY_SIZE = 8; //TIMESTAMP_TYPE:YY
localparam YY_MSB = 31; //TIMESTAMP_TYPE:YY
localparam YY = 24; //TIMESTAMP_TYPE:YY
// VERSION_TYPE Type (from x4xx_versioning_regs.v)
localparam VERSION_TYPE_SIZE = 32;
localparam VERSION_TYPE_MASK = 32'hFFFFFFFF;
localparam BUILD_SIZE = 12; //VERSION_TYPE:BUILD
localparam BUILD_MSB = 11; //VERSION_TYPE:BUILD
localparam BUILD = 0; //VERSION_TYPE:BUILD
localparam MINOR_SIZE = 11; //VERSION_TYPE:MINOR
localparam MINOR_MSB = 22; //VERSION_TYPE:MINOR
localparam MINOR = 12; //VERSION_TYPE:MINOR
localparam MAJOR_SIZE = 9; //VERSION_TYPE:MAJOR
localparam MAJOR_MSB = 31; //VERSION_TYPE:MAJOR
localparam MAJOR = 23; //VERSION_TYPE:MAJOR
//===============================================================================
// Register Group VERSIONING_CONSTANTS
//===============================================================================
// Enumerated type CPLD_IFC_VERSION
localparam CPLD_IFC_VERSION_SIZE = 7;
localparam CPLD_IFC_CURRENT_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MINOR
localparam CPLD_IFC_CURRENT_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_BUILD
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
localparam CPLD_IFC_CURRENT_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MAJOR
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam CPLD_IFC_VERSION_LAST_MODIFIED_TIME = 'h21011809; // CPLD_IFC_VERSION:CPLD_IFC_VERSION_LAST_MODIFIED_TIME
// Enumerated type DB_GPIO_IFC_VERSION
localparam DB_GPIO_IFC_VERSION_SIZE = 7;
localparam DB_GPIO_IFC_CURRENT_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MINOR
localparam DB_GPIO_IFC_CURRENT_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_BUILD
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
localparam DB_GPIO_IFC_CURRENT_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MAJOR
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h20110616; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME
// Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7;
localparam RF_CORE_100M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MINOR
localparam RF_CORE_100M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_BUILD
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_100M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MAJOR
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_100M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_100M_VERSION:RF_CORE_100M_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_400M_VERSION
localparam RF_CORE_400M_VERSION_SIZE = 7;
localparam RF_CORE_400M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MINOR
localparam RF_CORE_400M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_BUILD
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_400M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MAJOR
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_400M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_400M_VERSION:RF_CORE_400M_VERSION_LAST_MODIFIED_TIME
//===============================================================================
// Register Group VERSIONING_REGS
//===============================================================================
// Enumerated type COMPONENTS_INDEXES
localparam COMPONENTS_INDEXES_SIZE = 6;
localparam FPGA_VERSION_INDEX = 'h0; // COMPONENTS_INDEXES:FPGA_VERSION_INDEX
localparam CPLD_IFC_INDEX = 'h1; // COMPONENTS_INDEXES:CPLD_IFC_INDEX
localparam DB0_RF_CORE_INDEX = 'h2; // COMPONENTS_INDEXES:DB0_RF_CORE_INDEX
localparam DB1_RF_CORE_INDEX = 'h3; // COMPONENTS_INDEXES:DB1_RF_CORE_INDEX
localparam DB0_GPIO_IFC_INDEX = 'h4; // COMPONENTS_INDEXES:DB0_GPIO_IFC_INDEX
localparam DB1_GPIO_IFC_INDEX = 'h5; // COMPONENTS_INDEXES:DB1_GPIO_IFC_INDEX
// CURRENT_VERSION Register (from x4xx_versioning_regs.v)
localparam CURRENT_VERSION_COUNT = 64; // Number of elements in array
// OLDEST_COMPATIBLE_VERSION Register (from x4xx_versioning_regs.v)
localparam OLDEST_COMPATIBLE_VERSION_COUNT = 64; // Number of elements in array
// VERSION_LAST_MODIFIED Register (from x4xx_versioning_regs.v)
localparam VERSION_LAST_MODIFIED_COUNT = 64; // Number of elements in array
// RESERVED Register (from x4xx_versioning_regs.v)
localparam RESERVED_COUNT = 64; // Number of elements in array
// Return the offset of an element of register array CURRENT_VERSION
function integer CURRENT_VERSION (input integer i);
CURRENT_VERSION = (i * 'h10) + 'h0;
endfunction
// Return the offset of an element of register array OLDEST_COMPATIBLE_VERSION
function integer OLDEST_COMPATIBLE_VERSION (input integer i);
OLDEST_COMPATIBLE_VERSION = (i * 'h10) + 'h4;
endfunction
// Return the offset of an element of register array VERSION_LAST_MODIFIED
function integer VERSION_LAST_MODIFIED (input integer i);
VERSION_LAST_MODIFIED = (i * 'h10) + 'h8;
endfunction
// Return the offset of an element of register array RESERVED
function integer RESERVED (input integer i);
RESERVED = (i * 'h10) + 'hC;
endfunction
top/x400/rf/100m/rf_core_100m.v
+9 -4
View File
@@ -98,8 +98,9 @@ module rf_core_100m (
// Control/status vectors from/to RFDC.
// Notice these are all in the s_axi_config_clk domain.
output wire [15:0] dsp_info_sclk,
output wire [9:0] dsp_info_sclk,
output wire [15:0] axi_status_sclk,
output wire [15:0] rfdc_info_sclk,
// Resets.
input wire adc_data_out_resetn_dclk,
@@ -114,8 +115,8 @@ module rf_core_100m (
output wire [95:0] version_info
);
`include "../../regmap/rfdc_regs_regmap_utils.vh"
`include "../../regmap/versioning_regs_regmap_utils.vh"
`include "../../regmap/x410/rfdc_regs_regmap_utils.vh"
`include "../../regmap/x410/versioning_regs_regmap_utils.vh"
`include "../../regmap/versioning_utils.vh"
// Fixed for this implementation.
@@ -177,10 +178,14 @@ module rf_core_100m (
);
// Drive the DSP info vector with information on this specific DSP chain.
assign dsp_info_sclk[FABRIC_DSP_BW_MSB :FABRIC_DSP_BW] = FABRIC_DSP_BW_100M;
assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS;
assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS;
// This RF core always consumes 2 SPC from the gearbox per I/Q signal
assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(2);
assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(4);
assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd3;
//---------------------------------------------------------------------------
// ADC Post-Processing
//---------------------------------------------------------------------------
top/x400/rf/200m/rf_core_200m.v
+9 -7
View File
@@ -89,8 +89,9 @@ module rf_core_200m (
// Control/status vectors from/to RFDC.
// Notice these are all in the s_axi_config_clk domain.
output reg [15:0] dsp_info_sclk,
output wire [9:0] dsp_info_sclk,
output wire [15:0] axi_status_sclk,
output wire [15:0] rfdc_info_sclk,
// Resets.
input wire adc_data_out_resetn_dclk,
@@ -105,7 +106,7 @@ module rf_core_200m (
output wire [95:0] version_info
);
`include "../../regmap/rfdc_regs_regmap_utils.vh"
`include "../../regmap/x410/rfdc_regs_regmap_utils.vh"
//---------------------------------------------------------------------------
// 400 MHz RF Core
@@ -170,11 +171,12 @@ module rf_core_200m (
.version_info (version_info)
);
// Change reported bandwidth 200 MHz
always @(*) begin
dsp_info_sclk <= dsp_info_sclk_400m;
dsp_info_sclk[FABRIC_DSP_BW_MSB : FABRIC_DSP_BW] <= FABRIC_DSP_BW_200M;
end
assign dsp_info_sclk = dsp_info_sclk_400m;
// This RF core always consumes 8 SPC from the gearbox per I/Q signal
assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8);
assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16);
assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd6;
//---------------------------------------------------------------------------
top/x400/rf/400m/rf_core_400m.v
+9 -4
View File
@@ -101,8 +101,9 @@ module rf_core_400m (
// Control/status vectors from/to RFDC.
// Notice these are all in the s_axi_config_clk domain.
output wire [15:0] dsp_info_sclk,
output wire [9:0] dsp_info_sclk,
output wire [15:0] axi_status_sclk,
output wire [15:0] rfdc_info_sclk,
// Resets.
input wire adc_data_out_resetn_dclk,
@@ -117,8 +118,8 @@ module rf_core_400m (
output wire [95:0] version_info
);
`include "../../regmap/rfdc_regs_regmap_utils.vh"
`include "../../regmap/versioning_regs_regmap_utils.vh"
`include "../../regmap/x410/rfdc_regs_regmap_utils.vh"
`include "../../regmap/x410/versioning_regs_regmap_utils.vh"
`include "../../regmap/versioning_utils.vh"
// Fixed for this implementation
@@ -181,10 +182,14 @@ module rf_core_400m (
);
// Drive the DSP info vector with information on this specific DSP chain.
assign dsp_info_sclk[FABRIC_DSP_BW_MSB :FABRIC_DSP_BW] = FABRIC_DSP_BW_400M;
assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS;
assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS;
// This RF core always consumes 8 SPC from the gearbox per I/Q signal
assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8);
assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16);
assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd3;
//---------------------------------------------------------------------------
// ADC Post-Processing
//---------------------------------------------------------------------------
top/x400/rf/common/Makefile.srcs
+5 -2
View File
@@ -8,11 +8,14 @@ RF_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/common/, \
PkgRf.vhd \
axis_mux.vhd \
capture_sysref.v \
clock_gates.vhd \
gpio_to_axis_mux.vhd \
rf_nco_reset.vhd \
rf_reset.vhd \
rf_reset_controller.vhd \
scale_2x.vhd \
sync_wrapper.v \
))
RF_X410_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/x410/, \
x410_rf_reset_controller.vhd \
x410_clock_gates.vhd \
))
top/x400/rf/common/capture_sysref.v
+12 -3
View File
@@ -7,8 +7,15 @@
//
// Description:
//
// Capture SYSREF and transfer it to the higher clock domain. Module incurs
// in 2 pll_ref_clk cycles + 1 rfdc_clk cycle of delay.
// Capture SYSREF and transfer it to the higher clock domain.
// For X410, module incurs in 2 pll_ref_clk cycles + 1 rfdc_clk
// cycle of delay. For X440, module synchronizes to each
// pll_ref_clk and rfdc_clk separately, incurring in 2 cycles
// for each clock.
//
// Parameters:
//
// DEVICE_TYPE : Type of device for which SYSREF is synchronized.
//
module capture_sysref (
@@ -25,7 +32,9 @@ module capture_sysref (
output wire sysref_out_rclk // RFDC output (Domain: rfdc_clk).
);
reg sysref_pclk_ms = 1'b0, sysref_pclk = 1'b0, sysref_rclk = 1'b0;
(* ASYNC_REG = "TRUE" *) reg sysref_pclk_ms = 1'b0;
reg sysref_pclk = 1'b0;
reg sysref_rclk = 1'b0;
// Capture SYSREF synchronously with the pll_ref_clk, but double-sync it just
// in case static timing isn't met so as not to destroy downstream logic.
top/x400/rf/common/gpio_to_axis_mux.vhd
+101 -6
View File
@@ -1,5 +1,5 @@
--
-- Copyright 2021 Ettus Research, a National Instruments Brand
-- Copyright 2022 Ettus Research, a National Instruments Brand
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
@@ -38,8 +38,6 @@ entity gpio_to_axis_mux is
-- mux_select(n) chooses the data source for AXIS interface n.
-- '0' chooses s_axis_tdata_n. '1' chooses gpio as the data source.
-- The only used bits are 0, 1, 4, 5. The remaining bits are reserved for
-- future expansion.
mux_select : in std_logic_vector(7 downto 0);
s_axis_0_aclk : in std_logic;
@@ -72,7 +70,39 @@ entity gpio_to_axis_mux is
s_axis_tready_3 : out std_logic;
m_axis_3_aclk : in std_logic;
m_axis_tvalid_3 : out std_logic;
m_axis_tdata_3 : out std_logic_vector(kAxiWidth - 1 downto 0)
m_axis_tdata_3 : out std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_4_aclk : in std_logic;
s_axis_tdata_4 : in std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_tvalid_4 : in std_logic;
s_axis_tready_4 : out std_logic;
m_axis_4_aclk : in std_logic;
m_axis_tvalid_4 : out std_logic;
m_axis_tdata_4 : out std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_5_aclk : in std_logic;
s_axis_tdata_5 : in std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_tvalid_5 : in std_logic;
s_axis_tready_5 : out std_logic;
m_axis_5_aclk : in std_logic;
m_axis_tvalid_5 : out std_logic;
m_axis_tdata_5 : out std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_6_aclk : in std_logic;
s_axis_tdata_6 : in std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_tvalid_6 : in std_logic;
s_axis_tready_6 : out std_logic;
m_axis_6_aclk : in std_logic;
m_axis_tvalid_6 : out std_logic;
m_axis_tdata_6 : out std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_7_aclk : in std_logic;
s_axis_tdata_7 : in std_logic_vector(kAxiWidth - 1 downto 0);
s_axis_tvalid_7 : in std_logic;
s_axis_tready_7 : out std_logic;
m_axis_7_aclk : in std_logic;
m_axis_tvalid_7 : out std_logic;
m_axis_tdata_7 : out std_logic_vector(kAxiWidth - 1 downto 0)
);
end entity;
@@ -118,7 +148,7 @@ begin
kAxiWidth => kAxiWidth)
port map (
gpio => gpio,
mux_select => mux_select(4),
mux_select => mux_select(2),
s_axis_aclk => s_axis_2_aclk,
s_axis_tdata => s_axis_tdata_2,
s_axis_tvalid => s_axis_tvalid_2,
@@ -134,7 +164,7 @@ begin
kAxiWidth => kAxiWidth)
port map (
gpio => gpio,
mux_select => mux_select(5),
mux_select => mux_select(3),
s_axis_aclk => s_axis_3_aclk,
s_axis_tdata => s_axis_tdata_3,
s_axis_tvalid => s_axis_tvalid_3,
@@ -144,4 +174,69 @@ begin
m_axis_tdata => m_axis_tdata_3
);
axis_mux4: entity work.axis_mux (RTL)
generic map (
kGpioWidth => kGpioWidth,
kAxiWidth => kAxiWidth)
port map (
gpio => gpio,
mux_select => mux_select(4),
s_axis_aclk => s_axis_4_aclk,
s_axis_tdata => s_axis_tdata_4,
s_axis_tvalid => s_axis_tvalid_4,
s_axis_tready => s_axis_tready_4,
m_axis_aclk => m_axis_4_aclk,
m_axis_tvalid => m_axis_tvalid_4,
m_axis_tdata => m_axis_tdata_4
);
axis_mux5: entity work.axis_mux (RTL)
generic map (
kGpioWidth => kGpioWidth,
kAxiWidth => kAxiWidth)
port map (
gpio => gpio,
mux_select => mux_select(5),
s_axis_aclk => s_axis_5_aclk,
s_axis_tdata => s_axis_tdata_5,
s_axis_tvalid => s_axis_tvalid_5,
s_axis_tready => s_axis_tready_5,
m_axis_aclk => m_axis_5_aclk,
m_axis_tvalid => m_axis_tvalid_5,
m_axis_tdata => m_axis_tdata_5
);
axis_mux6: entity work.axis_mux (RTL)
generic map (
kGpioWidth => kGpioWidth,
kAxiWidth => kAxiWidth)
port map (
gpio => gpio,
mux_select => mux_select(6),
s_axis_aclk => s_axis_6_aclk,
s_axis_tdata => s_axis_tdata_6,
s_axis_tvalid => s_axis_tvalid_6,
s_axis_tready => s_axis_tready_6,
m_axis_aclk => m_axis_6_aclk,
m_axis_tvalid => m_axis_tvalid_6,
m_axis_tdata => m_axis_tdata_6
);
axis_mux7: entity work.axis_mux (RTL)
generic map (
kGpioWidth => kGpioWidth,
kAxiWidth => kAxiWidth)
port map (
gpio => gpio,
mux_select => mux_select(7),
s_axis_aclk => s_axis_7_aclk,
s_axis_tdata => s_axis_tdata_7,
s_axis_tvalid => s_axis_tvalid_7,
s_axis_tready => s_axis_tready_7,
m_axis_aclk => m_axis_7_aclk,
m_axis_tvalid => m_axis_tvalid_7,
m_axis_tdata => m_axis_tdata_7
);
end RTL;
top/x400/rf/common/rf_nco_reset.vhd
+20 -1
View File
@@ -59,6 +59,13 @@ entity rf_nco_reset is
cAdc0xNcoUpdateBusy : in std_logic;
cAdc0xNcoUpdateReq : out std_logic := '0';
-----------------------------------
--ADC Tile 225
-----------------------------------
-- ADC common NCO update controls and status.
cAdc1xNcoUpdateBusy : in std_logic;
cAdc1xNcoUpdateReq : out std_logic := '0';
-----------------------------------
--ADC Tile 226
-----------------------------------
@@ -66,6 +73,13 @@ entity rf_nco_reset is
cAdc2xNcoUpdateBusy : in std_logic;
cAdc2xNcoUpdateReq : out std_logic := '0';
-----------------------------------
--ADC Tile 227
-----------------------------------
-- ADC common NCO update controls and status.
cAdc3xNcoUpdateBusy : in std_logic;
cAdc3xNcoUpdateReq : out std_logic := '0';
-- NCO reset can be initiated only when cNcoPhaseRst is set to '1' and
-- cNcoUpdateEn = 0x20. The FSM in this entity will set these values when
-- an NCO reset is initiated during synchronization. These ports are common
@@ -146,7 +160,9 @@ begin
cDac0xSysrefIntReenable <= '0';
cDac1xNcoUpdateReq <= '0';
cAdc0xNcoUpdateReq <= '0';
cAdc1xNcoUpdateReq <= '0';
cAdc2xNcoUpdateReq <= '0';
cAdc3xNcoUpdateReq <= '0';
case cResetState is
-- Stay in this state until NCO reset sequence is initiated. NCO reset
-- is initiated only on the rising edge of SYSREF.
@@ -177,7 +193,9 @@ begin
cResetState <= CheckUpdateDone;
cDac1xNcoUpdateReq <= '1';
cAdc0xNcoUpdateReq <= '1';
cAdc1xNcoUpdateReq <= '1';
cAdc2xNcoUpdateReq <= '1';
cAdc3xNcoUpdateReq <= '1';
end if;
-- In this state, we check if the RFDC block is ready for NCO reset.
@@ -187,7 +205,8 @@ begin
cSysrefIntGating <= '1';
cResetState <= CheckUpdateDone;
if cDac0xNcoUpdateBusy = "10" and cAdc0xNcoUpdateBusy = '0' and
cAdc2xNcoUpdateBusy = '0' and cDac1xNcoUpdateBusy = '0' and
cAdc1xNcoUpdateBusy = '0' and cAdc2xNcoUpdateBusy = '0' and
cAdc3xNcoUpdateBusy = '0' and cDac1xNcoUpdateBusy = '0' and
cSysref = '1' and cSysrefDlyd = '0' then
cDac0xSysrefIntReenable <= '1';
cResetState <= CheckResetDone;
top/x400/rf/sim/Makefile
+14 -13
View File
@@ -36,8 +36,9 @@ include ../200m/Makefile.srcs
include ../400m/Makefile.srcs
DESIGN_SRCS += $(abspath \
../../regmap/PkgRFDC_REGS_REGMAP.vhd \
../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd \
$(RF_COMMON_SRCS) \
$(RF_X410_SRCS) \
$(RF_100M_SRCS) \
$(RF_200M_SRCS) \
$(RF_400M_SRCS) \
@@ -68,18 +69,18 @@ SIM_TOP = rf_all_tb
SIM_RUNTIME_US = 1000
SIM_SRCS = \
$(abspath tb_adc_gearbox_2x1.vhd ) \
$(abspath tb_adc_gearbox_2x4.vhd ) \
$(abspath tb_adc_gearbox_8x4.vhd ) \
$(abspath tb_capture_sysref.vhd ) \
$(abspath tb_dac_gearbox_12x8.vhd ) \
$(abspath tb_dac_gearbox_4x2.vhd ) \
$(abspath tb_dac_gearbox_6x12.vhd ) \
$(abspath tb_ddc_400m_saturate.vhd ) \
$(abspath tb_duc_400m_saturate.vhd ) \
$(abspath tb_rf_nco_reset.vhd ) \
$(abspath tb_rf_reset_controller.vhd) \
$(abspath rf_all_tb.sv ) \
$(abspath tb_adc_gearbox_2x1.vhd ) \
$(abspath tb_adc_gearbox_2x4.vhd ) \
$(abspath tb_adc_gearbox_8x4.vhd ) \
$(abspath tb_capture_sysref.vhd ) \
$(abspath tb_dac_gearbox_12x8.vhd ) \
$(abspath tb_dac_gearbox_4x2.vhd ) \
$(abspath tb_dac_gearbox_6x12.vhd ) \
$(abspath tb_ddc_400m_saturate.vhd ) \
$(abspath tb_duc_400m_saturate.vhd ) \
$(abspath tb_rf_nco_reset.vhd ) \
$(abspath tb_x410_rf_reset_controller.vhd ) \
$(abspath rf_all_tb.sv ) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x400/rf/sim/rf_all_tb.sv
+22 -22
View File
@@ -15,17 +15,17 @@ module rf_all_tb;
`include "test_exec.svh"
import PkgTestExec::*;
tb_adc_gearbox_2x1 tb_adc_gearbox_2x1_i ();
tb_adc_gearbox_2x4 tb_adc_gearbox_2x4_i ();
tb_adc_gearbox_8x4 tb_adc_gearbox_8x4_i ();
tb_capture_sysref tb_capture_sysref_i ();
tb_dac_gearbox_12x8 tb_dac_gearbox_12x8_i ();
tb_dac_gearbox_4x2 tb_dac_gearbox_4x2_i ();
tb_dac_gearbox_6x12 tb_dac_gearbox_6x12_i ();
tb_ddc_400m_saturate tb_ddc_400m_saturate_i ();
tb_duc_400m_saturate tb_duc_400m_saturate_i ();
tb_rf_nco_reset tb_rf_nco_reset_i ();
tb_rf_reset_controller tb_rf_reset_controller_i ();
tb_adc_gearbox_2x1 tb_adc_gearbox_2x1_i ();
tb_adc_gearbox_2x4 tb_adc_gearbox_2x4_i ();
tb_adc_gearbox_8x4 tb_adc_gearbox_8x4_i ();
tb_capture_sysref tb_capture_sysref_i ();
tb_dac_gearbox_12x8 tb_dac_gearbox_12x8_i ();
tb_dac_gearbox_4x2 tb_dac_gearbox_4x2_i ();
tb_dac_gearbox_6x12 tb_dac_gearbox_6x12_i ();
tb_ddc_400m_saturate tb_ddc_400m_saturate_i ();
tb_duc_400m_saturate tb_duc_400m_saturate_i ();
tb_rf_nco_reset tb_rf_nco_reset_i ();
tb_x410_rf_reset_controller tb_x410_rf_reset_controller_i ();
initial begin
test.start_tb("rf_all_tb", 1ms);
@@ -34,17 +34,17 @@ module rf_all_tb;
forever begin
#100ns;
if (
tb_adc_gearbox_2x1_i.StopSim &&
tb_adc_gearbox_2x4_i.StopSim &&
tb_adc_gearbox_8x4_i.StopSim &&
tb_capture_sysref_i.StopSim &&
tb_dac_gearbox_12x8_i.StopSim &&
tb_dac_gearbox_4x2_i.StopSim &&
tb_dac_gearbox_6x12_i.StopSim &&
tb_ddc_400m_saturate_i.StopSim &&
tb_duc_400m_saturate_i.StopSim &&
tb_rf_nco_reset_i.StopSim &&
tb_rf_reset_controller_i.StopSim
tb_adc_gearbox_2x1_i.StopSim &&
tb_adc_gearbox_2x4_i.StopSim &&
tb_adc_gearbox_8x4_i.StopSim &&
tb_capture_sysref_i.StopSim &&
tb_dac_gearbox_12x8_i.StopSim &&
tb_dac_gearbox_4x2_i.StopSim &&
tb_dac_gearbox_6x12_i.StopSim &&
tb_ddc_400m_saturate_i.StopSim &&
tb_duc_400m_saturate_i.StopSim &&
tb_rf_nco_reset_i.StopSim &&
tb_x410_rf_reset_controller_i.StopSim
) break;
end
test.end_test();
top/x400/rf/sim/tb_rf_nco_reset.vhd
+12
View File
@@ -21,7 +21,9 @@ end tb_rf_nco_reset;
architecture RTL of tb_rf_nco_reset is
signal cAdc0xNcoUpdateReq : std_logic;
signal cAdc1xNcoUpdateReq : std_logic;
signal cAdc2xNcoUpdateReq : std_logic;
signal cAdc3xNcoUpdateReq : std_logic;
signal cDac0xNcoUpdateReq : std_logic;
signal cDac0xSysrefIntGating : std_logic;
signal cDac0xSysrefIntReenable : std_logic;
@@ -33,7 +35,9 @@ architecture RTL of tb_rf_nco_reset is
signal cDac0xNcoUpdateBusy : std_logic_vector(1 downto 0) := "00";
signal dStartNcoReset : std_logic := '0';
signal cAdc0xNcoUpdateBusy : std_logic := '0';
signal cAdc1xNcoUpdateBusy : std_logic := '0';
signal cAdc2xNcoUpdateBusy : std_logic := '0';
signal cAdc3xNcoUpdateBusy : std_logic := '0';
signal cDac1xNcoUpdateBusy : std_logic := '0';
signal cSysref_ms, cSysref : std_logic := '0';
@@ -100,8 +104,12 @@ begin
cDac1xNcoUpdateReq => cDac1xNcoUpdateReq,
cAdc0xNcoUpdateBusy => cAdc0xNcoUpdateBusy,
cAdc0xNcoUpdateReq => cAdc0xNcoUpdateReq,
cAdc1xNcoUpdateBusy => cAdc1xNcoUpdateBusy,
cAdc1xNcoUpdateReq => cAdc1xNcoUpdateReq,
cAdc2xNcoUpdateBusy => cAdc2xNcoUpdateBusy,
cAdc2xNcoUpdateReq => cAdc2xNcoUpdateReq,
cAdc3xNcoUpdateBusy => cAdc3xNcoUpdateBusy,
cAdc3xNcoUpdateReq => cAdc3xNcoUpdateReq,
cNcoPhaseRst => cNcoPhaseRst,
cNcoUpdateEn => cNcoUpdateEn,
dNcoResetDone => dNcoResetDone
@@ -180,7 +188,9 @@ begin
cRfdcNcoState <= CheckUpdate;
cDac1xNcoUpdateBusy <= cDac1xNcoUpdateReq;
cAdc0xNcoUpdateBusy <= cAdc0xNcoUpdateReq;
cAdc1xNcoUpdateBusy <= cAdc1xNcoUpdateReq;
cAdc2xNcoUpdateBusy <= cAdc2xNcoUpdateReq;
cAdc3xNcoUpdateBusy <= cAdc3xNcoUpdateReq;
-- It takes 5 clock cycles to update each RFDC internal registers with
-- the used request change. In rf_nco_reset entity, we only want to
@@ -194,7 +204,9 @@ begin
cDac0xNcoUpdateBusy <= "10"; --Indicates that SYSREF is gated.
cDac1xNcoUpdateBusy <= '0';
cAdc0xNcoUpdateBusy <= '0';
cAdc1xNcoUpdateBusy <= '0';
cAdc2xNcoUpdateBusy <= '0';
cAdc3xNcoUpdateBusy <= '0';
end if;
cWrCount <= cWrCount + 1;
top/x400/rf/sim/tb_rf_reset_controller.vhd → top/x400/rf/sim/tb_x410_rf_reset_controller.vhd
+7 -7
View File
@@ -3,11 +3,11 @@
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: tb_rf_reset_controller
-- Module: tb_x410_rf_reset_controller
--
-- Description:
--
-- Testbench for rf_reset_controller.
-- Testbench for x410_rf_reset_controller.
--
library IEEE;
@@ -17,13 +17,13 @@ library IEEE;
library WORK;
use WORK.PkgRFDC_REGS_REGMAP.all;
entity tb_rf_reset_controller is
end tb_rf_reset_controller;
entity tb_x410_rf_reset_controller is
end tb_x410_rf_reset_controller;
architecture RTL of tb_rf_reset_controller is
architecture RTL of tb_x410_rf_reset_controller is
component rf_reset_controller
component x410_rf_reset_controller
port (
ConfigClk : in std_logic;
DataClk : in std_logic;
@@ -185,7 +185,7 @@ begin
PllRefClk <= not PllRefClk after kPllRefClkPer/2 when not StopSim else '0';
-- rAdcEnableData is a constant and is not tested.
dut: rf_reset_controller
dut: x410_rf_reset_controller
port map (
ConfigClk => ConfigClk,
DataClk => DataClk,
top/x400/rf/x410/x410_clock_gates.vhd
+300
View File
@@ -0,0 +1,300 @@
--
-- Copyright 2021 Ettus Research, a National Instruments Brand
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: x410_clock_gates
--
-- Description:
--
-- Gate propagation of DataClk and RfdcClk instances until the PLL lock
-- status signal is stable and software has acknowledged it by asserting the
-- pertinent controls.
--
-- RfdcClks are used on other Xilinx IP components in the Board Design, and
-- Vivado fails to detect their frequency correctly their buffer is
-- explicitly instantiated in the Block Design. Therefore, we only generate
-- the buffer enable signals for these clocks within this component.
--
-- Since DataClk are only used in other Custom IP blocks within the Block
-- design, it is possible to instantiate the clock buffers within this block
-- for without running into IP generation failures.
--
-- Parameters:
--
-- kReliableClkPeriodNs: Clock period (ns) for ReliableClk.
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library WORK;
use WORK.PkgRFDC_REGS_REGMAP.all;
entity x410_clock_gates is
generic (
kReliableClkPeriodNs : integer := 25
);
port (
-- MMCM reset
-- This clock will be asserted via AXI access before any clocking
-- configuration done, signals coming into this component will not change
-- immediately after this reset is de-asserted.
rPllReset_n : in std_logic;
aPllLocked : in std_logic;
-- Input Clocks (from MMCM)
ReliableClk : in std_logic;
DataClk1xPll : in std_logic;
DataClk2xPll : in std_logic;
-- Buffered Clock Outputs (to design)
DataClk1x : out std_logic;
DataClk2x : out std_logic;
-- Buffers for these signals must be instantiated on Block design for clock
-- rates to be identified. The Utility Buffers instantiated on the Block
-- Design require signals to be of type std_logic_vector.
aEnableRfBufg1x : out std_logic_vector(0 downto 0);
aEnableRfBufg2x : out std_logic_vector(0 downto 0);
-- PLL Status Signals
rPllLocked : out std_logic;
-- Window Interface
rSafeToEnableGatedClks : in std_logic;
rGatedBaseClksValid : out std_logic;
-- AXI GPIO interface
rSoftwareControl : in std_logic_vector(31 downto 0);
rSoftwareStatus : out std_logic_vector(31 downto 0)
);
end x410_clock_gates;
architecture STRUCT of x410_clock_gates is
component sync_wrapper
generic (
WIDTH : integer := 1;
STAGES : integer := 2;
INITIAL_VAL : integer := 0;
FALSE_PATH_TO_IN : integer := 1);
port (
clk : in std_logic;
rst : in std_logic;
signal_in : in std_logic_vector((WIDTH-1) downto 0);
signal_out : out std_logic_vector((WIDTH-1) downto 0));
end component;
component BUFGCE
generic(
CE_TYPE : string);
port (
O : out std_ulogic;
CE : in std_ulogic;
I : in std_ulogic);
end component;
-- UltraScale MMCM max lock time = 100 us / 25 ns = 4,000 clk cycles. If the
-- division kPllLockTimeNs / kReliableClkPeriodNs does not evaluate to an
-- integer, Vivado could either round up or down. In case they round down, we
-- add '1' to the result to ensure we have the full lock time accounted for.
-- In this case, it is better to count 1 more than necessary than kill the
-- process prematurely.
constant kPllLockTimeNs : integer := 100000;
constant kMaxPllLockCount : integer := kPllLockTimeNs / kReliableClkPeriodNs + 1;
signal rLockedFilterCount : integer range 0 to kMaxPllLockCount-1 := kMaxPllLockCount-1;
signal rClearDataClkUnlockedSticky : std_logic;
-----------------------------------------------------------------------------
-- PLL locked signals
-----------------------------------------------------------------------------
-- Synchronizer signals
signal aPllLockedLcl : std_logic_vector(0 downto 0);
signal rPllLockedDs : std_logic_vector(0 downto 0) := (others => '0');
-- Lock status indicators
signal rPllLockedLcl : std_logic := '0';
signal rPllUnlockedSticky : std_logic := '0';
-- Safe BUFG enable signals
signal rEnableDataClk1x,
rEnableDataClk2x,
rEnableRfdcClk1x,
rEnableRfdcClk2x : std_logic;
signal rEnableDataBufg1x : std_logic := '0';
signal rEnableDataBufg2x : std_logic := '0';
signal rEnableRfdcBufg1xLcl : std_logic := '0';
signal rEnableRfdcBufg2xLcl : std_logic := '0';
-- Active high version of reset required for synchronizer blocks.
signal rPllReset : std_logic;
-- Since these signals control sensitive components (clock enables), we apply
-- a dont_touch attribute to preserve the signals through both synthesis and
-- P&R. Implementation of "dont_touch" has been confirmed after P&R.
attribute dont_touch : string;
attribute dont_touch of rEnableDataBufg1x : signal is "TRUE";
attribute dont_touch of rEnableDataBufg2x : signal is "TRUE";
attribute dont_touch of aEnableRfBufg1x : signal is "TRUE";
attribute dont_touch of aEnableRfBufg2x : signal is "TRUE";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_INFO of DataClk1xPll : signal is
"xilinx.com:signal:clock:1.0 DataClk1xPll CLK";
attribute X_INTERFACE_INFO of DataClk2xPll : signal is
"xilinx.com:signal:clock:1.0 DataClk2xPll CLK";
begin
rPllReset <= not rPllReset_n;
-- Assert rGatedBaseClksValid once the PLL has been locked for the specified
-- time.
rGatedBaseClksValid <= rPllLockedLcl;
DataClkEnables : process(ReliableClk)
begin
if rising_edge(ReliableClk) then
if rPllReset_n = '0' then
rEnableDataBufg1x <= '0';
rEnableDataBufg2x <= '0';
rEnableRfdcBufg1xLcl <= '0';
rEnableRfdcBufg2xLcl <= '0';
else
rEnableDataBufg1x <=
rSafeToEnableGatedClks and
rEnableDataClk1x and
(not rPllUnlockedSticky);
rEnableDataBufg2x <=
rSafeToEnableGatedClks and
rEnableDataClk2x and
(not rPllUnlockedSticky);
rEnableRfdcBufg1xLcl <=
rSafeToEnableGatedClks and
rEnableRfdcClk1x and
(not rPllUnlockedSticky);
rEnableRfdcBufg2xLcl <=
rSafeToEnableGatedClks and
rEnableRfdcClk2x and
(not rPllUnlockedSticky);
end if;
end if;
end process DataClkEnables;
aEnableRfBufg1x(0) <= rEnableRfdcBufg1xLcl;
aEnableRfBufg2x(0) <= rEnableRfdcBufg2xLcl;
DataClk1xSafeBufg: BUFGCE
generic map(
CE_TYPE => "ASYNC"
)
port map (
I => DataClk1xPll,
CE => rEnableDataBufg1x,
O => DataClk1x
);
DataClk2xSafeBufg: BUFGCE
generic map(
CE_TYPE => "ASYNC"
)
port map (
I => DataClk2xPll,
CE => rEnableDataBufg2x,
O => DataClk2x
);
-----------------------------------------------------------------------------
-- Create PLL Lock Signal
-----------------------------------------------------------------------------
-- Double-sync the incoming aPllLocked signal from the PLL.
aPllLockedLcl(0) <= aPllLocked;
DataClkPllLockedDS: sync_wrapper
generic map (
WIDTH => 1,
STAGES => open,
INITIAL_VAL => open,
FALSE_PATH_TO_IN => open)
port map (
clk => ReliableClk,
rst => rPllReset,
signal_in => aPllLockedLcl,
signal_out => rPllLockedDs
);
-- Filter the Lock signal. Assert a lock when the PLL lock signal has been
-- asserted for kPllLockTimeNs
--
-- !!! SAFE COUNTER STARTUP !!!
-- rLockedFilterCount cannot start incrementing until rPllReset_n is
-- de-asserted. Once rPllReset_n is de-asserted through a AXI access, input
-- values for the registers in this state machine will not change until the
-- MMCM locks and the double synchronizer reflects a locked status, making
-- this start-up safe.
PllLockFilter: process (ReliableClk)
begin
if rising_edge(ReliableClk) then
if rPllReset_n = '0' then
rLockedFilterCount <= kMaxPllLockCount-1;
rPllLockedLcl <= '0';
else
if rPllLockedDs(0) = '1' then
if rLockedFilterCount = 0 then
rPllLockedLcl <= '1';
else
rPllLockedLcl <= '0';
rLockedFilterCount <= rLockedFilterCount - 1;
end if;
else
rLockedFilterCount <= kMaxPllLockCount-1;
rPllLockedLcl <= '0';
end if;
end if;
end if;
end process PllLockFilter;
-- Sticky bit to hold '1' if PLL ever comes unlocked
PllStickyBit: process (ReliableClk)
begin
if rising_edge(ReliableClk) then
if (not rPllReset_n or rClearDataClkUnlockedSticky) = '1' then
rPllUnlockedSticky <= '0';
else
if rPllLockedLcl = '1' and rPllLockedDs(0) = '0' then
rPllUnlockedSticky <= '1';
end if;
end if;
end if;
end process;
rPllLocked <= rPllLockedLcl;
-- AXI transaction decoding
rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED);
rEnableDataClk1x <= rSoftwareControl(kENABLE_DATA_CLK);
rEnableDataClk2x <= rSoftwareControl(kENABLE_DATA_CLK_2X);
rEnableRfdcClk1x <= rSoftwareControl(kENABLE_RF_CLK);
rEnableRfdcClk2x <= rSoftwareControl(kENABLE_RF_CLK_2X);
rSoftwareStatus(kDATA_CLK_PLL_LOCKED) <= rPllLockedLcl;
rSoftwareStatus(kDATA_CLK_PLL_UNLOCKED_STICKY) <= rPllUnlockedSticky;
end STRUCT;
top/x400/rf/x410/x410_rf_reset_controller.vhd
+208
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@@ -0,0 +1,208 @@
--
-- Copyright 2021 Ettus Research, a National Instruments Brand
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: x410_rf_reset_controller
--
-- Description:
--
-- Control RFDC, ADC, and DAC resets.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.PkgRFDC_REGS_REGMAP.all;
entity x410_rf_reset_controller is
port(
-- Clocks
-- Config clock is async to all the others.
ConfigClk : in std_logic;
DataClk : in std_logic;
PllRefClk : in std_logic;
RfClk : in std_logic;
RfClk2x : in std_logic;
DataClk2x : in std_logic;
-- Master resets from the Radio
dAdcResetPulse : in std_logic;
dDacResetPulse : in std_logic;
-- ADC Resets
dAdcDataOutReset_n : out std_logic;
r2AdcFirReset_n : out std_logic;
rAdcRfdcAxiReset_n : out std_logic;
rAdcEnableData : out std_logic;
rAdcGearboxReset_n : out std_logic;
-- DAC Resets
dDacDataInReset_n : out std_logic;
r2DacFirReset_n : out std_logic;
d2DacFirReset_n : out std_logic;
rDacRfdcAxiReset_n : out std_logic;
rDacGearboxReset_n : out std_logic;
-- SW Control and Status
-- Control to initiate resets to RFDC and decimation block including the
-- gearboxes. The reset status is a sticky status of both ADC and DAC.
cSoftwareControl : in std_logic_vector(31 downto 0);
cSoftwareStatus : out std_logic_vector(31 downto 0)
);
end x410_rf_reset_controller;
architecture RTL of x410_rf_reset_controller is
-- POR value for all resets are high.
signal cTriggerAdcReset : std_logic := '1';
signal cTriggerAdcResetDlyd : std_logic := '1';
signal cTriggerDacReset : std_logic := '1';
signal cTriggerDacResetDlyd : std_logic := '1';
signal dTriggerAdcReset_ms : std_logic := '1';
signal dTriggerAdcReset : std_logic := '1';
signal dTriggerDacReset_ms : std_logic := '1';
signal dTriggerDacReset : std_logic := '1';
-- POR value of all reset done signals are set to low.
signal cTriggerAdcResetDone_ms : std_logic := '0';
signal cTriggerAdcResetDone : std_logic := '0';
signal cAdcResetDoneSticky : std_logic := '0';
signal cTriggerDacResetDone_ms : std_logic := '0';
signal cTriggerDacResetDone : std_logic := '0';
signal cDacResetDoneSticky : std_logic := '0';
attribute ASYNC_REG : string;
attribute ASYNC_REG of dTriggerAdcReset : signal is "TRUE";
attribute ASYNC_REG of dTriggerDacReset : signal is "TRUE";
attribute ASYNC_REG of cTriggerAdcResetDone : signal is "TRUE";
attribute ASYNC_REG of cTriggerDacResetDone : signal is "TRUE";
attribute ASYNC_REG of dTriggerAdcReset_ms : signal is "TRUE";
attribute ASYNC_REG of dTriggerDacReset_ms : signal is "TRUE";
attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE";
attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE";
begin
-- rAdcEnableData is set to '1' as we don't control the flow of RX data.
rAdcEnableData <= '1';
cTriggerAdcReset <= cSoftwareControl(kADC_RESET);
cTriggerDacReset <= cSoftwareControl(kDAC_RESET);
cSoftwareStatus <= (
kADC_SEQ_DONE => cAdcResetDoneSticky,
kDAC_SEQ_DONE => cDacResetDoneSticky,
others => '0'
);
-----------------------------------------------------------------------------
-- High-Level Resets Using ConfigClk
-----------------------------------------------------------------------------
-- Pass the master FSM reset around to the other clock domains and then
-- return them back to the ConfigClk domain. This is also a handy way to
-- prove all your clocks are toggling to some extent.
-----------------------------------------------------------------------------
SeqResetDataClk : process(DataClk)
begin
if rising_edge(DataClk) then
-- double-syncs have no sync reset!
dTriggerAdcReset_ms <= cTriggerAdcReset;
dTriggerAdcReset <= dTriggerAdcReset_ms;
dTriggerDacReset_ms <= cTriggerDacReset;
dTriggerDacReset <= dTriggerDacReset_ms;
end if;
end process;
-----------------------------------------------------------------------------
-- Reset Sequence Done Status
-----------------------------------------------------------------------------
-- Now back to ConfigClk! We provide the status for all software controlled
-- resets. We move the signal from ConfigClk to DataClk domain and move it
-- back to ConfigClk domain. This just proves that DataClk is toggling and
-- the reset requested by software is sampled in the DataClk.
-----------------------------------------------------------------------------
SeqResetDone : process(ConfigClk)
begin
if rising_edge(ConfigClk) then
-- double-syncs have no sync reset!
cTriggerAdcResetDone_ms <= dTriggerAdcReset;
cTriggerAdcResetDone <= cTriggerAdcResetDone_ms;
cTriggerDacResetDone_ms <= dTriggerDacReset;
cTriggerDacResetDone <= cTriggerDacResetDone_ms;
end if;
end process;
-- ADC reset done
SwAdcResetDone: process(ConfigClk)
begin
if rising_edge(ConfigClk) then
cTriggerAdcResetDlyd <= cTriggerAdcReset;
-- De-assert reset status on the rising edge of SW ADC reset.
if cTriggerAdcReset = '1' and cTriggerAdcResetDlyd = '0' then
cAdcResetDoneSticky <= '0';
-- Assert and hold the ADC reset status on ADC reset strobe.
elsif cTriggerAdcResetDone = '1' then
cAdcResetDoneSticky <= '1';
end if;
end if;
end process SwAdcResetDone;
-- DAC reset done
SwDacResetDone: process(ConfigClk)
begin
if rising_edge(ConfigClk) then
cTriggerDacResetDlyd <= cTriggerDacReset;
-- De-assert reset status on the rising edge of SW DAC reset.
if cTriggerDacReset = '1' and cTriggerDacResetDlyd = '0' then
cDacResetDoneSticky <= '0';
-- Assert and hold the DAC reset status on DAC reset strobe.
elsif cTriggerDacResetDone = '1' then
cDacResetDoneSticky <= '1';
end if;
end if;
end process SwDacResetDone;
-----------------------------------------------------------------------------
-- rf_reset Instances
-----------------------------------------------------------------------------
AdcResets: entity work.rf_reset (RTL)
port map (
DataClk => DataClk,
PllRefClk => PllRefClk,
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dAdcResetPulse,
dSwReset => dTriggerAdcReset,
dReset_n => dAdcDataOutReset_n,
d2Reset_n => open,
r2Reset_n => r2AdcFirReset_n,
rAxiReset_n => rAdcRfdcAxiReset_n,
rReset_n => rAdcGearboxReset_n
);
DacResets: entity work.rf_reset (RTL)
port map (
DataClk => DataClk,
PllRefClk => PllRefClk,
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dDacResetPulse,
dSwReset => dTriggerDacReset,
dReset_n => dDacDataInReset_n,
d2Reset_n => d2DacFirReset_n,
r2Reset_n => r2DacFirReset_n,
rAxiReset_n => rDacRfdcAxiReset_n,
rReset_n => rDacGearboxReset_n
);
end RTL;
top/x400/tools/get_dts_input.py
Regular → Executable
+2 -2
View File
@@ -41,8 +41,8 @@ def parse_args():
def get_input(target):
# Remove the path from the beginning
dts_input = os.path.basename(target)
# Remove the _XXX and extension from the end of the file name
dts_input = "_".join(dts_input.split("_")[:-1])
# Remove everything after the bandwidth from the end of the file name
dts_input = "_".join(dts_input.split("_")[:4])
# Add path and extension
dts_input = os.path.join('dts', dts_input + '.dts')
return dts_input
top/x400/x410_400_d_rfnoc_image_core.v
+1490
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File diff suppressed because it is too large Load Diff
top/x400/x410_400_d_rfnoc_image_core.vh
+19
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@@ -0,0 +1,19 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x410)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x410_400_d_rfnoc_image_core.yml
//
`define CHDR_WIDTH 128
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x400/x410_400_d_rfnoc_image_core.yml
+125
View File
@@ -0,0 +1,125 @@
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 128 # Bit width of the CHDR bus for this image
device: 'x410' # USRP type
image_core_name: 'x410_400_d' # Name to use for the RFNoC Image Core files
default_target: 'X410_X4_400' # Default make target
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 32768 # Stream endpoint buffer size
ep1:
ctrl: False
data: True
buff_size_bytes: 32768
ep2:
ctrl: False
data: True
buff_size_bytes: 32768
ep3:
ctrl: False
data: True
buff_size_bytes: 32768
ep4:
ctrl: False
data: True
buff_size_bytes: 32768
ep5:
ctrl: False
data: True
buff_size_bytes: 32768
ep6:
ctrl: False
data: True
buff_size_bytes: 32768
ep7:
ctrl: False
data: True
buff_size_bytes: 32768
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
radio1:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 2
NIPC: RADIO_NIPC
replay0:
block_desc: 'replay.yml'
parameters:
NUM_PORTS: 4
MEM_DATA_W: 128
MEM_ADDR_W: 32
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 TX
- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
# RF A:1 TX
- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
# RF A:1 RX
- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
#
# RF B:0 TX
- { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 }
# RF B:0 RX
- { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 }
# RF B:1 TX
- { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 }
# RF B:1 RX
- { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 }
#
# Replay Connections
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
- { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
- { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
- { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
#
# BSP Connections
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device_")
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
top/x400/x410_400_d_static_router.hex
+17
View File
@@ -0,0 +1,17 @@
00000010
00400240
02400040
00800241
02410080
00c00280
028000c0
01000281
02810100
014002c0
02c00140
018002c1
02c10180
01c002c2
02c201c0
020002c3
02c30200
top/x400/x4xx.v
+885 -696
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File diff suppressed because it is too large Load Diff
top/x400/x4xx_core.v
+91 -60
View File
@@ -12,46 +12,50 @@
//
// Parameters:
//
// NUM_DBOARDS : Number of daughter boards
// REG_DWIDTH : Width of the AXI4-Lite data bus (must be 32 or 64)
// REG_AWIDTH : Width of the address bus
// CHDR_CLK_RATE : rfnoc_chdr_clk rate in Hz
// NUM_CHANNELS : Total number of channels
// CHDR_W : CHDR width used by RFNoC
// DMA_W : Width of the DMA port interface
// NET_CHDR_W : CHDR width used by the network interface ports
// ENET_W : Width of the Ethernet buses (each port may have a unique
// width, but all signals have equal width for simplicity).
// ENET_WIDTHS : Actual width of each Ethernet port's interface. This is a
// packed array of 32-bit integers with port 0 in the
// right-most position.
// MTU : Log2 of maximum transmission unit in CHDR_W sized words
// RFNOC_PROTOVER : RFNoC protocol version (major[7:0], minor[7:0])
// RADIO_SPC : Number of samples per radio clock cycle
// RF_BANDWIDTH : RF bandwidth of each radio channel
// NUM_DBOARDS : Number of daughter boards
// REG_DWIDTH : Width of the AXI4-Lite data bus (must be 32 or 64)
// REG_AWIDTH : Width of the address bus
// CHDR_CLK_RATE : rfnoc_chdr_clk rate in Hz
// NUM_CHANNELS : Total number of channels
// NUM_CH_PER_DB : Number of channels per daughterboard and radio core
// CHDR_W : CHDR width used by RFNoC
// DMA_W : Width of the DMA port interface
// NET_CHDR_W : CHDR width used by the network interface ports
// ENET_W : Width of the Ethernet buses (each port may have a unique
// width, but all signals have equal width for simplicity).
// ENET_WIDTHS : Actual width of each Ethernet port's interface. This is
// a packed array of 32-bit integers with port 0 in the
// right-most position.
// MTU : Log2 of maximum transmission unit in CHDR_W sized words
// RFNOC_PROTOVER : RFNoC protocol version (major[7:0], minor[7:0])
// RADIO_SPC : Number of samples per radio clock cycle
// NUM_TIMEKEEPERS : Number of timekeepers
// RF_BANDWIDTH : RF bandwidth of each radio channel
//
module x4xx_core #(
parameter NUM_DBOARDS = 2,
parameter REG_DWIDTH = 32,
parameter REG_AWIDTH = 32,
parameter CHDR_CLK_RATE = 200000000,
parameter NUM_CHANNELS = 4,
parameter CHDR_W = 64,
parameter DMA_W = 64,
parameter NET_CHDR_W = 64,
parameter [ 31:0] ENET_W = 64,
parameter [32*8-1:0] ENET_WIDTHS = {8{ENET_W}},
parameter MTU = $clog2(8192 / (CHDR_W/8)),
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter RADIO_SPC = 1,
parameter RF_BANDWIDTH = 200
parameter NUM_DBOARDS = 2,
parameter REG_DWIDTH = 32,
parameter REG_AWIDTH = 32,
parameter CHDR_CLK_RATE = 200000000,
parameter NUM_CH_PER_DB = 2,
parameter NUM_CHANNELS = NUM_CH_PER_DB*NUM_DBOARDS,
parameter CHDR_W = 64,
parameter DMA_W = 64,
parameter NET_CHDR_W = 64,
parameter [ 31:0] ENET_W = 64,
parameter [32*8-1:0] ENET_WIDTHS = {8{ENET_W}},
parameter MTU = $clog2(8192 / (CHDR_W/8)),
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter RADIO_SPC = 1,
parameter NUM_TIMEKEEPERS = NUM_DBOARDS,
parameter RF_BANDWIDTH = 200
) (
// Clocks and resets
input wire radio_clk,
input wire radio_rst,
input wire radio_clk_2x,
input wire [NUM_DBOARDS-1:0] radio_clk,
input wire [NUM_DBOARDS-1:0] radio_rst,
input wire [NUM_DBOARDS-1:0] radio_clk_2x,
input wire rfnoc_chdr_clk,
input wire rfnoc_chdr_rst,
@@ -116,7 +120,7 @@ module x4xx_core #(
input s_axi_rready,
// PPS and Clock Control
input pps_radioclk,
input [ 1:0] pps_radioclk,
output [ 1:0] pps_select,
output [ 1:0] trig_io_select,
output pll_sync_trigger,
@@ -124,7 +128,8 @@ module x4xx_core #(
input pll_sync_done,
output [ 7:0] pps_brc_delay,
output [25:0] pps_prc_delay,
output [ 1:0] prc_rc_divider,
output [ 1:0] prc_rc0_divider,
output [ 1:0] prc_rc1_divider,
output pps_rc_enabled,
// Radio Data
@@ -189,8 +194,8 @@ module x4xx_core #(
input fpga_aux_ref,
// Radio Control Ports
output wire [63:0] radio_time,
output wire radio_time_stb,
output wire [64*NUM_TIMEKEEPERS-1:0] radio_time,
output wire [ NUM_TIMEKEEPERS-1:0] radio_time_stb,
output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_wr,
output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_rd,
@@ -295,11 +300,13 @@ module x4xx_core #(
wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data;
x4xx_core_common #(
.CHDR_CLK_RATE (CHDR_CLK_RATE),
.CHDR_W (NET_CHDR_W),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NUM_DBOARDS (NUM_DBOARDS),
.PCIE_PRESENT (0)
.CHDR_CLK_RATE (CHDR_CLK_RATE),
.CHDR_W (NET_CHDR_W),
.RFNOC_PROTOVER (RFNOC_PROTOVER),
.NUM_DBOARDS (NUM_DBOARDS),
.NUM_CH_PER_DB (NUM_CH_PER_DB),
.NUM_TIMEKEEPERS (NUM_TIMEKEEPERS),
.PCIE_PRESENT (0)
) x4xx_core_common_i (
.radio_clk (radio_clk),
.radio_clk_2x (radio_clk_2x),
@@ -331,7 +338,8 @@ module x4xx_core #(
.pll_sync_done (pll_sync_done),
.pps_brc_delay (pps_brc_delay),
.pps_prc_delay (pps_prc_delay),
.prc_rc_divider (prc_rc_divider),
.prc_rc0_divider (prc_rc0_divider),
.prc_rc1_divider (prc_rc1_divider),
.pps_rc_enabled (pps_rc_enabled),
.radio_spc (RADIO_SPC),
.radio_time (radio_time),
@@ -548,8 +556,31 @@ module x4xx_core #(
// RFNoC Image Core
//---------------------------------------------------------------------------
// Calculate how may bits wide each channel is
// Calculate how many bits wide each channel is
localparam CHAN_W = 32 * RADIO_SPC;
wire [NUM_CH_PER_DB-1:0] rx_stb0, rx_stb1;
wire [NUM_CH_PER_DB-1:0] tx_stb0, tx_stb1;
wire [NUM_CH_PER_DB-1:0] rx_running0, rx_running1;
wire [NUM_CH_PER_DB-1:0] tx_running0, tx_running1;
wire [CHAN_W*NUM_CH_PER_DB-1:0] rx_data0, rx_data1;
wire [CHAN_W*NUM_CH_PER_DB-1:0] tx_data0, tx_data1;
// Separate out signals to the radio blocks, 1 per dboard, 2 assumed dboards
// [signal name]0 is lower half of a signal, and [signal name]1 is top half
// ex: rx_stb is 1 bit per channel with a width of NUM_CHANNELS
// rx_stb0 is lower half, NUM_CH_PER_DB-1:0
// rx_stb1 is top half, starting at NUM_CH_PER_DB
// Datapaths follow the same pattern but with CHAN_W factored in
// output paths can just concatenate top/bottom half signals
assign rx_stb0 = rx_stb[NUM_CH_PER_DB*0+:NUM_CH_PER_DB];
assign rx_stb1 = rx_stb[NUM_CH_PER_DB*1+:NUM_CH_PER_DB];
assign rx_running = { rx_running1, rx_running0};
assign rx_data0 = rx_data[CHAN_W*NUM_CH_PER_DB*0+:CHAN_W*NUM_CH_PER_DB];
assign rx_data1 = rx_data[CHAN_W*NUM_CH_PER_DB*1+:CHAN_W*NUM_CH_PER_DB];
assign tx_stb0 = tx_stb[NUM_CH_PER_DB*0+:NUM_CH_PER_DB];
assign tx_stb1 = tx_stb[NUM_CH_PER_DB*1+:NUM_CH_PER_DB];
assign tx_running = { tx_running1, tx_running0};
assign tx_data = { tx_data1, tx_data0};
localparam PORT_W = 512; // Set to max value; unused bits will be ignored.
localparam ENET0_W = ENET_WIDTHS[32*0 +: 32];
@@ -574,8 +605,8 @@ module x4xx_core #(
.chdr_aclk (rfnoc_chdr_clk),
.ctrl_aclk (rfnoc_ctrl_clk),
.core_arst (rfnoc_ctrl_rst),
.radio_clk (radio_clk),
.radio_2x_clk (radio_clk_2x),
.radio_clk (radio_clk[0]),
.radio_2x_clk (radio_clk_2x[0]),
.dram_clk (dram_clk),
.device_id (device_id),
.m_ctrlport_radio0_req_wr (ctrlport_radio_req_wr [0* 1+: 1]),
@@ -598,19 +629,19 @@ module x4xx_core #(
.m_ctrlport_radio1_resp_ack (ctrlport_radio_resp_ack [1* 1+: 1]),
.m_ctrlport_radio1_resp_status (ctrlport_radio_resp_status [1* 2+: 2]),
.m_ctrlport_radio1_resp_data (ctrlport_radio_resp_data [1*32+:32]),
.radio_rx_stb_radio1 ({ rx_stb[3], rx_stb[2] }),
.radio_rx_data_radio1 ({ rx_data[3*CHAN_W+:CHAN_W], rx_data[2*CHAN_W+:CHAN_W]}),
.radio_rx_running_radio1 ({rx_running[3], rx_running[2] }),
.radio_tx_stb_radio1 ({ tx_stb[3], tx_stb[2] }),
.radio_tx_data_radio1 ({ tx_data[3*CHAN_W+:CHAN_W], tx_data[2*CHAN_W+:CHAN_W]}),
.radio_tx_running_radio1 ({tx_running[3], tx_running[2] }),
.radio_rx_stb_radio0 ({ rx_stb[1], rx_stb[0] }),
.radio_rx_data_radio0 ({ rx_data[1*CHAN_W+:CHAN_W], rx_data[0*CHAN_W+:CHAN_W]}),
.radio_rx_running_radio0 ({rx_running[1], rx_running[0] }),
.radio_tx_stb_radio0 ({ tx_stb[1], tx_stb[0] }),
.radio_tx_data_radio0 ({ tx_data[1*CHAN_W+:CHAN_W], tx_data[0*CHAN_W+:CHAN_W]}),
.radio_tx_running_radio0 ({tx_running[1], tx_running[0] }),
.radio_time (radio_time),
.radio_rx_stb_radio1 ({ rx_stb1}),
.radio_rx_data_radio1 ({ rx_data1}),
.radio_rx_running_radio1 ({ rx_running1}),
.radio_tx_stb_radio1 ({ tx_stb1}),
.radio_tx_data_radio1 ({ tx_data1}),
.radio_tx_running_radio1 ({ tx_running1}),
.radio_rx_stb_radio0 ({ rx_stb0}),
.radio_rx_data_radio0 ({ rx_data0}),
.radio_rx_running_radio0 ({ rx_running0}),
.radio_tx_stb_radio0 ({ tx_stb0}),
.radio_tx_data_radio0 ({ tx_data0}),
.radio_tx_running_radio0 ({ tx_running0}),
.radio_time (radio_time[0*64+:64]),
.axi_rst (dram_rst),
.m_axi_awid (dram_axi_awid),
.m_axi_awaddr (dram_axi_awaddr),
top/x400/x4xx_core_common.v
+171 -146
View File
@@ -14,32 +14,36 @@
// the ctrlport interfaces in the radios, or a mix of both. A visual
// representation of how the AXI Ctrlport interface and the
// Ctrlport of each radio interact with the different blocks in this module
// can be found in ./doc/x4xx_core_common_buses.svg
// can be found in ./doc/common/x4xx_core_common_buses.svg
//
// Parameters:
//
// CHDR_CLK_RATE : Rate of rfnoc_chdr_clk in Hz
// CHDR_W : CHDR protocol width
// RFNOC_PROTOVER : RFNoC protocol version (major in most-significant byte,
// Minor is least significant byte)
// NUM_DBOARDS : Number of daughter boards to support
// PCIE_PRESENT : Indicates if PCIe is present in this image
// CHDR_CLK_RATE : Rate of rfnoc_chdr_clk in Hz
// CHDR_W : CHDR protocol width
// RFNOC_PROTOVER : RFNoC protocol version (major in most-significant byte,
// Minor is least significant byte)
// NUM_DBOARDS : Number of daughter boards to support
// NUM_CH_PER_DB : Number of RF Channels per daughterboard
// NUM_TIMEKEEPERS : Number of timekeepers
// PCIE_PRESENT : Indicates if PCIe is present in this image
//
`default_nettype none
module x4xx_core_common #(
parameter CHDR_CLK_RATE = 200000000,
parameter CHDR_W = 64,
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter NUM_DBOARDS = 2,
parameter PCIE_PRESENT = 0
parameter CHDR_CLK_RATE = 200000000,
parameter CHDR_W = 64,
parameter RFNOC_PROTOVER = {8'd1, 8'd0},
parameter NUM_DBOARDS = 2,
parameter NUM_CH_PER_DB = 2,
parameter NUM_TIMEKEEPERS = NUM_DBOARDS,
parameter PCIE_PRESENT = 0
) (
// Clocks and resets
input wire radio_clk,
input wire radio_clk_2x,
input wire radio_rst,
input wire [NUM_DBOARDS-1:0] radio_clk,
input wire [NUM_DBOARDS-1:0] radio_clk_2x,
input wire [NUM_DBOARDS-1:0] radio_rst,
input wire rfnoc_chdr_clk,
input wire rfnoc_chdr_rst,
@@ -65,7 +69,7 @@ module x4xx_core_common #(
output wire [31:0] s_ctrlport_resp_data,
// PPS (top-level inputs)
input wire pps_radioclk,
input wire [ 1:0] pps_radioclk,
// PPS and clock control (Domain: rfnoc_ctrl_clk)
output wire [ 1:0] pps_select,
@@ -75,14 +79,15 @@ module x4xx_core_common #(
input wire pll_sync_done,
output wire [ 7:0] pps_brc_delay,
output wire [25:0] pps_prc_delay,
output wire [ 1:0] prc_rc_divider,
output wire [ 1:0] prc_rc0_divider,
output wire [ 1:0] prc_rc1_divider,
output wire pps_rc_enabled,
// Timekeeper (Domain: radio_clk)
input wire [ 7:0] radio_spc,
output wire [63:0] radio_time,
input wire sample_rx_stb,
input wire [ 3:0] time_ignore_bits,
input wire [ 7:0] radio_spc,
input wire sample_rx_stb,
input wire [ 3:0] time_ignore_bits,
output wire [64*NUM_TIMEKEEPERS-1:0] radio_time,
// GPIO to DIO board (Domain: radio_clk)
output wire [11:0] gpio_en_a,
@@ -135,8 +140,8 @@ module x4xx_core_common #(
output wire dac_reset_pulse,
// Radio state for ATR control
input wire [NUM_DBOARDS*2-1:0] tx_running,
input wire [NUM_DBOARDS*2-1:0] rx_running,
input wire [NUM_DBOARDS*NUM_CH_PER_DB-1:0] tx_running,
input wire [NUM_DBOARDS*NUM_CH_PER_DB-1:0] rx_running,
// Misc (Domain: rfnoc_ctrl_clk)
input wire [31:0] qsfp_port_0_0_info,
@@ -177,13 +182,22 @@ module x4xx_core_common #(
wire [CTRLPORT_DATA_W-1:0] m_resp_data;
// Split ctrlport for multiple endpoints (domain: rfnoc_ctrl_clk)
wire timekeeper_req_wr, versioning_req_wr, global_regs_req_wr, dio_req_wr;
wire timekeeper_req_rd, versioning_req_rd, global_regs_req_rd, dio_req_rd;
wire [CTRLPORT_ADDR_W-1:0] timekeeper_req_addr, versioning_req_addr, global_regs_req_addr, dio_req_addr;
wire [CTRLPORT_DATA_W-1:0] timekeeper_req_data, versioning_req_data, global_regs_req_data, dio_req_data;
wire timekeeper_resp_ack, versioning_resp_ack, global_regs_resp_ack, dio_resp_ack;
wire [ CTRLPORT_STS_W-1:0] timekeeper_resp_status, versioning_resp_status, global_regs_resp_status, dio_resp_status;
wire [CTRLPORT_DATA_W-1:0] timekeeper_resp_data, versioning_resp_data, global_regs_resp_data, dio_resp_data;
wire versioning_req_wr, global_regs_req_wr, dio_req_wr;
wire versioning_req_rd, global_regs_req_rd, dio_req_rd;
wire [CTRLPORT_ADDR_W-1:0] versioning_req_addr, global_regs_req_addr, dio_req_addr;
wire [CTRLPORT_DATA_W-1:0] versioning_req_data, global_regs_req_data, dio_req_data;
wire versioning_resp_ack, global_regs_resp_ack, dio_resp_ack;
wire [ CTRLPORT_STS_W-1:0] versioning_resp_status, global_regs_resp_status, dio_resp_status;
wire [CTRLPORT_DATA_W-1:0] versioning_resp_data, global_regs_resp_data, dio_resp_data;
// Timekeeper ctrlports
wire [NUM_TIMEKEEPERS-1:0] timekeeper_req_wr;
wire [NUM_TIMEKEEPERS-1:0] timekeeper_req_rd;
wire [NUM_TIMEKEEPERS*CTRLPORT_ADDR_W-1:0] timekeeper_req_addr;
wire [NUM_TIMEKEEPERS*CTRLPORT_DATA_W-1:0] timekeeper_req_data;
wire [NUM_TIMEKEEPERS-1:0] timekeeper_resp_ack;
wire [NUM_TIMEKEEPERS*CTRLPORT_DATA_W-1:0] timekeeper_resp_data;
wire [NUM_TIMEKEEPERS*CTRLPORT_STS_W-1:0] timekeeper_resp_status;
ctrlport_clk_cross ctrlport_clk_cross_i (
.rst (ctrlport_rst),
@@ -218,7 +232,7 @@ module x4xx_core_common #(
);
ctrlport_splitter #(
.NUM_SLAVES (4)
.NUM_SLAVES (3+NUM_TIMEKEEPERS)
) ctrlport_splitter_i (
.ctrlport_clk (rfnoc_ctrl_clk),
.ctrlport_rst (rfnoc_ctrl_rst),
@@ -249,8 +263,6 @@ module x4xx_core_common #(
// Global Registers
// -------------------------------------------------------------------
localparam NUM_TIMEKEEPERS = 1;
x4xx_global_regs #(
.REG_BASE (GLOBAL_REGS),
.REG_SIZE (GLOBAL_REGS_SIZE),
@@ -278,7 +290,8 @@ module x4xx_core_common #(
.pll_sync_done (pll_sync_done),
.pps_brc_delay (pps_brc_delay),
.pps_prc_delay (pps_prc_delay),
.prc_rc_divider (prc_rc_divider),
.prc_rc0_divider (prc_rc0_divider),
.prc_rc1_divider (prc_rc1_divider),
.pps_rc_enabled (pps_rc_enabled),
.qsfp_port_0_0_info (qsfp_port_0_0_info),
.qsfp_port_0_1_info (qsfp_port_0_1_info),
@@ -319,29 +332,34 @@ module x4xx_core_common #(
// Timekeeper
//---------------------------------------------------------------------------
assign timekeeper_resp_status = CTRL_STS_OKAY;
assign timekeeper_resp_status = {NUM_TIMEKEEPERS{CTRL_STS_OKAY}};
localparam TIMEKEEPERS = {TIMEKEEPER_B[CTRLPORT_ADDR_W-1:0], TIMEKEEPER_A[CTRLPORT_ADDR_W-1:0]};
timekeeper #(
.BASE_ADDR (TIMEKEEPER),
.TIME_INCREMENT (0)
) timekeeper_i (
.tb_clk (radio_clk),
.tb_rst (radio_rst),
.s_ctrlport_clk (rfnoc_ctrl_clk),
.s_ctrlport_req_wr (timekeeper_req_wr),
.s_ctrlport_req_rd (timekeeper_req_rd),
.s_ctrlport_req_addr (timekeeper_req_addr),
.s_ctrlport_req_data (timekeeper_req_data),
.s_ctrlport_resp_ack (timekeeper_resp_ack),
.s_ctrlport_resp_data (timekeeper_resp_data),
.time_increment (radio_spc),
.sample_rx_stb (sample_rx_stb),
.pps (pps_radioclk),
.tb_timestamp (radio_time),
.tb_timestamp_last_pps (),
.tb_period_ns_q32 (),
.tb_changed ()
);
genvar tk_i;
generate
for (tk_i = 0; tk_i < NUM_TIMEKEEPERS; tk_i = tk_i+1) begin : gen_timekeeper
timekeeper #(
.BASE_ADDR (TIMEKEEPERS[CTRLPORT_ADDR_W*tk_i+:CTRLPORT_ADDR_W]),
.TIME_INCREMENT (0)
) timekeeper_i (
.tb_clk (radio_clk[tk_i]),
.tb_rst (radio_rst[tk_i]),
.s_ctrlport_clk (rfnoc_ctrl_clk),
.s_ctrlport_req_wr (timekeeper_req_wr[tk_i]),
.s_ctrlport_req_rd (timekeeper_req_rd[tk_i]),
.s_ctrlport_req_addr (timekeeper_req_addr[CTRLPORT_ADDR_W*tk_i+:CTRLPORT_ADDR_W]),
.s_ctrlport_req_data (timekeeper_req_data[CTRLPORT_DATA_W*tk_i+:CTRLPORT_DATA_W]),
.s_ctrlport_resp_ack (timekeeper_resp_ack[tk_i]),
.s_ctrlport_resp_data (timekeeper_resp_data[CTRLPORT_DATA_W*tk_i+:CTRLPORT_DATA_W]),
.time_increment (radio_spc),
.sample_rx_stb (sample_rx_stb),
.pps (pps_radioclk[tk_i]),
.tb_timestamp (radio_time[64*tk_i+:64]),
.tb_timestamp_last_pps (),
.tb_period_ns_q32 ()
);
end
endgenerate
//-----------------------------------------------------------------------
@@ -389,9 +407,9 @@ module x4xx_core_common #(
wire [NUM_DBOARDS*32-1:0] spi_gpio_out;
wire [NUM_DBOARDS*32-1:0] spi_gpio_ddr;
genvar db;
genvar db_i, ch_i;
generate
for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_radio_ctrlport
for ( db_i = 0; db_i < NUM_DBOARDS; db_i = db_i + 1) begin : gen_radio_ctrlport
//----------------------------------------------------------------------------
// Timed command processing
@@ -408,21 +426,23 @@ module x4xx_core_common #(
ctrlport_timer #(
.EXEC_LATE_CMDS(1)
) ctrlport_timer_i (
.clk (radio_clk),
.rst (radio_rst),
.clk (radio_clk[db_i]),
.rst (radio_rst[db_i]),
`ifdef X410
.time_now (radio_time),
`endif
.time_now_stb (sample_rx_stb),
.time_ignore_bits (time_ignore_bits),
.s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db+: 1]),
.s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db+: 1]),
.s_ctrlport_req_addr (s_radio_ctrlport_req_addr [20*db+:20]),
.s_ctrlport_req_data (s_radio_ctrlport_req_data [32*db+:32]),
.s_ctrlport_req_byte_en (s_radio_ctrlport_req_byte_en [ 4*db+: 4]),
.s_ctrlport_req_has_time (s_radio_ctrlport_req_has_time [ 1*db+: 1]),
.s_ctrlport_req_time (s_radio_ctrlport_req_time [64*db+:64]),
.s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db+: 1]),
.s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db+: 2]),
.s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db+:32]),
.s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db_i+: 1]),
.s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db_i+: 1]),
.s_ctrlport_req_addr (s_radio_ctrlport_req_addr [20*db_i+:20]),
.s_ctrlport_req_data (s_radio_ctrlport_req_data [32*db_i+:32]),
.s_ctrlport_req_byte_en (s_radio_ctrlport_req_byte_en [ 4*db_i+: 4]),
.s_ctrlport_req_has_time (s_radio_ctrlport_req_has_time [ 1*db_i+: 1]),
.s_ctrlport_req_time (s_radio_ctrlport_req_time [64*db_i+:64]),
.s_ctrlport_resp_ack (s_radio_ctrlport_resp_ack [ 1*db_i+: 1]),
.s_ctrlport_resp_status (s_radio_ctrlport_resp_status [ 2*db_i+: 2]),
.s_ctrlport_resp_data (s_radio_ctrlport_resp_data [32*db_i+:32]),
.m_ctrlport_req_wr (ctrlport_timed_req_wr),
.m_ctrlport_req_rd (ctrlport_timed_req_rd),
.m_ctrlport_req_addr (ctrlport_timed_req_addr),
@@ -440,7 +460,7 @@ module x4xx_core_common #(
// This section takes the CtrlPort master from each radio block and splits it
// into a CtrlPort bus for the associated daughter(m_radio_ctrlport_*), the
// RFDC timing control (rf_ctrlport_*), the ATR GPIO control for the DB state
// the current radio(db), the SPI controller of the radio, and DIO main
// the current radio(db_i), the SPI controller of the radio, and DIO main
// control block(x4xx_dio).
// Refer to diagram in the RADIO_CTRLPORT_REGMAP Register map for a
// visual representation on how these interfaces are distributed.
@@ -472,8 +492,8 @@ module x4xx_core_common #(
DB_WINDOW_SIZE_W
})
) ctrlport_decoder_param_i (
.ctrlport_clk ( radio_clk ),
.ctrlport_rst ( radio_rst ),
.ctrlport_clk ( radio_clk[db_i] ),
.ctrlport_rst ( radio_rst[db_i] ),
.s_ctrlport_req_wr ( ctrlport_timed_req_wr),
.s_ctrlport_req_rd ( ctrlport_timed_req_rd),
.s_ctrlport_req_addr ( ctrlport_timed_req_addr),
@@ -484,85 +504,87 @@ module x4xx_core_common #(
.s_ctrlport_resp_ack ( ctrlport_timed_resp_ack),
.s_ctrlport_resp_status ( ctrlport_timed_resp_status),
.s_ctrlport_resp_data ( ctrlport_timed_resp_data),
.m_ctrlport_req_wr ({ gpio_spi_ctrlport_req_wr [ 1*db+: 1],
radio_dio_req_wr [ 1*db+: 1],
gpio_atr_ctrlport_req_wr [ 1*db+: 1],
rf_ctrlport_req_wr [ 1*db+: 1],
m_radio_ctrlport_req_wr [ 1*db+: 1] }),
.m_ctrlport_req_rd ({ gpio_spi_ctrlport_req_rd [ 1*db+: 1],
radio_dio_req_rd [ 1*db+: 1],
gpio_atr_ctrlport_req_rd [ 1*db+: 1],
rf_ctrlport_req_rd [ 1*db+: 1],
m_radio_ctrlport_req_rd [ 1*db+: 1] }),
.m_ctrlport_req_addr ({ gpio_spi_ctrlport_req_addr [20*db+:20],
radio_dio_req_addr [20*db+:20],
gpio_atr_ctrlport_req_addr [20*db+:20],
rf_ctrlport_req_addr [20*db+:20],
m_radio_ctrlport_req_addr [20*db+:20] }),
.m_ctrlport_req_data ({ gpio_spi_ctrlport_req_data [32*db+:32],
radio_dio_req_data [32*db+:32],
gpio_atr_ctrlport_req_data [32*db+:32],
rf_ctrlport_req_data [32*db+:32],
m_radio_ctrlport_req_data [32*db+:32] }),
.m_ctrlport_req_wr ({ gpio_spi_ctrlport_req_wr [ 1*db_i+: 1],
radio_dio_req_wr [ 1*db_i+: 1],
gpio_atr_ctrlport_req_wr [ 1*db_i+: 1],
rf_ctrlport_req_wr [ 1*db_i+: 1],
m_radio_ctrlport_req_wr [ 1*db_i+: 1] }),
.m_ctrlport_req_rd ({ gpio_spi_ctrlport_req_rd [ 1*db_i+: 1],
radio_dio_req_rd [ 1*db_i+: 1],
gpio_atr_ctrlport_req_rd [ 1*db_i+: 1],
rf_ctrlport_req_rd [ 1*db_i+: 1],
m_radio_ctrlport_req_rd [ 1*db_i+: 1] }),
.m_ctrlport_req_addr ({ gpio_spi_ctrlport_req_addr [20*db_i+:20],
radio_dio_req_addr [20*db_i+:20],
gpio_atr_ctrlport_req_addr [20*db_i+:20],
rf_ctrlport_req_addr [20*db_i+:20],
m_radio_ctrlport_req_addr [20*db_i+:20] }),
.m_ctrlport_req_data ({ gpio_spi_ctrlport_req_data [32*db_i+:32],
radio_dio_req_data [32*db_i+:32],
gpio_atr_ctrlport_req_data [32*db_i+:32],
rf_ctrlport_req_data [32*db_i+:32],
m_radio_ctrlport_req_data [32*db_i+:32] }),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack ({ gpio_spi_ctrlport_resp_ack [ 1*db+: 1],
radio_dio_resp_ack [ 1*db+: 1],
gpio_atr_ctrlport_resp_ack [ 1*db+: 1],
rf_ctrlport_resp_ack [ 1*db+: 1],
m_radio_ctrlport_resp_ack [ 1*db+: 1] }),
.m_ctrlport_resp_status ({ gpio_spi_ctrlport_resp_status [ 2*db+: 2],
radio_dio_resp_status [ 2*db+: 2],
gpio_atr_ctrlport_resp_status [ 2*db+: 2],
rf_ctrlport_resp_status [ 2*db+: 2],
m_radio_ctrlport_resp_status [ 2*db+: 2] }),
.m_ctrlport_resp_data ({ gpio_spi_ctrlport_resp_data [32*db+:32],
radio_dio_resp_data [32*db+:32],
gpio_atr_ctrlport_resp_data [32*db+:32],
rf_ctrlport_resp_data [32*db+:32],
m_radio_ctrlport_resp_data [32*db+:32] })
.m_ctrlport_resp_ack ({ gpio_spi_ctrlport_resp_ack [ 1*db_i+: 1],
radio_dio_resp_ack [ 1*db_i+: 1],
gpio_atr_ctrlport_resp_ack [ 1*db_i+: 1],
rf_ctrlport_resp_ack [ 1*db_i+: 1],
m_radio_ctrlport_resp_ack [ 1*db_i+: 1] }),
.m_ctrlport_resp_status ({ gpio_spi_ctrlport_resp_status [ 2*db_i+: 2],
radio_dio_resp_status [ 2*db_i+: 2],
gpio_atr_ctrlport_resp_status [ 2*db_i+: 2],
rf_ctrlport_resp_status [ 2*db_i+: 2],
m_radio_ctrlport_resp_status [ 2*db_i+: 2] }),
.m_ctrlport_resp_data ({ gpio_spi_ctrlport_resp_data [32*db_i+:32],
radio_dio_resp_data [32*db_i+:32],
gpio_atr_ctrlport_resp_data [32*db_i+:32],
rf_ctrlport_resp_data [32*db_i+:32],
m_radio_ctrlport_resp_data [32*db_i+:32] })
);
// Compute ATR state for this radio
wire [ 3:0] db_state;
wire [ 2*NUM_CH_PER_DB-1:0] db_state;
assign db_state = { tx_running[2*db + 1], rx_running[2*db + 1],
tx_running[2*db + 0], rx_running[2*db + 0]};
for ( ch_i = 0; ch_i < NUM_CH_PER_DB; ch_i = ch_i + 1) begin: gen_db_state_ch
assign db_state[ch_i*2] = rx_running[NUM_CH_PER_DB*db_i+ch_i];
assign db_state[ch_i*2+1] = tx_running[NUM_CH_PER_DB*db_i+ch_i];
end
x4xx_gpio_atr #(
.REG_SIZE (RADIO_GPIO_ATR_REGS_SIZE)
) x4xx_gpio_atr_i (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.s_ctrlport_req_wr (gpio_atr_ctrlport_req_wr [ 1*db+: 1]),
.s_ctrlport_req_rd (gpio_atr_ctrlport_req_rd [ 1*db+: 1]),
.s_ctrlport_req_addr (gpio_atr_ctrlport_req_addr [20*db+:20]),
.s_ctrlport_req_data (gpio_atr_ctrlport_req_data [32*db+:32]),
.s_ctrlport_resp_ack (gpio_atr_ctrlport_resp_ack [ 1*db+: 1]),
.s_ctrlport_resp_status (gpio_atr_ctrlport_resp_status [ 2*db+: 2]),
.s_ctrlport_resp_data (gpio_atr_ctrlport_resp_data [32*db+:32]),
.ctrlport_clk (radio_clk[db_i]),
.ctrlport_rst (radio_rst[db_i]),
.s_ctrlport_req_wr (gpio_atr_ctrlport_req_wr [ 1*db_i+: 1]),
.s_ctrlport_req_rd (gpio_atr_ctrlport_req_rd [ 1*db_i+: 1]),
.s_ctrlport_req_addr (gpio_atr_ctrlport_req_addr [20*db_i+:20]),
.s_ctrlport_req_data (gpio_atr_ctrlport_req_data [32*db_i+:32]),
.s_ctrlport_resp_ack (gpio_atr_ctrlport_resp_ack [ 1*db_i+: 1]),
.s_ctrlport_resp_status (gpio_atr_ctrlport_resp_status [ 2*db_i+: 2]),
.s_ctrlport_resp_data (gpio_atr_ctrlport_resp_data [32*db_i+:32]),
.db_state (db_state),
.gpio_in ({4'b0, gpio_in_b, 4'b0, gpio_in_a}),
.gpio_out (atr_gpio_out[db*32+: 32]),
.gpio_ddr (atr_gpio_ddr[db*32+: 32])
.gpio_out (atr_gpio_out[db_i*32+: 32]),
.gpio_ddr (atr_gpio_ddr[db_i*32+: 32])
);
x4xx_gpio_spi #(
.NUM_SLAVES (2)
) x4xx_gpio_spi_i(
.ctrlport_clk (radio_clk),
.ctrlport_clk_2x (radio_clk_2x),
.ctrlport_rst (radio_rst),
.s_ctrlport_req_wr (gpio_spi_ctrlport_req_wr [ 1*db+: 1]),
.s_ctrlport_req_rd (gpio_spi_ctrlport_req_rd [ 1*db+: 1]),
.s_ctrlport_req_addr (gpio_spi_ctrlport_req_addr [20*db+:20]),
.s_ctrlport_req_data (gpio_spi_ctrlport_req_data [32*db+:32]),
.s_ctrlport_resp_ack (gpio_spi_ctrlport_resp_ack [ 1*db+: 1]),
.s_ctrlport_resp_status (gpio_spi_ctrlport_resp_status [ 2*db+: 2]),
.s_ctrlport_resp_data (gpio_spi_ctrlport_resp_data [32*db+:32]),
.gpio_out (spi_gpio_out[db*32+: 32]),
.gpio_ddr (spi_gpio_ddr[db*32+: 32]),
.ctrlport_clk (radio_clk[db_i]),
.ctrlport_clk_2x (radio_clk_2x[db_i]),
.ctrlport_rst (radio_rst[db_i]),
.s_ctrlport_req_wr (gpio_spi_ctrlport_req_wr [ 1*db_i+: 1]),
.s_ctrlport_req_rd (gpio_spi_ctrlport_req_rd [ 1*db_i+: 1]),
.s_ctrlport_req_addr (gpio_spi_ctrlport_req_addr [20*db_i+:20]),
.s_ctrlport_req_data (gpio_spi_ctrlport_req_data [32*db_i+:32]),
.s_ctrlport_resp_ack (gpio_spi_ctrlport_resp_ack [ 1*db_i+: 1]),
.s_ctrlport_resp_status (gpio_spi_ctrlport_resp_status [ 2*db_i+: 2]),
.s_ctrlport_resp_data (gpio_spi_ctrlport_resp_data [32*db_i+:32]),
.gpio_out (spi_gpio_out[db_i*32+: 32]),
.gpio_ddr (spi_gpio_ddr[db_i*32+: 32]),
.gpio_in ({4'b0, gpio_in_b, 4'b0, gpio_in_a})
);
@@ -577,8 +599,8 @@ module x4xx_core_common #(
rfdc_timing_control #(
.NUM_DBOARDS (NUM_DBOARDS)
) rfdc_timing_control_i (
.clk (radio_clk),
.rst (radio_rst),
.clk (radio_clk[0]),
.rst (radio_rst[0]),
.s_ctrlport_req_wr (rf_ctrlport_req_wr),
.s_ctrlport_req_rd (rf_ctrlport_req_rd),
.s_ctrlport_req_addr (rf_ctrlport_req_addr),
@@ -641,7 +663,7 @@ module x4xx_core_common #(
.s_ctrlport_resp_ack (dio_resp_ack),
.s_ctrlport_resp_status (dio_resp_status),
.s_ctrlport_resp_data (dio_resp_data),
.m_ctrlport_clk (radio_clk),
.m_ctrlport_clk (radio_clk[0]),
.m_ctrlport_req_wr (mpm_dio_req_wr),
.m_ctrlport_req_rd (mpm_dio_req_rd),
.m_ctrlport_req_addr (mpm_dio_req_addr),
@@ -680,8 +702,8 @@ module x4xx_core_common #(
.PORT_BASE ({DIO[19:0]}),
.PORT_ADDR_W ({$clog2(DIO_SIZE)})
) ctrlport_decoder_dio_window (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.ctrlport_clk (radio_clk[0]),
.ctrlport_rst (radio_rst[0]),
.s_ctrlport_req_wr (mpm_dio_req_wr),
.s_ctrlport_req_rd (mpm_dio_req_rd),
.s_ctrlport_req_addr (mpm_dio_req_addr),
@@ -721,8 +743,8 @@ module x4xx_core_common #(
.NUM_MASTERS (NUM_DBOARDS + 1),
.PRIORITY (1)
) ctrlport_combiner_dio (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.ctrlport_clk (radio_clk[0]),
.ctrlport_rst (radio_rst[0]),
.s_ctrlport_req_wr ({radio_dio_req_wr, windowed_mpm_dio_req_wr}),
.s_ctrlport_req_rd ({radio_dio_req_rd, windowed_mpm_dio_req_rd}),
.s_ctrlport_req_addr ({radio_dio_req_addr, windowed_mpm_dio_req_addr}),
@@ -755,8 +777,8 @@ module x4xx_core_common #(
.REG_SIZE (DIO_SIZE),
.NUM_DBOARDS (NUM_DBOARDS)
) x4xx_dio_i (
.ctrlport_clk (radio_clk),
.ctrlport_rst (radio_rst),
.ctrlport_clk (radio_clk[0]),
.ctrlport_rst (radio_rst[0]),
.s_ctrlport_req_wr (dio_ctrlport_req_wr),
.s_ctrlport_req_rd (dio_ctrlport_req_rd),
.s_ctrlport_req_addr (dio_ctrlport_req_addr),
@@ -802,7 +824,7 @@ endmodule
// starts at offset 0x80000 in the RFNoC Radio block's register space.
// The following diagram displays the distribution of the CtrlPort
// interface to the different modules it interacts with.
// <img src = "x4xx_core_common_buses.svg"
// <img src = "../common/x4xx_core_common_buses.svg"
// </info>
// <window name="DB_WINDOW" offset="0x00000" size="0x08000">
// <info>Daughterboard GPIO interface. Register access within this space
@@ -829,7 +851,7 @@ endmodule
//
// The following diagram shows how the communication bus interacts with the
// modules in CORE_REGS.
// <img src = "x4xx_core_common_buses.svg"
// <img src = "../common/x4xx_core_common_buses.svg"
// </info>
// <group name="CORE_REGS">
// <window name="GLOBAL_REGS" offset="0x0" size="0xC00" targetregmap="GLOBAL_REGS_REGMAP">
@@ -838,7 +860,10 @@ endmodule
// <window name="VERSIONING_REGS" offset="0xC00" size="0x400" targetregmap="VERSIONING_REGS_REGMAP">
// <info>Window to access versioning registers in the FPGA.</info>
// </window>
// <window name="TIMEKEEPER" offset="0x1000" size="0x20">
// <window name="TIMEKEEPER_A" offset="0x1000" size="0x20">
// <info>Window to access the timekeeper register map.</info>
// </window>
// <window name="TIMEKEEPER_B" offset="0x1100" size="0x20">
// <info>Window to access the timekeeper register map.</info>
// </window>
// <window name="DIO" offset="0x2000" size="0x40" targetregmap="DIO_REGMAP">
top/x400/x4xx_dio.v
+1 -1
View File
@@ -519,7 +519,7 @@ endmodule
// read the GPIO lines as master. The following diagram shows how source
// selection multiplexers are arranged, as well as an indicator for the
// register that control them. </br>
// <img src = "..\..\..\..\..\host\docs\res\x4xx_dio_source_muxes.svg"
// <img src = "..\..\..\..\..\..\host\docs\res\x4xx_dio_source_muxes.svg"
// alt="Front-Panel Programmable GPIOs"/></br>
// Make sure the GPIO lines between FPGA and GPIO board are not driven by
// two drivers. Set the DIO registers in @.PS_CPLD_BASE_REGMAP appropriately.
top/x400/x4xx_dram.v
+1001 -132
View File
File diff suppressed because it is too large Load Diff
top/x400/x4xx_global_regs.v
+20 -10
View File
@@ -55,7 +55,8 @@ module x4xx_global_regs #(
input wire pll_sync_done,
output reg [ 7:0] pps_brc_delay = 8'b0,
output reg [25:0] pps_prc_delay = 26'b0,
output reg [ 1:0] prc_rc_divider = 2'b0,
output reg [ 1:0] prc_rc0_divider = 2'b0,
output reg [ 1:0] prc_rc1_divider = 2'b0,
output reg pps_rc_enabled = 1'b0,
// Misc control and status signals (domain: s_ctrlport_clk)
@@ -77,7 +78,10 @@ module x4xx_global_regs #(
`include "../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/global_regs_regmap_utils.vh"
`include "regmap/versioning_regs_regmap_utils.vh"
// Variant-dependent register map.
`include "regmap/x410/versioning_regs_regmap_utils.vh"
// Make DEVICE_ID default to anything but 0, since that has special meaning
localparam [DEVICE_ID_SIZE-1:0] DEFAULT_DEVICE_ID = 1;
@@ -191,7 +195,8 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin
pps_prc_delay <= s_ctrlport_req_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY];
prc_rc_divider <= s_ctrlport_req_data[PRC_RC_DIVIDER_MSB:PRC_RC_DIVIDER];
prc_rc0_divider <= s_ctrlport_req_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER];
prc_rc1_divider <= s_ctrlport_req_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER];
pps_rc_enabled <= s_ctrlport_req_data[PPS_RC_ENABLED];
end
@@ -272,7 +277,8 @@ module x4xx_global_regs #(
REG_BASE + PPS_CTRL_REG: begin
s_ctrlport_resp_data[PPS_RC_ENABLED] <= pps_rc_enabled;
s_ctrlport_resp_data[PRC_RC_DIVIDER_MSB:PRC_RC_DIVIDER] <= prc_rc_divider;
s_ctrlport_resp_data[PRC_RC0_DIVIDER_MSB:PRC_RC0_DIVIDER] <= prc_rc0_divider;
s_ctrlport_resp_data[PRC_RC1_DIVIDER_MSB:PRC_RC1_DIVIDER] <= prc_rc1_divider;
s_ctrlport_resp_data[PPS_PRC_DELAY_MSB:PPS_PRC_DELAY] <= pps_prc_delay;
end
@@ -576,9 +582,16 @@ endmodule
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC_DIVIDER" range="29..28">
// <bitfield name="PRC_RC1_DIVIDER" range="27..26">
// <info>
// Clock multiplier used to generate radio clock from PLL reference clock.
// Clock multiplier used to generate radio clock 1 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// HDL implementation.
// </info>
// </bitfield>
// <bitfield name="PRC_RC0_DIVIDER" range="29..28">
// <info>
// Clock multiplier used to generate radio clock 0 from PLL reference clock.
// The value written to the register has to be reduced by 2 due to
// HDL implementation.
// </info>
@@ -596,10 +609,7 @@ endmodule
// </register>
// <register name="CHDR_CLK_RATE_REG" offset="0x20" size="32" writable="false">
// <info>Returns the RFNoC bus clock rate (CHDR).</info>
// <bitfield name="CHDR_CLK" range="31..0" initialvalue="CHDR_CLK_VALUE">
// <enumeratedtype name="CHDR_CLK_ENUM" showhex="true">
// <value name="CHDR_CLK_VALUE" integer="200000000"/>
// </enumeratedtype>
// <bitfield name="CHDR_CLK" range="31..0">
// </bitfield>
// </register>
// <register name="CHDR_CLK_COUNT_REG" offset="0x24" size="32" writable="false">
top/x400/x4xx_gpio_atr.v
+9 -7
View File
@@ -14,14 +14,16 @@
//
// Parameters:
//
// REG_BASE : Base address to use for registers.
// REG_SIZE : Register space size.
// WIDTH : Number of GPIO lines controlled by this block.
// REG_BASE : Base address to use for registers.
// REG_SIZE : Register space size.
// WIDTH : Number of GPIO lines controlled by this block.
// NUM_CH_PER_DB : Number of RF Channels per daughterboard
//
module x4xx_gpio_atr #(
parameter REG_BASE = 0,
parameter REG_SIZE = 'h20,
parameter WIDTH = 32
parameter REG_BASE = 0,
parameter REG_SIZE = 'h20,
parameter WIDTH = 32,
parameter NUM_CH_PER_DB = 2
) (
// Slave ctrlport interface
input wire ctrlport_clk,
@@ -34,7 +36,7 @@ module x4xx_gpio_atr #(
output reg [ 1:0] s_ctrlport_resp_status = 2'b00,
output reg [31:0] s_ctrlport_resp_data = {32 {1'bX}},
// Run state signals that indicate tx and rx operation
input wire [3:0] db_state,
input wire [2*NUM_CH_PER_DB-1:0] db_state,
// GPIO control signals
input wire [WIDTH-1:0] gpio_in, //GPIO input state
output reg [WIDTH-1:0] gpio_out = {WIDTH {1'b0}}, //GPIO output state
top/x400/x4xx_gpio_spi.v
+53 -48
View File
@@ -151,14 +151,14 @@ module x4xx_gpio_spi #(
// Assigned to unassigned mapping. This avoids overwriting
// signals with those from uninitialized slaves.
for (slave_i=0; slave_i<4; slave_i=slave_i+1) begin
for ( slave_i = 0; slave_i < 4; slave_i = slave_i + 1 ) begin
sclk_mapping[slave_i] <= 5'h31;
mosi_mapping[slave_i] <= 5'h31;
miso_mapping[slave_i] <= 5'h31;
ss_mapping [slave_i] <= 5'h31;
end
for (slave_i=0; slave_i<NUM_SLAVES; slave_i=slave_i+1) begin
for ( slave_i = 0; slave_i < NUM_SLAVES; slave_i = slave_i + 1) begin
slave_spi_length[slave_i] <= {SPI_LENGTH_SIZE{1'b0}};
end
end else begin
@@ -330,7 +330,7 @@ module x4xx_gpio_spi #(
gpio_is_sclk <= 32'h0;
gpio_is_cs <= 32'h0;
for (slave_i=0; slave_i<NUM_SLAVES; slave_i=slave_i+1) begin
for ( slave_i = 0; slave_i < NUM_SLAVES; slave_i = slave_i + 1) begin
gpio_is_mosi [mosi_mapping[slave_i]] <= 1'b1;
gpio_is_sclk [sclk_mapping[slave_i]] <= 1'b1;
gpio_is_cs [ ss_mapping[slave_i]] <= 1'b1;
@@ -339,56 +339,59 @@ module x4xx_gpio_spi #(
end
end
//---------------------------------------------------------------------------
// SPI master
//---------------------------------------------------------------------------
// Register set_stb for use in 2x domain.
reg set_stb_2x = 1'b0;
reg ctrlport_clk_phase = 1'b1;
`ifdef X410
always @ (posedge ctrlport_clk_2x) begin
if (ctrlport_rst) begin
ctrlport_clk_phase <= 1'b1;
set_stb_2x <= 1'b0;
end else begin
// Assert strobe only during a single 2x cycle of the
// 1x pulse, when 1x clock is low.
set_stb_2x <= ctrlport_clk_phase & set_stb;
ctrlport_clk_phase <= ~ctrlport_clk_phase;
// Register set_stb for use in 2x domain.
reg set_stb_2x = 1'b0;
reg ctrlport_clk_phase = 1'b1;
always @ (posedge ctrlport_clk_2x) begin
if (ctrlport_rst) begin
ctrlport_clk_phase <= 1'b1;
set_stb_2x <= 1'b0;
end else begin
// Assert strobe only during a single 2x cycle of the
// 1x pulse, when 1x clock is low.
set_stb_2x <= ctrlport_clk_phase & set_stb;
ctrlport_clk_phase <= ~ctrlport_clk_phase;
end
end
end
simple_spi_core #(
.BASE (0),
.WIDTH (NUM_SLAVES),
.CLK_IDLE (0),
.SEN_IDLE ({NUM_SLAVES{1'b1}})
) simple_spi_core_i (
.clock (ctrlport_clk_2x),
.reset (ctrlport_rst),
.set_stb (set_stb_2x),
.set_addr (set_addr),
.set_data (set_data),
.readback (readback),
.readback_stb (readback_stb),
.ready (),
.sen (ss[NUM_SLAVES-1:0]),
.sclk (sclk),
.mosi (mosi),
.miso (miso),
.debug ()
);
simple_spi_core #(
.BASE (0),
.WIDTH (NUM_SLAVES),
.CLK_IDLE (0),
.SEN_IDLE ({NUM_SLAVES{1'b1}})
) simple_spi_core_i (
.clock (ctrlport_clk_2x),
.reset (ctrlport_rst),
.set_stb (set_stb_2x),
.set_addr (set_addr),
.set_data (set_data),
.readback (readback),
.readback_stb (readback_stb),
.ready (),
.sen (ss[NUM_SLAVES-1:0]),
.sclk (sclk),
.mosi (mosi),
.miso (miso),
.debug ()
);
// Delay and extend signal for use in 1x domain.
reg readback_stb_dly = 1'b0;
// Delay and extend signal for use in 1x domain.
reg readback_stb_dly = 1'b0;
always @ (posedge ctrlport_clk_2x) begin
readback_stb_dly <= readback_stb;
end
always @ (posedge ctrlport_clk_2x) begin
readback_stb_dly <= readback_stb;
end
assign readback_stb_extended = readback_stb_dly | readback_stb;
assign readback_stb_extended = readback_stb_dly | readback_stb;
`endif
//---------------------------------------------------------------------------
// GPIO Mapping
@@ -420,11 +423,13 @@ module x4xx_gpio_spi #(
assign gated_sclk[i] = gpio_is_sclk[i] ? sclk : 1'b0;
// register signals once remapping logic is resolved
always @ (posedge ctrlport_clk_2x) begin
mosi_mux_out_dlyd[i] <= mosi_mux_out[i];
gpio_is_sclk_dlyd[i] <= gpio_is_sclk[i];
gated_sclk_dlyd[i] <= gated_sclk[i];
end
`ifdef X410
always @ (posedge ctrlport_clk_2x) begin
mosi_mux_out_dlyd[i] <= mosi_mux_out[i];
gpio_is_sclk_dlyd[i] <= gpio_is_sclk[i];
gated_sclk_dlyd[i] <= gated_sclk[i];
end
`endif
// Choose between SCLK and MOSI/SS mux.
glitch_free_mux glitch_free_gpio_out (
top/x400/x4xx_mgt_io_core.sv
+5 -2
View File
@@ -157,8 +157,11 @@ module x4xx_mgt_io_core #(
logic [31:0] mac_status, phy_status;
logic [31:0] mac_status_bclk, phy_status_bclk;
logic activity_bclk, link_up_bclk;
logic [31:0] port_info_bclk;
assign port_info = {COMPAT_NUM, 6'h0, activity_bclk, link_up_bclk, MGT_PROTOCOL, PORTNUM};
// readback on m_axi.clk outside this core
assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM};
assign port_info_bclk = {COMPAT_NUM, 6'h0, activity_bclk, link_up_bclk, MGT_PROTOCOL, PORTNUM};
always @(posedge bus_clk) begin
// No reset handling needed for readback
@@ -166,7 +169,7 @@ module x4xx_mgt_io_core #(
reg_rd_resp <= 1'b1;
case(reg_rd_addr)
REG_PORT_INFO:
reg_rd_data <= port_info;
reg_rd_data <= port_info_bclk;
REG_MAC_CTRL_STATUS:
reg_rd_data <= mac_status_bclk;
REG_PHY_CTRL_STATUS:
top/x400/x4xx_pps_sync.v
+50 -30
View File
@@ -19,20 +19,20 @@
module x4xx_pps_sync #(
parameter SIMULATION = 0
parameter SIMULATION = 0
) (
// clock and reset
input wire base_ref_clk, // BRC
input wire pll_ref_clk, // PRC
input wire ctrl_clk, // CC
input wire radio_clk, // RC
input wire base_ref_clk, // BRC
input wire pll_ref_clk, // PRC
input wire ctrl_clk, // CC
input wire [1:0] radio_clk, // RC
input wire brc_rst,
// PPS
input wire pps_in, // BRC domain
output wire pps_out_brc,
output reg pps_out_rc = 1'b0,
output reg [1:0] pps_out_rc = 2'b00,
// LMK control signal
output reg sync = 1'b0,
@@ -44,7 +44,7 @@ module x4xx_pps_sync #(
output wire pll_sync_done,
input wire [7:0] pps_brc_delay,
input wire [25:0] pps_prc_delay,
input wire [1:0] prc_rc_divider,
input wire [3:0] prc_rc_divider,
input wire pps_rc_enabled,
//signal for debugging
@@ -386,31 +386,51 @@ module x4xx_pps_sync #(
// rc. The divider has to account for the output register and the shift
// register.
wire [1:0] prc_rc_divider_rc;
wire pps_rc_enabled_rc;
synchronizer #(
.FALSE_PATH_TO_IN (1),
.WIDTH (2)
) synchronizer_prc_rc_divider (
.clk (radio_clk),
.rst (1'b0),
.in (prc_rc_divider),
.out (prc_rc_divider_rc)
);
synchronizer #(
.FALSE_PATH_TO_IN (1)
) synchronizer_pps_rc_enabled (
.clk (radio_clk),
.rst (1'b0),
.in (pps_rc_enabled),
.out (pps_rc_enabled_rc)
);
wire [3:0] prc_rc_divider_rc;
wire [1:0] pps_rc_enabled_rc;
wire [1:0] pps_delayed_prc_rc;
reg [7:0] pps_shift_reg_rc = 8'b0;
genvar rc_sync_i;
generate
for (rc_sync_i = 0; rc_sync_i < 2; rc_sync_i = rc_sync_i+1) begin : gen_rc_sync
synchronizer #(
.FALSE_PATH_TO_IN (1),
.WIDTH (2)
) synchronizer_prc_rc_divider (
.clk (radio_clk[rc_sync_i]),
.rst (1'b0),
.in (prc_rc_divider[2*rc_sync_i+:2]),
.out (prc_rc_divider_rc[2*rc_sync_i+:2])
);
synchronizer #(
.FALSE_PATH_TO_IN (1)
) synchronizer_pps_rc_enabled (
.clk (radio_clk[rc_sync_i]),
.rst (1'b0),
.in (pps_rc_enabled),
.out (pps_rc_enabled_rc[rc_sync_i])
);
synchronizer #(
.FALSE_PATH_TO_IN (1)
) synchronizer_pps_rc (
.clk (radio_clk[rc_sync_i]),
.rst (1'b0),
.in (pps_delayed_prc),
.out (pps_delayed_prc_rc[rc_sync_i])
);
end
endgenerate
reg [3:0] pps_shift_reg_rc = 4'b0;
always @(posedge radio_clk) begin
pps_shift_reg_rc <= {pps_shift_reg_rc[2:0], pps_delayed_prc};
always @(posedge radio_clk[0]) begin
pps_shift_reg_rc[3:0] <= {pps_shift_reg_rc[2:0], pps_delayed_prc_rc[0]};
// Restoring a one clock cycle pulse by feeding back to output value.
pps_out_rc <= pps_shift_reg_rc[prc_rc_divider_rc] & ~pps_out_rc & pps_rc_enabled_rc;
pps_out_rc[0] <= pps_shift_reg_rc[prc_rc_divider_rc[1:0]] & ~pps_out_rc[0] & pps_rc_enabled_rc[0];
end
always @(posedge radio_clk[1]) begin
pps_shift_reg_rc[7:4] <= {pps_shift_reg_rc[6:4], pps_delayed_prc_rc[1]};
// Restoring a one clock cycle pulse by feeding back to output value.
pps_out_rc[1] <= pps_shift_reg_rc[prc_rc_divider_rc[3:2]] & ~pps_out_rc[1] & pps_rc_enabled_rc[1];
end
//---------------------------------------------------------------------------
top/x400/x4xx_versioning_regs.v
+5 -1
View File
@@ -68,7 +68,11 @@ module x4xx_versioning_regs #(
input wire [64*96-1:0] version_info
);
`include "regmap/versioning_regs_regmap_utils.vh"
// Variant-dependent register map.
`ifdef X410
`include "regmap/x410/versioning_regs_regmap_utils.vh"
`endif
`include "regmap/versioning_utils.vh"
`include "../../lib/rfnoc/core/ctrlport.vh"