Files
b210-k7-fpga/top/x400/rf/sim/rf_all_tb.sv
T
adf6f576c6 mpm/fpga: x4xx: Major updates in preparation for future devices
FPGA:
- Split up MB registers that control daughterboard specific settings so
  that daughterboards 0 and 1 could have different setings, in
  preparation for future devices that require different settings.
  This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
  block/tile mapping of the individual channels, and information about
  resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
  them to their own headers, so it's trivial to add device-specific
  sections of code instead for other devices in the future.
  - This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
  was unused and possibly broken.
- Move daughterboard-specific code into its own code location
  (dboards/zbx)
- Move X410-specific register documentation to its own location
  (doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
  switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
  timekeeper)

MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
  multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>


Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
2023-05-23 09:06:17 +02:00

58 lines
1.9 KiB
Systemverilog

//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rf_all_tb
//
// Description:
//
// Top-level testbench for X400 RF components. This instantiates all the RF
// testbenches.
//
module rf_all_tb;
`include "test_exec.svh"
import PkgTestExec::*;
tb_adc_gearbox_2x1 tb_adc_gearbox_2x1_i ();
tb_adc_gearbox_2x4 tb_adc_gearbox_2x4_i ();
tb_adc_gearbox_8x4 tb_adc_gearbox_8x4_i ();
tb_capture_sysref tb_capture_sysref_i ();
tb_dac_gearbox_12x8 tb_dac_gearbox_12x8_i ();
tb_dac_gearbox_4x2 tb_dac_gearbox_4x2_i ();
tb_dac_gearbox_6x12 tb_dac_gearbox_6x12_i ();
tb_ddc_400m_saturate tb_ddc_400m_saturate_i ();
tb_duc_400m_saturate tb_duc_400m_saturate_i ();
tb_rf_nco_reset tb_rf_nco_reset_i ();
tb_x410_rf_reset_controller tb_x410_rf_reset_controller_i ();
initial begin
test.start_tb("rf_all_tb", 1ms);
test.start_test("Run RF TBs");
forever begin
#100ns;
if (
tb_adc_gearbox_2x1_i.StopSim &&
tb_adc_gearbox_2x4_i.StopSim &&
tb_adc_gearbox_8x4_i.StopSim &&
tb_capture_sysref_i.StopSim &&
tb_dac_gearbox_12x8_i.StopSim &&
tb_dac_gearbox_4x2_i.StopSim &&
tb_dac_gearbox_6x12_i.StopSim &&
tb_ddc_400m_saturate_i.StopSim &&
tb_duc_400m_saturate_i.StopSim &&
tb_rf_nco_reset_i.StopSim &&
tb_x410_rf_reset_controller_i.StopSim
) break;
end
test.end_test();
// If they all stop before the timeout, and there are no errors, then we
// assume everything passed.
test.end_tb();
end
endmodule : rf_all_tb