From adf6f576c67d8d40f1d0efec6b8b1384d8907307 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Mon, 15 May 2023 14:51:43 +0200 Subject: [PATCH] mpm/fpga: x4xx: Major updates in preparation for future devices FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife Co-authored-by: Ryan Marlow Co-authored-by: Martin Braun Co-authored-by: Humberto Jimenez Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223 --- tools/make/viv_ip_builder.mak | 36 + tools/scripts/viv_ip_retarget_subcores.py | 165 + top/x400/Makefile | 103 +- top/x400/Makefile.x4xx.inc | 41 +- top/x400/constraints/pins/common.xdc | 48 - top/x400/constraints/pins/x410/db_gpio.xdc | 59 + top/x400/constraints/timing/common.xdc | 130 - top/x400/constraints/timing/x410.xdc | 141 + top/x400/constraints/timing/x410_clocks.xdc | 18 + .../regmap/x440/constants_regmap_utils.vh | 28 + .../regmap/x440/led_setup_regmap_utils.vh | 63 + .../regmap/x440/mb_cpld_pl_regmap_utils.vh | 36 + top/x400/cpld_interface.v | 202 +- top/x400/cpld_interface_regs.v | 6 +- .../dboards/ctrlport_clk_crossing_derived.v | 130 + .../dboards/zbx/cpld/quartus/zbx_top_cpld.qsf | 8 +- top/x400/dboards/zbx/db_gpio_interface.v | 214 + top/x400/doc/X410/X410_FPGA.htm | 10 + top/x400/doc/X410/X410_FPGA_left.htm | 743 + top/x400/doc/X410/X410_FPGA_right.htm | 25951 ++++++++++++++++ top/x400/ip/Makefile.inc | 68 +- .../ip/axi_inter_1x512_512_bd/Makefile.inc | 32 + .../axi_inter_1x512_512_bd.tcl | 314 + .../ip/axi_inter_2x512_512_bd/Makefile.inc | 32 + .../axi_inter_2x512_512_bd.tcl | 380 + .../ip/axi_inter_4x128_512_bd/Makefile.inc | 32 + .../axi_inter_4x128_512_bd.tcl | 823 + .../common/regmap/common_regs.v | 509 + .../x4xx_ps_rfdc_bd/common/regmap/uhd_regs.v | 336 + .../x410_ps_rfdc_bd/Makefile.inc | 52 + .../x410_ps_rfdc_bd/hdl_sources.tcl | 14 + .../x410_ps_rfdc_bd/regmap/x410_rfdc_regs.v | 224 + .../synthstub/x410_ps_rfdc_bd.vhd | 411 + .../x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl | 3825 +++ top/x400/ip/xge_pcs_pma/Makefile.inc | 2 +- top/x400/ipass_present_controller.v | 2 +- top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd | 663 - top/x400/regmap/core_regs_regmap_utils.vh | 15 +- .../regmap/cpld_interface_regmap_utils.vh | 2 +- top/x400/regmap/dig_ifc_regmap_utils.vh | 2 +- top/x400/regmap/dio_regmap_utils.vh | 2 +- top/x400/regmap/global_regs_regmap_utils.vh | 13 +- top/x400/regmap/gpio_atr_regmap_utils.vh | 2 +- top/x400/regmap/pl_cpld_regmap_utils.vh | 2 +- .../regmap/radio_ctrlport_regmap_utils.vh | 2 +- top/x400/regmap/radio_dio_regmap_utils.vh | 2 +- top/x400/regmap/rfdc_timing_regmap_utils.vh | 2 +- top/x400/regmap/x410/PkgRFDC_REGS_REGMAP.vhd | 1004 + .../regmap/x410/rfdc_regs_regmap_utils.vh | 466 + .../x410/versioning_regs_regmap_utils.vh | 153 + top/x400/rf/100m/rf_core_100m.v | 13 +- top/x400/rf/200m/rf_core_200m.v | 16 +- top/x400/rf/400m/rf_core_400m.v | 13 +- top/x400/rf/common/Makefile.srcs | 7 +- top/x400/rf/common/capture_sysref.v | 15 +- top/x400/rf/common/gpio_to_axis_mux.vhd | 107 +- top/x400/rf/common/rf_nco_reset.vhd | 21 +- top/x400/rf/sim/Makefile | 27 +- top/x400/rf/sim/rf_all_tb.sv | 44 +- top/x400/rf/sim/tb_rf_nco_reset.vhd | 12 + ...er.vhd => tb_x410_rf_reset_controller.vhd} | 14 +- top/x400/rf/x410/x410_clock_gates.vhd | 300 + top/x400/rf/x410/x410_rf_reset_controller.vhd | 208 + top/x400/tools/get_dts_input.py | 4 +- top/x400/x410_400_d_rfnoc_image_core.v | 1490 + top/x400/x410_400_d_rfnoc_image_core.vh | 19 + top/x400/x410_400_d_rfnoc_image_core.yml | 125 + top/x400/x410_400_d_static_router.hex | 17 + top/x400/x4xx.v | 1581 +- top/x400/x4xx_core.v | 151 +- top/x400/x4xx_core_common.v | 317 +- top/x400/x4xx_dio.v | 2 +- top/x400/x4xx_dram.v | 1133 +- top/x400/x4xx_global_regs.v | 30 +- top/x400/x4xx_gpio_atr.v | 16 +- top/x400/x4xx_gpio_spi.v | 101 +- top/x400/x4xx_mgt_io_core.sv | 7 +- top/x400/x4xx_pps_sync.v | 80 +- top/x400/x4xx_versioning_regs.v | 6 +- 79 files changed, 41079 insertions(+), 2315 deletions(-) create mode 100644 tools/scripts/viv_ip_retarget_subcores.py create mode 100644 top/x400/constraints/pins/x410/db_gpio.xdc create mode 100644 top/x400/constraints/timing/x410.xdc create mode 100644 top/x400/constraints/timing/x410_clocks.xdc create mode 100644 top/x400/cpld/regmap/x440/constants_regmap_utils.vh create mode 100644 top/x400/cpld/regmap/x440/led_setup_regmap_utils.vh create mode 100644 top/x400/cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh create mode 100644 top/x400/dboards/ctrlport_clk_crossing_derived.v create mode 100644 top/x400/dboards/zbx/db_gpio_interface.v create mode 100644 top/x400/doc/X410/X410_FPGA.htm create mode 100644 top/x400/doc/X410/X410_FPGA_left.htm create mode 100644 top/x400/doc/X410/X410_FPGA_right.htm create mode 100644 top/x400/ip/axi_inter_1x512_512_bd/Makefile.inc create mode 100644 top/x400/ip/axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.tcl create mode 100644 top/x400/ip/axi_inter_2x512_512_bd/Makefile.inc create mode 100644 top/x400/ip/axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.tcl create mode 100644 top/x400/ip/axi_inter_4x128_512_bd/Makefile.inc create mode 100644 top/x400/ip/axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.tcl create mode 100644 top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v create mode 100644 top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/uhd_regs.v create mode 100644 top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc create mode 100644 top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/hdl_sources.tcl create mode 100644 top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap/x410_rfdc_regs.v create mode 100644 top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/synthstub/x410_ps_rfdc_bd.vhd create mode 100644 top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl delete mode 100644 top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd create mode 100644 top/x400/regmap/x410/PkgRFDC_REGS_REGMAP.vhd create mode 100644 top/x400/regmap/x410/rfdc_regs_regmap_utils.vh create mode 100644 top/x400/regmap/x410/versioning_regs_regmap_utils.vh rename top/x400/rf/sim/{tb_rf_reset_controller.vhd => tb_x410_rf_reset_controller.vhd} (98%) create mode 100644 top/x400/rf/x410/x410_clock_gates.vhd create mode 100644 top/x400/rf/x410/x410_rf_reset_controller.vhd mode change 100644 => 100755 top/x400/tools/get_dts_input.py create mode 100644 top/x400/x410_400_d_rfnoc_image_core.v create mode 100644 top/x400/x410_400_d_rfnoc_image_core.vh create mode 100644 top/x400/x410_400_d_rfnoc_image_core.yml create mode 100644 top/x400/x410_400_d_static_router.hex diff --git a/tools/make/viv_ip_builder.mak b/tools/make/viv_ip_builder.mak index ddc24c7..26e843c 100644 --- a/tools/make/viv_ip_builder.mak +++ b/tools/make/viv_ip_builder.mak @@ -42,6 +42,42 @@ BUILD_VIVADO_IP = \ $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \ exit $$VIV_ERR +# ------------------------------------------------------------------- +# Usage: BUILD_VIVADO_IP_WITH_SUBCORES +# Args: $1 = IP_NAME (IP name) +# $2 = ARCH (zynq, kintex7, etc) +# $3 = PART_ID (//[/[/]]) +# $4 = IP_SRC_DIR (Absolute path to the top level ip src dir) +# $5 = IP_BUILD_DIR (Absolute path to the top level ip build dir) +# $6 = GENERATE_EXAMPLE (0 or 1) +# Prereqs: +# - TOOLS_DIR must be defined globally +# ------------------------------------------------------------------- + +BUILD_VIVADO_IP_WITH_SUBCORES = \ + @ \ + echo "========================================================"; \ + echo "BUILDER: Building IP $(1)"; \ + echo "========================================================"; \ + export XCI_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).xci); \ + export PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ + export GEN_EXAMPLE=$(6); \ + export SYNTH_IP=$(SYNTH_IP); \ + echo "BUILDER: Staging IP in build directory..."; \ + rm -rf $(5)/$(1); \ + mkdir -p $(5)/$(1); \ + $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \ + cp -rf $(4)/$(1)/* $(5)/$(1); \ + echo "BUILDER: Retargeting IP to part $(2)/$(3)..."; \ + python3 $(TOOLS_DIR)/scripts/viv_ip_xci_editor.py --output_dir=$(5)/$(1) --target=$(2)/$(3) retarget $(4)/$(1)/$(1).xci; \ + python3 $(TOOLS_DIR)/scripts/viv_ip_retarget_subcores.py --output_dir=$(5)/$(1) --target=$(2)/$(3) $(4)/$(1)/$(1).xci; \ + cd $(5); \ + echo "BUILDER: Building IP..."; \ + export VIV_ERR=0; \ + $(TOOLS_DIR)/scripts/launch_vivado.py -mode batch -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_generate_ip.tcl) -log $(1).log -nojournal || export VIV_ERR=$$?; \ + $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \ + exit $$VIV_ERR + # ------------------------------------------------------------------- # Usage: REBUILD_VIVADO_IP_WITH_PATCH # Args: $1 = IP_NAME (IP name) diff --git a/tools/scripts/viv_ip_retarget_subcores.py b/tools/scripts/viv_ip_retarget_subcores.py new file mode 100644 index 0000000..27bfba9 --- /dev/null +++ b/tools/scripts/viv_ip_retarget_subcores.py @@ -0,0 +1,165 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: GPL-3.0-or-later +# + +""" Vivado IP sub-core re-targeting. + + Script to update the sub-cores in a directory to a specific + part number +""" + +import argparse +import os +import re +import sys + +# Parse command line options +def get_options(): + """Parse script arguments.""" + parser = argparse.ArgumentParser( + description="Utility script to modify subcores for a Xilinx IP XCI file" + ) + parser.add_argument( + "xci_filepath", type=str, default=None, help="Name for the IP core" + ) + parser.add_argument( + "--target", + type=str, + default=None, + help="Input value for target. Must be of the form ////", + ) + parser.add_argument( + "--name", type=str, default=None, help="Input value for new IP name" + ) + parser.add_argument( + "--output_dir", type=str, default=".", help="Build directory for IP" + ) + args = parser.parse_args() + if not args.xci_filepath: + print("ERROR: Please specify the location for the XCI file to operate on\n") + parser.print_help() + sys.exit(1) + if not os.path.isfile(args.xci_filepath): + print( + "ERROR: XCI File " + + args.xci_filepath + + " could not be accessed or is not a file.\n" + ) + parser.print_help() + sys.exit(1) + return args + + +def get_match_str(item): + """Produce the string to an XML parameter with a value.""" + return ( + '(.*\)(.+)(\)' + ) + + +def get_empty_match_str(item): + """Produce the string to an XML parameter without a value.""" + return ( + '(.*\' + ) + + +def retarget_subcore(path, file, output_dir, target_tok): + """Update target parameter for the specified sub-core.""" + # Read XCI File + with open(os.path.join(path, file)) as in_file: + xci_lines = in_file.readlines() + + replace_dict = { + "ARCHITECTURE": target_tok[0], + "DEVICE": target_tok[1], + "PACKAGE": target_tok[2], + "SPEEDGRADE": target_tok[3], + "C_XDEVICEFAMILY": target_tok[0], + "C_FAMILY": target_tok[0], + "C_XDEVICE": target_tok[1], + } + if len(target_tok) > 4: + replace_dict["TEMPERATURE_GRADE"] = target_tok[4] + if len(target_tok) > 5: + replace_dict["SILICON_REVISION"] = target_tok[5] + out_xci_filename = os.path.join(os.path.abspath(output_dir), os.path.basename(file)) + + # Write files with modified parameters + with open(out_xci_filename, "w") as out_file: + for r_line in xci_lines: + w_line = r_line + m = re.search( + get_match_str("(" + "|".join(list(replace_dict.keys())) + ")"), r_line + ) + if m is not None: + w_line = m.group(1) + replace_dict[m.group(2)] + m.group(4) + "\n" + else: + m = re.search( + get_empty_match_str( + "(" + "|".join(list(replace_dict.keys())) + ")" + ), + r_line, + ) + if m is not None: + w_line = ( + m.group(1) + + ">" + + replace_dict[m.group(2)] + + "\n" + ) + out_file.write(w_line) + + +def main(): + """Perform directory traversal to detect and update sub-cores.""" + args = get_options() + + # Validate arguments + if not os.path.isdir(args.output_dir): + print( + "ERROR: IP Build directory " + + args.output_dir + + " could not be accessed or is not a directory." + ) + sys.exit(1) + if not args.target: + print("ERROR: No target specified.") + sys.exit(1) + target_tok = args.target.split("/") + if len(target_tok) < 4: + print( + "ERROR: Invalid target format. Must be /////" + ) + sys.exit(1) + + sub_cores = [] + + # Detect sub-cores + ip_dir, ip_name = os.path.split(args.xci_filepath) + for path, _, files in os.walk(ip_dir): + for name in files: + if name.endswith("xci"): + sub_cores.append(os.path.join(path, name)) + + # Get the relative path for each IP core detected + relative_paths = [os.path.relpath(path, ip_dir) for path in sub_cores] + + # Remove main core + relative_paths.remove(ip_name) + + for rp in relative_paths: + retarget_subcore( + os.path.join(ip_dir, os.path.split(rp)[0]), + os.path.split(rp)[1], + os.path.join(args.output_dir, os.path.split(rp)[0]), + target_tok, + ) + + +if __name__ == "__main__": + main() diff --git a/top/x400/Makefile b/top/x400/Makefile index 0fe6da4..00a52fa 100644 --- a/top/x400/Makefile +++ b/top/x400/Makefile @@ -42,26 +42,26 @@ QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10Gb QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled) # Target specific variables -X410_IP: DEFS += $(QSFP0_10GBE) RFBW_100M=1 -X410_X1_100: DEFS += $(QSFP0_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_X4_100: DEFS += $(QSFP0_4X10GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=0 -X410_C1_100: DEFS += $(QSFP0_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_UC_100: DEFS += $(QSFP1_100GBE) RFBW_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_C1_200: DEFS += $(QSFP0_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_UC_200: DEFS += $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_X1_200: DEFS += $(QSFP0_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_X4_200: DEFS += $(QSFP0_4X10GBE) RFBW_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 -X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 DRAM_CH=0 -X410_X1_400: DEFS += $(QSFP0_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128 -X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128 -X410_X4_400: DEFS += $(QSFP0_4X10GBE) RFBW_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128 -X410_C1_400: DEFS += $(QSFP0_100GBE) RFBW_400M=1 DRAM_CH=0 -X410_UC_400: DEFS += $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0 -X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 DRAM_CH=0 +X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100 +X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=0 +X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=4*$(DRAM) DRAM_W=64 +X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_CH=0 +X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128 +X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128 +X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=4*$(DRAM) DRAM_W=128 +X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 +X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 +X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 # DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to # exclude it. Note that some targets exclude it regardless of this setting. @@ -78,8 +78,7 @@ X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex) X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex) X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex) -X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex) - +X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex) # Option to stop after RTL elaboration. Use this flag as a synthesis check. ifndef TARGET @@ -112,27 +111,27 @@ endif ## ##Available Targets -##-------------|-----------|-----------------|-----------------|------------ -##Target | Bandwidth | QSFP0 | QSFP1 | DRAM -##-------------|-----------|-----------------|-----------------|------------ -##X410_X1_100 | 100 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch -##X410_XG_100 | 100 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch -##X410_X4_100 | 100 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch -##X410_X4C_100 | 100 MHz | 4 x 10 GbE | 100 GbE | Unused -##X410_C1_100 | 100 MHz | 100 GbE | Unused | 64b x 4 Ch -##X410_UC_100 | 100 MHz | Unused | 100 GbE | 64b x 4 Ch -##X410_X1_200 | 200 MHz | 10 GbE (Lane 0) | Unused | 64b x 4 Ch -##X410_XG_200 | 200 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch -##X410_X4_200 | 200 MHz | 4 x 10 GbE | Unused | 64b x 4 Ch -##X410_X4C_200 | 200 MHz | 4 x 10 GbE | 100 GbE | Unused -##X410_C1_200 | 200 MHz | 100 GbE | Unused | 64b x 4 Ch -##X410_UC_200 | 200 MHz | Unused | 100 GbE | 64b x 4 Ch -##X410_X1_400 | 400 MHz | 10 GbE (Lane 0) | Unused | 128b x 4 Ch -##X410_XG_400 | 400 MHz | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch -##X410_X4_400 | 400 MHz | 4 x 10 GbE | Unused | 128b x 4 Ch -##X410_C1_400 | 400 MHz | 100 GbE | Unused | Unused -##X410_UC_400 | 400 MHz | Unused | 100 GbE | Unused -##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | Unused +##-------------|-----------|----|-----------------|-----------------|------------ +##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM +##-------------|-----------|----|-----------------|-----------------|------------ +##X410_X1_100 | 100 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch +##X410_XG_100 | 100 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch +##X410_X4_100 | 100 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch +##X410_X4C_100 | 100 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused +##X410_C1_100 | 100 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch +##X410_UC_100 | 100 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch +##X410_X1_200 | 200 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch +##X410_XG_200 | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch +##X410_X4_200 | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch +##X410_X4C_200 | 200 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused +##X410_C1_200 | 200 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch +##X410_UC_200 | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch +##X410_X1_400 | 400 MHz | 4 | 10 GbE (Lane 0) | Unused | 128b x 4 Ch +##X410_XG_400 | 400 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch +##X410_X4_400 | 400 MHz | 4 | 4 x 10 GbE | Unused | 128b x 4 Ch +##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused +##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused +##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused ##* Note: Not all targets are shipped with UHD. ##* Note: Some YAML configurations might not use all available DRAM channels. @@ -185,15 +184,15 @@ X410_UC_200: X410_IP build/usrp_x410_fpga_UC_200.dts $(call post_build,X410,UC_200) X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts - $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS)) + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS)) $(call post_build,X410,X1_400) X410_XG_400: X410_IP build/usrp_x410_fpga_XG_400.dts - $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS)) + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS)) $(call post_build,X410,XG_400) X410_X4_400: X410_IP build/usrp_x410_fpga_X4_400.dts - $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS)) + $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS)) $(call post_build,X410,X4_400) X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts @@ -210,10 +209,10 @@ X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts ## ##Experimental Targets -##-------------|-----------|-----------------|-----------------|------------ -##Target | Bandwidth | QSFP0 | QSFP1 | DRAM -##-------------|-----------|-----------------|-----------------|------------ -##X410_CG_200 | 200 | 100 GbE | 100 GbE | 64b x 4 Ch +##-------------|-----------|----|-----------------|-----------------|------------ +##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM +##-------------|-----------|----|-----------------|-----------------|------------ +##X410_CG_200 | 200 | 4 | 100 GbE | 100 GbE | 64b x 4 Ch X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS)) @@ -230,10 +229,10 @@ all: X410_X4_200 X410_CG_400 X410_UC_200 ##(Default targets) X410_IP: ##Build IP only. +$(call vivado_ip,X410,$(DEFS) X410=1) -build/%.dts: dts/*.dts dts/*.dtsi +build/usrp_x410%.dts: dts/*.dts dts/*.dtsi -mkdir -p build tools/parse_versions_for_dts.py \ - --input regmap/versioning_regs_regmap_utils.vh \ + --input regmap/x410/versioning_regs_regmap_utils.vh \ --output dts/x410-version-info.dtsi \ --components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m ${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \ diff --git a/top/x400/Makefile.x4xx.inc b/top/x400/Makefile.x4xx.inc index ad4667c..69ac999 100644 --- a/top/x400/Makefile.x4xx.inc +++ b/top/x400/Makefile.x4xx.inc @@ -35,6 +35,7 @@ include $(LIB_DIR)/dsp/Makefile.srcs include $(LIB_DIR)/ip/Makefile.inc include $(LIB_DIR)/rfnoc/Makefile.srcs include $(LIB_DIR)/wb_spi/Makefile.srcs +include $(LIB_DIR)/wishbone/Makefile.srcs include $(LIB_DIR)/axi4_sv/Makefile.srcs include $(LIB_DIR)/axi4s_sv/Makefile.srcs include $(LIB_DIR)/axi4lite_sv/Makefile.srcs @@ -62,10 +63,7 @@ EDGE_FILE ?= $(DEFAULT_EDGE_FILE) ################################################## # Sources ################################################## -TOP_SRCS = - -ifdef X410 -TOP_SRCS += \ +TOP_SRCS = \ x4xx.v \ x4xx_qsfp_wrapper_temp.sv \ x4xx_qsfp_wrapper.sv \ @@ -78,12 +76,6 @@ x4xx_dio.v \ x4xx_gpio_atr.v \ x4xx_gpio_spi.v \ x4xx_dram.v \ -rf/100m/rf_core_100m.v \ -rf/200m/rf_core_200m.v \ -rf/200m/rf_down_4to2.v \ -rf/200m/rf_up_2to4.v \ -rf/400m/rf_core_400m.v \ -rf/common/rf_reset_controller.vhd \ ctrlport_spi_master.v \ cpld_interface.v \ cpld_interface_regs.v \ @@ -92,20 +84,41 @@ rfdc_timing_control.v \ x4xx_pps_sync.v \ ../../lib/timing/pps_generator.v \ dboards/ctrlport_byte_serializer.v \ -dboards/db_gpio_interface.v \ +dboards/ctrlport_clk_crossing_derived.v \ dboards/db_gpio_reordering.v \ ipass_present_controller.v \ $(IMAGE_CORE) + +ifdef X410 +TOP_SRCS += \ +rf/100m/rf_core_100m.v \ +rf/200m/rf_core_200m.v \ +rf/200m/rf_down_4to2.v \ +rf/200m/rf_up_2to4.v \ +rf/400m/rf_core_400m.v \ +rf/x410/x410_rf_reset_controller.vhd \ +dboards/zbx/db_gpio_interface.v endif -MB_XDC = \ +ifdef X410 +MB_XDC += \ +constraints/timing/x410_clocks.xdc +endif + +MB_XDC += \ constraints/pins/common.xdc \ -constraints/pins/rfdc_2x2.xdc \ constraints/timing/shared_constants.sdc \ constraints/timing/common.xdc \ constraints/pins/dram.xdc \ constraints/timing/dram.xdc +ifdef X410 +MB_XDC += \ +constraints/pins/rfdc_2x2.xdc \ +constraints/pins/x410/db_gpio.xdc \ +constraints/timing/x410.xdc +endif + # Definitions # MGT Types from x4xx_mgt_type.vh MGT_100GbE = 5 @@ -145,9 +158,7 @@ ifneq (,$(findstring QSFP1_3,$(EXTRA_DEFS))) MB_XDC += constraints/pins/qsfp1_3.xdc endif -ifdef X410 DESIGN_SRCS = $(abspath $(MB_XDC)) -endif # The XDC files must be read in a specific order, motherboard first and then daughterboard. # Outside of that, all the other sources can be read in any order desired. diff --git a/top/x400/constraints/pins/common.xdc b/top/x400/constraints/pins/common.xdc index 92b0957..518cb25 100644 --- a/top/x400/constraints/pins/common.xdc +++ b/top/x400/constraints/pins/common.xdc @@ -60,57 +60,9 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports {FABRIC_CLK_OUT_*}] # Pin constraints for the other PL pins (1.8 V) ############################################################################### -set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}] -set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}] -set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}] -set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}] -set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}] -set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}] -set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}] -set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}] -set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}] -set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}] -set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}] -set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}] -set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}] -set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}] -set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}] -set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}] -set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}] -set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}] -set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}] -set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}] -set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}] -set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}] -set_property IOB TRUE [get_ports {DB1_GPIO[*]}] - set_property PACKAGE_PIN A7 [get_ports {DB1_SYNTH_SYNC}] set_property IOSTANDARD LVCMOS18 [get_ports {DB1_SYNTH_SYNC}] -set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}] -set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}] -set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}] -set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}] -set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}] -set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}] -set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}] -set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}] -set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}] -set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}] -set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}] -set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}] -set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}] -set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}] -set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}] -set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}] -set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}] -set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}] -set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}] -set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}] -set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}] -set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}] -set_property IOB TRUE [get_ports {DB0_GPIO[*]}] - set_property PACKAGE_PIN AP5 [get_ports {DB0_SYNTH_SYNC}] set_property IOSTANDARD LVCMOS18 [get_ports {DB0_SYNTH_SYNC}] diff --git a/top/x400/constraints/pins/x410/db_gpio.xdc b/top/x400/constraints/pins/x410/db_gpio.xdc new file mode 100644 index 0000000..5128dac --- /dev/null +++ b/top/x400/constraints/pins/x410/db_gpio.xdc @@ -0,0 +1,59 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# DB GPIO pin constraints for X410. +# + +############################################################################### +# Pin constraints for the other PL pins (1.8 V) +############################################################################### +set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}] +set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}] +set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}] +set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}] +set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}] +set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}] +set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}] +set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}] +set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}] +set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}] +set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}] +set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}] +set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}] +set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}] +set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}] +set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}] +set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}] +set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}] +set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}] +set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}] +set_property IOB TRUE [get_ports {DB1_GPIO[*]}] + +set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}] +set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}] +set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}] +set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}] +set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}] +set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}] +set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}] +set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}] +set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}] +set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}] +set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}] +set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}] +set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}] +set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}] +set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}] +set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}] +set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}] +set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}] +set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}] +set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}] +set_property IOB TRUE [get_ports {DB0_GPIO[*]}] diff --git a/top/x400/constraints/timing/common.xdc b/top/x400/constraints/timing/common.xdc index 288465a..865708e 100644 --- a/top/x400/constraints/timing/common.xdc +++ b/top/x400/constraints/timing/common.xdc @@ -16,12 +16,6 @@ set ref_clk_period 40.00 create_clock -name ref_clk -period $ref_clk_period [get_ports BASE_REFCLK_FPGA_P] -# PLL Reference Clock. Used to derive data clocks. -# Constrain to the fastest possible clock rate supported in the driver. -# MPM supports 61.44 / 62.5 / 64.0 MHz. -set pll_ref_clk_period 15.625 -create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P] - # MGT Clocks # Clock Reference | Frequency | Purpose # MGT_REFCLK_LMK0 | 156.25/125 MHz | 10 GbE @@ -69,22 +63,11 @@ set synth_sync_ports [get_ports {DB0_SYNTH_SYNC DB1_SYNTH_SYNC}] set_output_delay -clock [get_clocks pll_ref_clk] -min -$synth_sync_hold_requirement $synth_sync_ports set_output_delay -clock [get_clocks pll_ref_clk] -max $synth_sync_setup_requirement $synth_sync_ports - ############################################################################### # SPI to MB CPLD (PL) # This interface is defined as system synchronous to pll_ref_clk. ############################################################################### -# The output delays are chosen to allow a large time window of valid data for -# the MB CPLD logic. -set spi_min_out_delay 0.000 -set spi_max_out_delay 11.000 - -# Set output constraints for all ports. -set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}] -set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports -set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports - # Both CPLD and FPGA use PLL reference clock from a common clock chip. # The traces from that clock chip to the ICs are not length matched. Assume a # worst case clock difference of 0.5 ns at the IC inputs. There is no direction @@ -249,93 +232,6 @@ set_output_delay -clock ref_clk -max $lmk_sync_output_max_delay [get_ports {LMK_ set_output_delay -clock ref_clk -min $lmk_sync_output_min_delay [get_ports {LMK_SYNC}] -############################################################################### -# SPLL SYSREF Capture -############################################################################### - -# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces -# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both -# SYSREF and PLL reference clock are directly fed into the RFSoC. -# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC -# output) with a double synchronizer and then transfered to the RFDC clock -# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for -# sync. purposes. -# SYSREF is a continuous signal running at PRC freq. / 25, and it is -# intentionally shifted in the LMK chip to align it closer to the -# PRC's falling edge. -# The added delay follows the formula: -# SYSREF LMK delay = 22 * sample clock period -# The highest sampling frequency supported in MPM (3.072 GHz) is used for -# timing constrains. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9). -set sysref_lmk_delay 7.161 -# -# These are the signals' lengths and corresponding delays (assuming 170 ps/in): -# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns -# - PRC --> 5668 mils (5.668 inches) = 0.964 ns -# -# For min/max input delay calculations, it is assumed min prop. delay of 0 ns, -# which essentially over-constrains SYSREF. -# -# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is -# calculated as follows: -# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max) -# - PRC prop. delay (min) -set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}] -# -# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it -# is calculated as follows: -# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min) -# - PRC prop. delay (min) -set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}] - -set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}] -set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}] - - -############################################################################### -# DB GPIO -# This interface is defined as system synchronous to pll_ref_clk. -# Some timing constants in this section are declared in -# /fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc -############################################################################### - -# Set output constraints for all ports. -set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}] -set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports -set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports - -# Output enable signal is available one clock cycle ahead of valid data, this -# enables the use of multi-cycle paths. -set db_gpio_out_en_regs [get_cells -hierarchical -filter \ - {PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}] -set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports -set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports - -# Calculate output delays back from capturing edge, add board delay and clock -# difference. -# Assume worst case as data being generated late and receiving an early clock: -# - Max CPLD TCO -# - Max data propagation delay -# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay -# - Maximum delay from MC100EPT23 clock buffer -set_input_delay -clock pll_ref_clk \ - -max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \ - + $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \ - $db_gpio_ports - -# Negate minimum output delay as it is defined from the change to the start -# clock edge. -# Assume worst case as data being generated early and receiving an late clock: -# - Min CPLD TCO -# - Min data propagation delay (0) -# - Min CPLD clock propagation delay and max FPGA clock propagation delay -set_input_delay -clock pll_ref_clk \ - -min [expr {- $db_gpio_cpld_min_out \ - - $db_gpio_board_min_delay \ - - $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \ - $db_gpio_ports - - ############################################################################### # x4xx_ps_rfdc_bd ############################################################################### @@ -350,32 +246,6 @@ set gpio_regs [get_pins -of [get_cells -filter {IS_SEQUENTIAL && NAME =~ *rfdc/c set mux_regs [get_cells -hier -filter {IS_SEQUENTIAL && NAME =~ *rfdc/calibration_muxes/gpio_to_axis_mux*}] set_false_path -from $gpio_regs -to $mux_regs -# This property tells Vivado that we require these clocks to be well aligned. -# We have synchronous clock domain crossings between these clocks that can have -# large hold violations after placement due to uneven clock loading. -set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\ - NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\ - NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\ - NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\ - NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\ - NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \ -}] - -# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that -# code clocked in this domain will be reset after this clocked is enabled. This -# will make timing easier to meet on these clock domains. -set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \ - -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}] - -set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \ - -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}] - -set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \ - -to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}] - -set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \ - -to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}] - ############################################################################### # Misc Constraints diff --git a/top/x400/constraints/timing/x410.xdc b/top/x400/constraints/timing/x410.xdc new file mode 100644 index 0000000..454e821 --- /dev/null +++ b/top/x400/constraints/timing/x410.xdc @@ -0,0 +1,141 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# Timing constraints exclusive to X410. These should be used +# in conjunction with ./common.xdc +# + +############################################################################### +# DB GPIO +# This interface is defined as system synchronous to pll_ref_clk. +# Some timing constants in this section are declared in +# /fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc +############################################################################### + +# Set output constraints for all ports. +set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}] +set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports +set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports + +# Output enable signal is available one clock cycle ahead of valid data, this +# enables the use of multi-cycle paths. +set db_gpio_out_en_regs [get_cells -hierarchical -filter \ + {PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}] +set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports +set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports + +# Calculate output delays back from capturing edge, add board delay and clock +# difference. +# Assume worst case as data being generated late and receiving an early clock: +# - Max CPLD TCO +# - Max data propagation delay +# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay +# - Maximum delay from MC100EPT23 clock buffer +set_input_delay -clock pll_ref_clk \ + -max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \ + + $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \ + $db_gpio_ports + +# Negate minimum output delay as it is defined from the change to the start +# clock edge. +# Assume worst case as data being generated early and receiving an late clock: +# - Min CPLD TCO +# - Min data propagation delay (0) +# - Min CPLD clock propagation delay and max FPGA clock propagation delay +set_input_delay -clock pll_ref_clk \ + -min [expr {- $db_gpio_cpld_min_out \ + - $db_gpio_board_min_delay \ + - $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \ + $db_gpio_ports + + +############################################################################### +# x410_ps_rfdc_bd +############################################################################### + +# This property tells Vivado that we require these clocks to be well aligned. +# We have synchronous clock domain crossings between these clocks that can have +# large hold violations after placement due to uneven clock loading. +set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \ +}] + +# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that +# code clocked in this domain will be reset after this clocked is enabled. This +# will make timing easier to meet on these clock domains. +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}] + +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}] + +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}] + +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}] + + +############################################################################### +# SPLL SYSREF Capture +############################################################################### + +# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces +# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both +# SYSREF and PLL reference clock are directly fed into the RFSoC. +# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC +# output) with a double synchronizer and then transfered to the RFDC clock +# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for +# sync. purposes. +# SYSREF is a continuous signal running at PRC freq. / 25, and it is +# intentionally shifted in the LMK chip to align it closer to the +# PRC's falling edge. +# The added delay follows the formula: +# SYSREF LMK delay = 22 * sample clock period +# The highest sampling frequency supported in MPM (3.072 GHz) is used for +# timing constraints. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9). +set sysref_lmk_delay 7.161 +# +# These are the signals' lengths and corresponding delays (assuming 170 ps/in): +# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns +# - PRC --> 5668 mils (5.668 inches) = 0.964 ns +# +# For min/max input delay calculations, it is assumed min prop. delay of 0 ns, +# which essentially over-constrains SYSREF. +# +# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is +# calculated as follows: +# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max) +# - PRC prop. delay (min) +set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}] +# +# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it +# is calculated as follows: +# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min) +# - PRC prop. delay (min) +set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}] + +set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}] +set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}] + +############################################################################### +# SPI to MB CPLD (PL) +# This interface is defined as system synchronous to pll_ref_clk. +############################################################################### + +# The output delays are chosen to allow a large time window of valid data for +# the MB CPLD logic. +set spi_min_out_delay 0.000 +set spi_max_out_delay 11.000 + +# Set output constraints for all ports. +set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}] +set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports +set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports diff --git a/top/x400/constraints/timing/x410_clocks.xdc b/top/x400/constraints/timing/x410_clocks.xdc new file mode 100644 index 0000000..c45e26d --- /dev/null +++ b/top/x400/constraints/timing/x410_clocks.xdc @@ -0,0 +1,18 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# Clock definition constraints for X410 +# + +############################################################################### +# Motherboard Clocks +############################################################################### + +# PLL Reference Clock. Used to derive data clocks. +# Constrain to the fastest possible clock rate supported in the driver. +# MPM supports 61.44 / 62.5 / 64.0 MHz. +set pll_ref_clk_period 15.625 +create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P] diff --git a/top/x400/cpld/regmap/x440/constants_regmap_utils.vh b/top/x400/cpld/regmap/x440/constants_regmap_utils.vh new file mode 100644 index 0000000..54d338e --- /dev/null +++ b/top/x400/cpld/regmap/x440/constants_regmap_utils.vh @@ -0,0 +1,28 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: constants_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group CONSTANTS_GROUP +//=============================================================================== + + // Enumerated type CONSTANTS_ENUM + localparam CONSTANTS_ENUM_SIZE = 4; + localparam PS_CPLD_SIGNATURE = 'hA522D28; // CONSTANTS_ENUM:PS_CPLD_SIGNATURE + localparam CPLD_REVISION = 'h22080414; // CONSTANTS_ENUM:CPLD_REVISION + localparam OLDEST_CPLD_REVISION = 'h22080414; // CONSTANTS_ENUM:OLDEST_CPLD_REVISION + localparam PL_CPLD_SIGNATURE = 'h3FDC5C47; // CONSTANTS_ENUM:PL_CPLD_SIGNATURE diff --git a/top/x400/cpld/regmap/x440/led_setup_regmap_utils.vh b/top/x400/cpld/regmap/x440/led_setup_regmap_utils.vh new file mode 100644 index 0000000..a04415e --- /dev/null +++ b/top/x400/cpld/regmap/x440/led_setup_regmap_utils.vh @@ -0,0 +1,63 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: led_setup_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // LED_CONTROL : 0x0 (led_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group LED_SETUP_REGISTERS +//=============================================================================== + + // LED_CONTROL Register (from led_control.v) + localparam LED_CONTROL = 'h0; // Register Offset + localparam LED_CONTROL_SIZE = 32; // register width in bits + localparam LED_CONTROL_MASK = 32'h7070707; + localparam CH0_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH0_RX2_LED_EN + localparam CH0_RX2_LED_EN_MSB = 0; //LED_CONTROL:CH0_RX2_LED_EN + localparam CH0_RX2_LED_EN = 0; //LED_CONTROL:CH0_RX2_LED_EN + localparam CH0_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH0_TRX1_LED_RED_EN + localparam CH0_TRX1_LED_RED_EN_MSB = 1; //LED_CONTROL:CH0_TRX1_LED_RED_EN + localparam CH0_TRX1_LED_RED_EN = 1; //LED_CONTROL:CH0_TRX1_LED_RED_EN + localparam CH0_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH0_TRX1_LED_GR_EN + localparam CH0_TRX1_LED_GR_EN_MSB = 2; //LED_CONTROL:CH0_TRX1_LED_GR_EN + localparam CH0_TRX1_LED_GR_EN = 2; //LED_CONTROL:CH0_TRX1_LED_GR_EN + localparam CH1_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH1_RX2_LED_EN + localparam CH1_RX2_LED_EN_MSB = 8; //LED_CONTROL:CH1_RX2_LED_EN + localparam CH1_RX2_LED_EN = 8; //LED_CONTROL:CH1_RX2_LED_EN + localparam CH1_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH1_TRX1_LED_RED_EN + localparam CH1_TRX1_LED_RED_EN_MSB = 9; //LED_CONTROL:CH1_TRX1_LED_RED_EN + localparam CH1_TRX1_LED_RED_EN = 9; //LED_CONTROL:CH1_TRX1_LED_RED_EN + localparam CH1_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH1_TRX1_LED_GR_EN + localparam CH1_TRX1_LED_GR_EN_MSB = 10; //LED_CONTROL:CH1_TRX1_LED_GR_EN + localparam CH1_TRX1_LED_GR_EN = 10; //LED_CONTROL:CH1_TRX1_LED_GR_EN + localparam CH2_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH2_RX2_LED_EN + localparam CH2_RX2_LED_EN_MSB = 16; //LED_CONTROL:CH2_RX2_LED_EN + localparam CH2_RX2_LED_EN = 16; //LED_CONTROL:CH2_RX2_LED_EN + localparam CH2_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH2_TRX1_LED_RED_EN + localparam CH2_TRX1_LED_RED_EN_MSB = 17; //LED_CONTROL:CH2_TRX1_LED_RED_EN + localparam CH2_TRX1_LED_RED_EN = 17; //LED_CONTROL:CH2_TRX1_LED_RED_EN + localparam CH2_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH2_TRX1_LED_GR_EN + localparam CH2_TRX1_LED_GR_EN_MSB = 18; //LED_CONTROL:CH2_TRX1_LED_GR_EN + localparam CH2_TRX1_LED_GR_EN = 18; //LED_CONTROL:CH2_TRX1_LED_GR_EN + localparam CH3_RX2_LED_EN_SIZE = 1; //LED_CONTROL:CH3_RX2_LED_EN + localparam CH3_RX2_LED_EN_MSB = 24; //LED_CONTROL:CH3_RX2_LED_EN + localparam CH3_RX2_LED_EN = 24; //LED_CONTROL:CH3_RX2_LED_EN + localparam CH3_TRX1_LED_RED_EN_SIZE = 1; //LED_CONTROL:CH3_TRX1_LED_RED_EN + localparam CH3_TRX1_LED_RED_EN_MSB = 25; //LED_CONTROL:CH3_TRX1_LED_RED_EN + localparam CH3_TRX1_LED_RED_EN = 25; //LED_CONTROL:CH3_TRX1_LED_RED_EN + localparam CH3_TRX1_LED_GR_EN_SIZE = 1; //LED_CONTROL:CH3_TRX1_LED_GR_EN + localparam CH3_TRX1_LED_GR_EN_MSB = 26; //LED_CONTROL:CH3_TRX1_LED_GR_EN + localparam CH3_TRX1_LED_GR_EN = 26; //LED_CONTROL:CH3_TRX1_LED_GR_EN diff --git a/top/x400/cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh b/top/x400/cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh new file mode 100644 index 0000000..622c935 --- /dev/null +++ b/top/x400/cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh @@ -0,0 +1,36 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: mb_cpld_pl_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // PL_REGISTERS : 0x0 (mb_cpld.v) + // PL_DB0_LED_REGISTERS : 0x50 (mb_cpld.v) + // PL_DB1_LED_REGISTERS : 0x60 (mb_cpld.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group MB_CPLD_PL_WINDOWS +//=============================================================================== + + // PL_REGISTERS Window (from mb_cpld.v) + localparam PL_REGISTERS = 'h0; // Window Offset + localparam PL_REGISTERS_SIZE = 'h40; // size in bytes + + // PL_DB0_LED_REGISTERS Window (from mb_cpld.v) + localparam PL_DB0_LED_REGISTERS = 'h50; // Window Offset + localparam PL_DB0_LED_REGISTERS_SIZE = 'h10; // size in bytes + + // PL_DB1_LED_REGISTERS Window (from mb_cpld.v) + localparam PL_DB1_LED_REGISTERS = 'h60; // Window Offset + localparam PL_DB1_LED_REGISTERS_SIZE = 'h10; // size in bytes diff --git a/top/x400/cpld_interface.v b/top/x400/cpld_interface.v index a98fe79..9168868 100644 --- a/top/x400/cpld_interface.v +++ b/top/x400/cpld_interface.v @@ -30,11 +30,6 @@ module cpld_interface ( // Reset (domain: pll_ref_clk) input wire ctrlport_rst, - // Timestamp (domain: radio_clk) - input wire [63:0] radio_time, - input wire radio_time_stb, - input wire [ 3:0] time_ignore_bits, - // AXI4-Lite: Write address port (domain: s_axi_aclk) input wire [16:0] s_axi_awaddr, input wire s_axi_awvalid, @@ -64,8 +59,6 @@ module cpld_interface ( input wire [19:0] s_ctrlport_req_addr, input wire [31:0] s_ctrlport_req_data, input wire [ 3:0] s_ctrlport_req_byte_en, - input wire s_ctrlport_req_has_time, - input wire [63:0] s_ctrlport_req_time, output wire s_ctrlport_resp_ack, output wire [ 1:0] s_ctrlport_resp_status, output wire [31:0] s_ctrlport_resp_data, @@ -91,7 +84,8 @@ module cpld_interface ( `include "../../lib/rfnoc/core/ctrlport.vh" `include "regmap/pl_cpld_regmap_utils.vh" - `include "cpld/regmap/mb_cpld_pl_regmap_utils.vh" + // Variant-dependent register map. + `include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh" `include "cpld/regmap/pl_cpld_base_regmap_utils.vh" //--------------------------------------------------------------------------- @@ -103,28 +97,6 @@ module cpld_interface ( assign s_axi_areset = ~s_axi_aresetn; assign ctrlport_clk = pll_ref_clk; - //--------------------------------------------------------------------------- - // Timestamp synchronization - //--------------------------------------------------------------------------- - - reg [ 3:0] radio_time_stb_shift_reg; - wire radio_time_stb_prc; - reg [63:0] radio_time_prc; - - // radio_clk and pll_ref_clk are synchronous clocks with an integer - // multiplier <= 4. - // - // A simple register can be used to capture the latest timestamp the strobe - // pulse is preserved for up to 4 clock cycles and used in pll_ref_clk domain - // to driver timers. - always @(posedge radio_clk) begin - radio_time_stb_shift_reg <= {radio_time_stb_shift_reg[2:0], radio_time_stb}; - if (radio_time_stb) begin - radio_time_prc <= radio_time; - end - end - assign radio_time_stb_prc = | radio_time_stb_shift_reg; - //--------------------------------------------------------------------------- // MPM Endpoint connection //--------------------------------------------------------------------------- @@ -134,12 +106,10 @@ module cpld_interface ( wire [19:0] mpm_endpoint_ctrlport_axi_clk_req_addr; wire [ 3:0] mpm_endpoint_ctrlport_axi_clk_req_byte_en; wire [31:0] mpm_endpoint_ctrlport_axi_clk_req_data; - wire mpm_endpoint_ctrlport_axi_clk_req_has_time; wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_portid; wire mpm_endpoint_ctrlport_axi_clk_req_rd; wire [15:0] mpm_endpoint_ctrlport_axi_clk_req_rem_epid; wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_rem_portid; - wire [63:0] mpm_endpoint_ctrlport_axi_clk_req_time; wire mpm_endpoint_ctrlport_axi_clk_req_wr; wire mpm_endpoint_ctrlport_axi_clk_resp_ack; wire [31:0] mpm_endpoint_ctrlport_axi_clk_resp_data; @@ -177,8 +147,8 @@ module cpld_interface ( .m_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid), .m_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data), .m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en), - .m_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time), - .m_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), .m_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack), .m_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status), .m_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data) @@ -186,16 +156,14 @@ module cpld_interface ( // Transfer AXI clock based MPM endpoint control port request to pll_ref_clk // domain. - wire [19:0] mpm_endpoint_ctrlport_pll_clk_req_addr; - wire [ 3:0] mpm_endpoint_ctrlport_pll_clk_req_byte_en; - wire [31:0] mpm_endpoint_ctrlport_pll_clk_req_data; - wire mpm_endpoint_ctrlport_pll_clk_req_has_time; - wire mpm_endpoint_ctrlport_pll_clk_req_rd; - wire [63:0] mpm_endpoint_ctrlport_pll_clk_req_time; - wire mpm_endpoint_ctrlport_pll_clk_req_wr; - wire mpm_endpoint_ctrlport_pll_clk_resp_ack; - wire [31:0] mpm_endpoint_ctrlport_pll_clk_resp_data; - wire [ 1:0] mpm_endpoint_ctrlport_pll_clk_resp_status; + wire [19:0] mpm_endpoint_ctrlport_req_addr; + wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en; + wire [31:0] mpm_endpoint_ctrlport_req_data; + wire mpm_endpoint_ctrlport_req_rd; + wire mpm_endpoint_ctrlport_req_wr; + wire mpm_endpoint_ctrlport_resp_ack; + wire [31:0] mpm_endpoint_ctrlport_resp_data; + wire [ 1:0] mpm_endpoint_ctrlport_resp_status; ctrlport_clk_cross ctrlport_clk_cross_mpm ( .rst (s_axi_areset), @@ -208,63 +176,25 @@ module cpld_interface ( .s_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid), .s_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data), .s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en), - .s_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time), - .s_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time), + .s_ctrlport_req_has_time (1'b0), + .s_ctrlport_req_time (64'b0), .s_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack), .s_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status), .s_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data), .m_ctrlport_clk (ctrlport_clk), - .m_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr), - .m_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd), - .m_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr), + .m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr), + .m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd), + .m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr), .m_ctrlport_req_portid (), .m_ctrlport_req_rem_epid (), .m_ctrlport_req_rem_portid (), - .m_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data), - .m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en), - .m_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time), - .m_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time), - .m_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack), - .m_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status), - .m_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data) - ); - - // Apply time of ControlPort request to MPM endpoint request. - wire [19:0] mpm_endpoint_ctrlport_req_addr; - wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en; - wire [31:0] mpm_endpoint_ctrlport_req_data; - wire mpm_endpoint_ctrlport_req_rd; - wire mpm_endpoint_ctrlport_req_wr; - wire mpm_endpoint_ctrlport_resp_ack; - wire [31:0] mpm_endpoint_ctrlport_resp_data; - wire [ 1:0] mpm_endpoint_ctrlport_resp_status; - - ctrlport_timer #( - .EXEC_LATE_CMDS (1) - ) ctrlport_timer_mpm ( - .clk (ctrlport_clk), - .rst (ctrlport_rst), - .time_now (radio_time_prc), - .time_now_stb (radio_time_stb_prc), - .time_ignore_bits (time_ignore_bits), - .s_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr), - .s_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd), - .s_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr), - .s_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data), - .s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en), - .s_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time), - .s_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time), - .s_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack), - .s_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status), - .s_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data), - .m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr), - .m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd), - .m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr), - .m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data), - .m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en), - .m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack), - .m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status), - .m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data) + .m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data), + .m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack), + .m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status), + .m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data) ); //--------------------------------------------------------------------------- @@ -272,16 +202,14 @@ module cpld_interface ( //--------------------------------------------------------------------------- // Transfer request to pll_ref_clk domain. - wire [19:0] app_ctrlport_pll_clk_req_addr; - wire [ 3:0] app_ctrlport_pll_clk_req_byte_en; - wire [31:0] app_ctrlport_pll_clk_req_data; - wire app_ctrlport_pll_clk_req_has_time; - wire app_ctrlport_pll_clk_req_rd; - wire [63:0] app_ctrlport_pll_clk_req_time; - wire app_ctrlport_pll_clk_req_wr; - wire app_ctrlport_pll_clk_resp_ack; - wire [31:0] app_ctrlport_pll_clk_resp_data; - wire [ 1:0] app_ctrlport_pll_clk_resp_status; + wire [19:0] app_ctrlport_req_addr; + wire [ 3:0] app_ctrlport_req_byte_en; + wire [31:0] app_ctrlport_req_data; + wire app_ctrlport_req_rd; + wire app_ctrlport_req_wr; + wire app_ctrlport_resp_ack; + wire [31:0] app_ctrlport_resp_data; + wire [ 1:0] app_ctrlport_resp_status; ctrlport_clk_cross ctrlport_clk_cross_app ( .rst (ctrlport_rst), @@ -294,63 +222,25 @@ module cpld_interface ( .s_ctrlport_req_rem_portid (), .s_ctrlport_req_data (s_ctrlport_req_data), .s_ctrlport_req_byte_en (s_ctrlport_req_byte_en), - .s_ctrlport_req_has_time (s_ctrlport_req_has_time), - .s_ctrlport_req_time (s_ctrlport_req_time), + .s_ctrlport_req_has_time (1'b0), + .s_ctrlport_req_time (64'b0), .s_ctrlport_resp_ack (s_ctrlport_resp_ack), .s_ctrlport_resp_status (s_ctrlport_resp_status), .s_ctrlport_resp_data (s_ctrlport_resp_data), .m_ctrlport_clk (ctrlport_clk), - .m_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr), - .m_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd), - .m_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr), + .m_ctrlport_req_wr (app_ctrlport_req_wr), + .m_ctrlport_req_rd (app_ctrlport_req_rd), + .m_ctrlport_req_addr (app_ctrlport_req_addr), .m_ctrlport_req_portid (), .m_ctrlport_req_rem_epid (), .m_ctrlport_req_rem_portid (), - .m_ctrlport_req_data (app_ctrlport_pll_clk_req_data), - .m_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en), - .m_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time), - .m_ctrlport_req_time (app_ctrlport_pll_clk_req_time), - .m_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack), - .m_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status), - .m_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data) - ); - - // Apply timing to application based ControlPort request. - wire [19:0] app_ctrlport_req_addr; - wire [ 3:0] app_ctrlport_req_byte_en; - wire [31:0] app_ctrlport_req_data; - wire app_ctrlport_req_rd; - wire app_ctrlport_req_wr; - wire app_ctrlport_resp_ack; - wire [31:0] app_ctrlport_resp_data; - wire [ 1:0] app_ctrlport_resp_status; - - ctrlport_timer #( - .EXEC_LATE_CMDS (1) - ) ctrlport_timer_app ( - .clk (ctrlport_clk), - .rst (ctrlport_rst), - .time_now (radio_time_prc), - .time_now_stb (radio_time_stb_prc), - .time_ignore_bits (time_ignore_bits), - .s_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr), - .s_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd), - .s_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr), - .s_ctrlport_req_data (app_ctrlport_pll_clk_req_data), - .s_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en), - .s_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time), - .s_ctrlport_req_time (app_ctrlport_pll_clk_req_time), - .s_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack), - .s_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status), - .s_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data), - .m_ctrlport_req_wr (app_ctrlport_req_wr), - .m_ctrlport_req_rd (app_ctrlport_req_rd), - .m_ctrlport_req_addr (app_ctrlport_req_addr), - .m_ctrlport_req_data (app_ctrlport_req_data), - .m_ctrlport_req_byte_en (app_ctrlport_req_byte_en), - .m_ctrlport_resp_ack (app_ctrlport_resp_ack), - .m_ctrlport_resp_status (app_ctrlport_resp_status), - .m_ctrlport_resp_data (app_ctrlport_resp_data) + .m_ctrlport_req_data (app_ctrlport_req_data), + .m_ctrlport_req_byte_en (app_ctrlport_req_byte_en), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (app_ctrlport_resp_ack), + .m_ctrlport_resp_status (app_ctrlport_resp_status), + .m_ctrlport_resp_data (app_ctrlport_resp_data) ); //--------------------------------------------------------------------------- @@ -440,8 +330,8 @@ module cpld_interface ( .s_ctrlport_req_rem_portid (), .s_ctrlport_req_data ({ipass_ctrlport_req_data, led_ctrlport_req_data, mpm_endpoint_ctrlport_req_data, app_ctrlport_req_data}), .s_ctrlport_req_byte_en ({ipass_ctrlport_req_byte_en, led_ctrlport_req_byte_en, mpm_endpoint_ctrlport_req_byte_en, app_ctrlport_req_byte_en}), - .s_ctrlport_req_has_time (), - .s_ctrlport_req_time (), + .s_ctrlport_req_has_time ({4{1'b0}}), + .s_ctrlport_req_time ({4{64'b0}}), .s_ctrlport_resp_ack ({ipass_ctrlport_resp_ack, led_ctrlport_resp_ack, mpm_endpoint_ctrlport_resp_ack, app_ctrlport_resp_ack}), .s_ctrlport_resp_status ({ipass_ctrlport_resp_status, led_ctrlport_resp_status, mpm_endpoint_ctrlport_resp_status, app_ctrlport_resp_status}), .s_ctrlport_resp_data ({ipass_ctrlport_resp_data, led_ctrlport_resp_data, mpm_endpoint_ctrlport_resp_data, app_ctrlport_resp_data}), diff --git a/top/x400/cpld_interface_regs.v b/top/x400/cpld_interface_regs.v index 72cfa9c..a6d0dad 100644 --- a/top/x400/cpld_interface_regs.v +++ b/top/x400/cpld_interface_regs.v @@ -45,9 +45,11 @@ module cpld_interface_regs #( output wire [95:0] version_info ); - `include "regmap/cpld_interface_regmap_utils.vh" - `include "regmap/versioning_regs_regmap_utils.vh" + // Variant-dependent register map. + `include "regmap/x410/versioning_regs_regmap_utils.vh" + `include "regmap/versioning_utils.vh" + `include "regmap/cpld_interface_regmap_utils.vh" `include "../../lib/rfnoc/core/ctrlport.vh" //---------------------------------------------------------- diff --git a/top/x400/dboards/ctrlport_clk_crossing_derived.v b/top/x400/dboards/ctrlport_clk_crossing_derived.v new file mode 100644 index 0000000..a3135cc --- /dev/null +++ b/top/x400/dboards/ctrlport_clk_crossing_derived.v @@ -0,0 +1,130 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ctrlport_clk_crossing_derived +// +// Description: +// Performs a simplified clk crossing for a ctrlport interface. +// i_clk must be derived from o_clk by an integer multiplier and +// originate from the same PLL. This ensures the clock crossing +// can be achieved by using simple registers, as STA will be able +// to meet setup and hold requirements on them. +// + +`default_nettype none + +module ctrlport_clk_crossing_derived ( + // Clocks + input wire i_clk, + input wire o_clk, + + // Request (domain: i_clk) + input wire i_ctrlport_rst, + input wire i_ctrlport_req_wr, + input wire i_ctrlport_req_rd, + input wire [19:0] i_ctrlport_req_addr, + input wire [31:0] i_ctrlport_req_data, + + // Response (domain: i_clk) + output wire i_ctrlport_resp_ack, + output reg [ 1:0] i_ctrlport_resp_status, + output reg [31:0] i_ctrlport_resp_data, + + // Request (domain: o_clk) + output reg o_ctrlport_rst, + output reg o_ctrlport_req_wr, + output reg o_ctrlport_req_rd, + output reg [19:0] o_ctrlport_req_addr, + output reg [31:0] o_ctrlport_req_data, + + // Response (domain: o_clk) + input wire o_ctrlport_resp_ack, + input wire [ 1:0] o_ctrlport_resp_status, + input wire [31:0] o_ctrlport_resp_data + +); + + // holding read and write flags for multiple i_clk cycles + reg ctrlport_req_wr_hold = 1'b0; + reg ctrlport_req_rd_hold = 1'b0; + + reg ctrlport_req_rd_fall = 1'b0; + reg ctrlport_req_wr_fall = 1'b0; + reg [31:0] ctrlport_resp_data_fall = 32'b0; + reg [ 1:0] ctrlport_resp_status_fall = 2'b0; + reg ctrlport_resp_ack_fall = 1'b0; + + // Retime signals to falling edge of i_clk. By sampling on the falling edge of + // i_clk, we provide (nominally) half a i_clk period of hold, while + // reducing setup time by half. The late arrival of i_clk adds back some + // of the lost setup margin. + always @(negedge i_clk) begin + ctrlport_req_rd_fall <= o_ctrlport_req_rd; + ctrlport_req_wr_fall <= o_ctrlport_req_wr; + ctrlport_resp_ack_fall <= o_ctrlport_resp_ack; + ctrlport_resp_status_fall <= o_ctrlport_resp_status; + ctrlport_resp_data_fall <= o_ctrlport_resp_data; + end + + always @(posedge i_clk) begin + if (ctrlport_req_wr_fall) begin + ctrlport_req_wr_hold <= 1'b0; + end else if (i_ctrlport_req_wr) begin + ctrlport_req_wr_hold <= 1'b1; + end + if (ctrlport_req_rd_fall) begin + ctrlport_req_rd_hold <= 1'b0; + end else if (i_ctrlport_req_rd) begin + ctrlport_req_rd_hold <= 1'b1; + end + + // capture request address and data + if (i_ctrlport_req_wr || i_ctrlport_req_rd) begin + o_ctrlport_req_addr <= i_ctrlport_req_addr; + o_ctrlport_req_data <= i_ctrlport_req_data; + end + end + + // capture extended flags in o_clk domain + always @(posedge o_clk) begin + o_ctrlport_req_wr <= ctrlport_req_wr_hold; + o_ctrlport_req_rd <= ctrlport_req_rd_hold; + end + + // search for rising edge in response + reg [1:0] ctrlport_resp_ack_reg = 2'b0; + always @(posedge i_clk) begin + ctrlport_resp_ack_reg = {ctrlport_resp_ack_reg[0], ctrlport_resp_ack_fall}; + end + assign i_ctrlport_resp_ack = ctrlport_resp_ack_reg[0] & ~ctrlport_resp_ack_reg[1]; + + // capture response data + always @(posedge i_clk) begin + if (ctrlport_resp_ack_fall) begin + i_ctrlport_resp_status <= ctrlport_resp_status_fall; + i_ctrlport_resp_data <= ctrlport_resp_data_fall; + end + end + + // transfer reset + reg ctrlport_rst_hold = 1'b0; + reg ctrlport_rst_fall = 1'b0; + always @(posedge i_clk) begin + if (i_ctrlport_rst) begin + ctrlport_rst_hold <= 1'b1; + end else if (ctrlport_rst_fall) begin + ctrlport_rst_hold <= 1'b0; + end + end + always @(posedge o_clk) begin + o_ctrlport_rst <= ctrlport_rst_hold; + end + always @(negedge i_clk) begin + ctrlport_rst_fall <= o_ctrlport_rst; + end + +endmodule + +`default_nettype wire diff --git a/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf b/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf index 2b765e8..126b141 100644 --- a/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf +++ b/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf @@ -827,14 +827,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc -set_global_assignment -name SDC_FILE ../../../../cpld/db_spi_shared_constants.sdc +set_global_assignment -name SDC_FILE ../../../../cpld/x410/db_spi_shared_constants.sdc set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v -set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave.v -set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave_to_ctrlport_master.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave_to_ctrlport_master.v set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v set_global_assignment -name VERILOG_FILE ../register_endpoints/power_regs.v set_global_assignment -name VERILOG_FILE ../register_endpoints/switch_control.v @@ -847,7 +847,7 @@ set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v -set_global_assignment -name VERILOG_FILE ../../../../cpld/reconfig_engine.v +set_global_assignment -name VERILOG_FILE ../../../../cpld/common/reconfig_engine.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh diff --git a/top/x400/dboards/zbx/db_gpio_interface.v b/top/x400/dboards/zbx/db_gpio_interface.v new file mode 100644 index 0000000..c5983ca --- /dev/null +++ b/top/x400/dboards/zbx/db_gpio_interface.v @@ -0,0 +1,214 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: db_gpio_interface +// +// Description: +// Interface for GPIO interface towards daughterboards. +// +// A ControlPort interface is serialized into bytes along with a valid signal. +// The ControlPort supports write requests only. Byte enables are not supported. +// There is support for timed commands. +// Furthermore there are 4 state wires towards the DB. Ensure an appropriate +// hold time on the states as the transmission happens in pll_ref_clk, which is +// slower than radio_clk. Pulses of e.g. just a single clock cycle may not get +// transferred to the DB. +// +// The 20 available GPIO lines are assigned with +// - 5x empty +// - bytestream direction +// - bytestream valid +// - bytestream data (8 bits) +// - 1x empty +// - db_state (4 bits) +// + +`default_nettype none + +module db_gpio_interface ( + // Clocks and reset + input wire radio_clk, + input wire pll_ref_clk, + + // DB state lines (domain: radio_clk) + input wire [ 3:0] db_state, + // Request (domain: radio_clk) + input wire ctrlport_rst, + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + + // Response (domain: radio_clk) + output wire s_ctrlport_resp_ack, + output wire [ 1:0] s_ctrlport_resp_status, + output wire [31:0] s_ctrlport_resp_data, + + // GPIO interface (domain: pll_ref_clk) + input wire [19:0] gpio_in, + output wire [19:0] gpio_out, + output wire [19:0] gpio_out_en, + + // Version (Constant) + output wire [95:0] version_info +); + + `include "../../regmap/x410/versioning_regs_regmap_utils.vh" + `include "../../regmap/versioning_utils.vh" + + //---------------------------------------------------------------------------- + // Clock domain crossing (radio_clk -> pll_ref_clk) + //---------------------------------------------------------------------------- + // Radio_clk is derived from pll_ref_clk by an integer multiplier and + // originate from the same PLL. + // Therefore the clock crossing can be achieved by using simple registers. + // Static timing analysis will be able to meet setup and hold requirements on + // them. + + wire ctrlport_rst_prc; + + wire ctrlport_req_wr_prc; + wire ctrlport_req_rd_prc; + wire [19:0] ctrlport_req_addr_prc; + wire [31:0] ctrlport_req_data_prc; + + wire ctrlport_resp_ack_prc; + wire [ 1:0] ctrlport_resp_status_prc; + wire [31:0] ctrlport_resp_data_prc; + + ctrlport_clk_crossing_derived ctrlport_clk_crossing_derived_i( + .i_clk (radio_clk), + .o_clk (pll_ref_clk), + .i_ctrlport_rst (ctrlport_rst), + .i_ctrlport_req_wr (s_ctrlport_req_wr), + .i_ctrlport_req_rd (s_ctrlport_req_rd), + .i_ctrlport_req_addr (s_ctrlport_req_addr), + .i_ctrlport_req_data (s_ctrlport_req_data), + .i_ctrlport_resp_ack (s_ctrlport_resp_ack), + .i_ctrlport_resp_status (s_ctrlport_resp_status), + .i_ctrlport_resp_data (s_ctrlport_resp_data), + .o_ctrlport_rst (ctrlport_rst_prc), + .o_ctrlport_req_wr (ctrlport_req_wr_prc), + .o_ctrlport_req_rd (ctrlport_req_rd_prc), + .o_ctrlport_req_addr (ctrlport_req_addr_prc), + .o_ctrlport_req_data (ctrlport_req_data_prc), + .o_ctrlport_resp_ack (ctrlport_resp_ack_prc), + .o_ctrlport_resp_status (ctrlport_resp_status_prc), + .o_ctrlport_resp_data (ctrlport_resp_data_prc) + ); + + // transfer state lines + reg [3:0] db_state_prc = 4'b0; + reg [3:0] db_state_prc_fe = 4'b0; + always @(posedge pll_ref_clk) begin + db_state_prc <= db_state; + end + always @(negedge pll_ref_clk) begin + db_state_prc_fe <= db_state_prc; + end + + //---------------------------------------------------------------------------- + // Ctrlport serializer + //---------------------------------------------------------------------------- + wire [7:0] bytestream_data_in; + wire [7:0] bytestream_data_out; + wire bytestream_direction; + wire bytestream_output_enable; + wire bytestream_valid_in; + wire bytestream_valid_out; + + ctrlport_byte_serializer serializer_i ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr (ctrlport_req_wr_prc), + .s_ctrlport_req_rd (ctrlport_req_rd_prc), + .s_ctrlport_req_addr (ctrlport_req_addr_prc), + .s_ctrlport_req_data (ctrlport_req_data_prc), + .s_ctrlport_resp_ack (ctrlport_resp_ack_prc), + .s_ctrlport_resp_status (ctrlport_resp_status_prc), + .s_ctrlport_resp_data (ctrlport_resp_data_prc), + .bytestream_data_in (bytestream_data_in), + .bytestream_valid_in (bytestream_valid_in), + .bytestream_data_out (bytestream_data_out), + .bytestream_valid_out (bytestream_valid_out), + .bytestream_direction (bytestream_direction), + .bytestream_output_enable (bytestream_output_enable) + ); + + // IOB registers to drive data on the falling edge + reg [7:0] bytestream_data_out_fe; + reg bytestream_direction_fe; + reg bytestream_output_enable_fe; + reg bytestream_valid_out_fe; + + // Signals are shifted into a falling edge domain to help meet + // hold requirements at CPLD + always @(negedge pll_ref_clk) begin + if (ctrlport_rst_prc) begin + bytestream_data_out_fe <= 8'b0; + bytestream_valid_out_fe <= 1'b0; + bytestream_direction_fe <= 1'b0; + bytestream_output_enable_fe <= 1'b1; + end else begin + bytestream_data_out_fe <= bytestream_data_out; + bytestream_valid_out_fe <= bytestream_valid_out; + bytestream_direction_fe <= bytestream_direction; + bytestream_output_enable_fe <= bytestream_output_enable; + end + end + + //---------------------------------------------------------------------------- + // wire assignment + //---------------------------------------------------------------------------- + // 5 unused, 10 used, 1 unused and 4 used signals + assign gpio_out = {5'b0, bytestream_direction_fe, bytestream_valid_out_fe, bytestream_data_out_fe, 1'b0, db_state_prc_fe}; + assign gpio_out_en = {5'b0, 1'b1, {9 {bytestream_output_enable_fe}}, 1'b0, {4 {1'b1}} }; + + assign bytestream_valid_in = gpio_in[13]; + assign bytestream_data_in = gpio_in[12:5]; + + //---------------------------------------------------------------------------- + // version_info + //---------------------------------------------------------------------------- + + // Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh + assign version_info = build_component_versions( + DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME, + build_version( + DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR, + DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR, + DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD), + build_version( + DB_GPIO_IFC_CURRENT_VERSION_MAJOR, + DB_GPIO_IFC_CURRENT_VERSION_MINOR, + DB_GPIO_IFC_CURRENT_VERSION_BUILD)); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// +// Daughterboard GPIO interface.{BR/} +// For guidance on when to update these revision numbers, +// please refer to the register map documentation accordingly: +//
  • Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION +//
  • Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION +//
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED +// +// +// +// +// +// +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/doc/X410/X410_FPGA.htm b/top/x400/doc/X410/X410_FPGA.htm new file mode 100644 index 0000000..c38ee0b --- /dev/null +++ b/top/x400/doc/X410/X410_FPGA.htm @@ -0,0 +1,10 @@ + + + X410_FPGA + + + + + + + \ No newline at end of file diff --git a/top/x400/doc/X410/X410_FPGA_left.htm b/top/x400/doc/X410/X410_FPGA_left.htm new file mode 100644 index 0000000..869b9e5 --- /dev/null +++ b/top/x400/doc/X410/X410_FPGA_left.htm @@ -0,0 +1,743 @@ + + + + + + + +
    +

    + + + X410_FPGA +

    +
    +

    + + + P5 Content +

    +
    +
    +

    + + + ports +

    +
    +

    ARM_M_AXI_HPM0

    +

    ARM_S_AXI_HPC0

    +

    ARM_S_AXI_HPC1

    +

    ARM_SPI1_CS3

    +
    +
    +

    + + + AXI_HPM0_REGMAP +

    +

    + + + COMMON +

    +
    +

    RPU

    +

    JTAG_ENGINE

    +

    RESERVED

    +

    MPM_ENDPOINT

    +

    CORE_REGS

    +

    INT_ETH_DMA

    +

    INT_ETH_REGS

    +

    RFDC

    +

    RFDC_REGS

    +
    +

    + + + UHD_ONLY +

    +
    +

    QSFP_0_0

    +

    QSFP_0_1

    +

    QSFP_0_2

    +

    QSFP_0_3

    +

    QSFP_1_0

    +

    QSFP_1_1

    +

    QSFP_1_2

    +

    QSFP_1_3

    +
    +
    +

    + + + MB_CPLD_PS_REGMAP +

    +

    + + + MB_CPLD_PS_WINDOWS +

    +
    +

    PS_REGISTERS

    +

    RECONFIG

    +

    POWER_REGISTERS

    +
    +

    + + + PS_SPI_ENDPOINTS +

    +
    +

    enum SPI_ENDPOINT

    +
    +
    +

    + + + CMAC_REGMAP +

    +

    + + + XILINX_CMAC_REGISTERS +

    +
    +
    +
    +

    + + + CONSTANTS_REGMAP +

    +

    + + + CONSTANTS_GROUP +

    +
    +

    enum CONSTANTS_ENUM

    +
    +
    +

    + + + CORE_REGS_REGMAP +

    +

    + + + CORE_REGS +

    +
    +

    GLOBAL_REGS

    +

    VERSIONING_REGS

    +

    TIMEKEEPER_A

    +

    TIMEKEEPER_B

    +

    DIO

    +
    +
    +

    + + + CPLD_INTERFACE_REGMAP +

    +

    + + + CPLD_INTERFACE_REGS +

    +
    +

    SIGNATURE_REGISTER

    +

    SCRATCH_REGISTER

    +
    +

    + + + CPLD_SPI_CONTROL_REGS +

    +
    +

    MOTHERBOARD_CPLD_DIVIDER

    +

    DAUGHTERBOARD_CPLD_DIVIDER

    +
    +

    + + + IPASS_REGS +

    +
    +

    IPASS_CONTROL

    +
    +
    +

    + + + DIG_IFC_REGMAP +

    +

    + + + SPI_OVER_GPIO_REGS +

    +
    +

    SPI_SLAVE_CONFIG

    +

    SPI_TRANSACTION_CONFIG

    +

    SPI_TRANSACTION_GO

    +

    SPI_STATUS

    +

    CONTROLLER_INFO

    +
    +
    +

    + + + DIO_REGMAP +

    +

    + + + DIO_REGS +

    +
    +

    DIO_MASTER_REGISTER

    +

    DIO_DIRECTION_REGISTER

    +

    DIO_INPUT_REGISTER

    +

    DIO_OUTPUT_REGISTER

    +

    DIO_SOURCE_REGISTER

    +

    RADIO_SOURCE_REGISTER

    +

    INTERFACE_DIO_SELECT

    +

    DIO_OVERRIDE

    +

    SW_DIO_CONTROL

    +
    +
    +

    + + + DMA_REGMAP +

    +

    + + + XILINX_DMA_REGISTERS +

    +
    +
    +
    +

    + + + ETH_DMA_CTRL_REGMAP +

    +

    + + + ETH_DMA_CTRL +

    +
    +

    AXI_DMA_CTRL

    +

    ETH_IO_CTRL

    +
    +
    +

    + + + GLOBAL_REGS_REGMAP +

    +

    + + + GLOBAL_REGS +

    +
    +

    COMPAT_NUM_REG

    +

    DATESTAMP_REG

    +

    GIT_HASH_REG

    +

    SCRATCH_REG

    +

    DEVICE_ID_REG

    +

    RFNOC_INFO_REG

    +

    CLOCK_CTRL_REG

    +

    PPS_CTRL_REG

    +

    CHDR_CLK_RATE_REG

    +

    CHDR_CLK_COUNT_REG

    +

    BUILD_SEED_REG

    +

    GPS_CTRL_REG

    +

    GPS_STATUS_REG

    +

    DBOARD_CTRL_REG

    +

    DBOARD_STATUS_REG

    +

    NUM_TIMEKEEPERS_REG

    +

    SERIAL_NUM_LOW_REG

    +

    SERIAL_NUM_HIGH_REG

    +

    MFG_TEST_CTRL_REG

    +

    MFG_TEST_STATUS_REG

    +

    QSFP_PORT_0_0_INFO_REG

    +

    QSFP_PORT_0_1_INFO_REG

    +

    QSFP_PORT_0_2_INFO_REG

    +

    QSFP_PORT_0_3_INFO_REG

    +

    QSFP_PORT_1_0_INFO_REG

    +

    QSFP_PORT_1_1_INFO_REG

    +

    QSFP_PORT_1_2_INFO_REG

    +

    QSFP_PORT_1_3_INFO_REG

    +
    +
    +

    + + + GPIO_ATR_REGMAP +

    +

    + + + GPIO_ATR_REGS +

    +
    +

    ATR_STATE

    +

    CLASSIC_ATR_CONFIG

    +

    ATR_OPTION_REGISTRER

    +

    GPIO_DIR

    +

    GPIO_DISABLED

    +

    GPIO_IN

    +
    +
    +

    + + + JTAG_REGMAP +

    +

    + + + JTAG_REGS +

    +
    +

    TX_DATA

    +

    STB_DATA

    +

    CONTROL

    +

    RX_DATA

    +
    +
    +

    + + + MB_CPLD_PL_REGMAP +

    +

    + + + MB_CPLD_PL_WINDOWS +

    +
    +

    PL_REGISTERS

    +

    JTAG_DB0

    +

    JTAG_DB1

    +
    +
    +

    + + + NIXGE_REGMAP +

    +

    + + + XGE_MAC_REGS +

    +
    +

    PORT_INFO

    +

    MAC_CTRL_STATUS

    +

    MAC_PHY_STATUS

    +

    MAC_LED_CTL

    +

    ETH_MDIO_BASE

    +

    AURORA_OVERRUNS

    +

    AURORA_CHECKSUM_ERRORS

    +

    AURORA_BIST_CHECKER_SAMPS

    +

    AURORA_BIST_CHECKER_ERRORS

    +
    +

    + + + XGE_MAC_WINDOW +

    +
    +

    XGE_MAC

    +
    +
    +

    + + + PL_CPLD_BASE_REGMAP +

    +

    + + + MB_CPLD_LED_REGS +

    +
    +

    LED_REGISTER

    +
    +

    + + + PL_CMI_REGS +

    +
    +

    CABLE_PRESENT_REG

    +
    +

    + + + PL_CPLD_BASE_REGS +

    +
    +

    SIGNATURE_REGISTER

    +

    REVISION_REGISTER

    +

    OLDEST_COMPATIBLE_REVISION_REGISTER

    +

    SCRATCH_REGISTER

    +

    GIT_HASH_REGISTER

    +
    +
    +

    + + + PL_CPLD_REGMAP +

    +

    + + + PL_CPLD_WINDOWS +

    +
    +

    BASE

    +

    MB_CPLD

    +

    DB0_CPLD

    +

    DB1_CPLD

    +
    +
    +

    + + + PL_DMA_MASTER_REGMAP +

    +

    + + + HPC0_DMA +

    +
    +

    AXI_HPC0_WINDOW

    +
    +

    + + + HPC1_DMA +

    +
    +

    AXI_HPC1_WINDOW

    +
    +
    +

    + + + PS_CPLD_BASE_REGMAP +

    +

    + + + DIO_REGS +

    +
    +

    DIO_DIRECTION_REGISTER

    +
    +

    + + + PS_CMI_REGS +

    +
    +

    SERIAL_NUM_LOW_REG

    +

    SERIAL_NUM_HIGH_REG

    +

    CMI_CONTROL_STATUS

    +
    +

    + + + PS_CONTROL_REGS +

    +
    +

    PL_DB_REGISTER

    +
    +

    + + + PS_CPLD_BASE_REGS +

    +
    +

    SIGNATURE_REGISTER

    +

    REVISION_REGISTER

    +

    OLDEST_COMPATIBLE_REVISION_REGISTER

    +

    SCRATCH_REGISTER

    +

    GIT_HASH_REGISTER

    +
    +
    +

    + + + PS_POWER_REGMAP +

    +

    + + + PS_POWER_REGS +

    +
    +

    IPASS_POWER_REG

    +

    OSC_POWER_REG

    +
    +
    +

    + + + QSFP_REGMAP +

    +

    + + + QSFP_WINDOWS +

    +
    +

    ETH_DMA

    +

    NIXGE

    +

    UIO

    +

    CMAC

    +
    +
    +

    + + + RADIO_CTRLPORT_REGMAP +

    +

    + + + RADIO_CTRLPORT_WINDOWS +

    +
    +

    DB_WINDOW

    +

    RFDC_TIMING_WINDOW

    +

    DIO_WINDOW

    +
    +
    +

    + + + RADIO_DIO_REGMAP +

    +

    + + + DIO_SOURCES +

    +
    +

    RADIO_GPIO_ATR_REGS

    +

    DIO_SOURCE_CONTROL

    +

    DIGITAL_IFC_REGS

    +
    +
    +

    + + + RECONFIG_REGMAP +

    +

    + + + RECONFIG_REGS +

    +
    +

    enum FLASH_PRIMARY_IMAGE_ADDR_ENUM

    +

    FLASH_STATUS_REG

    +

    FLASH_CONTROL_REG

    +

    FLASH_ADDR_REG

    +

    FLASH_WRITE_DATA_REG

    +

    FLASH_READ_DATA_REG

    +

    FLASH_CFM0_START_ADDR_REG

    +

    FLASH_CFM0_END_ADDR_REG

    +
    +
    +

    + + + RFDC_REGS_REGMAP +

    +

    + + + RFDC_REGS +

    +
    +

    enum FABRIC_DSP_BW_ENUM

    +

    MMCM

    +

    INVERT_DB0_IQ_REG

    +

    INVERT_DB1_IQ_REG

    +

    MMCM_RESET_REG

    +

    RF_RESET_CONTROL_REG

    +

    RF_RESET_STATUS_REG

    +

    RF_AXI_STATUS_REG

    +

    FABRIC_DSP_REG

    +

    CALIBRATION_DATA

    +

    CALIBRATION_ENABLE

    +

    THRESHOLD_STATUS

    +

    RF_PLL_CONTROL_REG

    +

    RF_PLL_STATUS_REG

    +

    ADC_TILEMAP_REG

    +

    DAC_TILEMAP_REG

    +

    RFDC_INFO_REG

    +
    +
    +

    + + + RFDC_TIMING_REGMAP +

    +

    + + + RFDC_TIMING_REGS +

    +
    +

    NCO_RESET_REG

    +

    GEARBOX_RESET_REG

    +
    +
    +

    + + + SPI_REGMAP +

    +

    + + + SPI_REGS +

    +
    +

    RX_DATA_LOW

    +

    RX_DATA_HIGH

    +

    TX_DATA_LOW

    +

    TX_DATA_HIGH

    +

    CONTROL

    +

    CLOCK_DIVIDER

    +

    SLAVE_SELECT

    +
    +
    +

    + + + UIO_REGMAP +

    +

    + + + UIO_REGS +

    +
    +

    IP

    +

    UDP

    +

    BRIDGE_MAC_LSB

    +

    BRIDGE_MAC_MSB

    +

    BRIDGE_IP

    +

    BRIDGE_UDP

    +

    BRIDGE_ENABLE

    +

    CHDR_DROPPED

    +

    CPU_DROPPED

    +

    PAUSE

    +
    +
    +

    + + + VERSIONING_REGS_REGMAP +

    +

    + + + VERSIONING_CONSTANTS +

    +
    +

    enum CPLD_IFC_VERSION

    +

    enum DB_GPIO_IFC_VERSION

    +

    enum FPGA_VERSION

    +

    enum RF_CORE_100M_VERSION

    +

    enum RF_CORE_400M_VERSION

    +
    +

    + + + VERSIONING_REGS +

    +
    +

    enum COMPONENTS_INDEXES

    +

    CURRENT_VERSION

    +

    OLDEST_COMPATIBLE_VERSION

    +

    VERSION_LAST_MODIFIED

    +

    RESERVED

    +
    +
    +

    + + + XGE_MAC_REGMAP +

    +

    + + + OPENCORE_XGE_REGISTERS +

    +
    +
    +
    +
    + + \ No newline at end of file diff --git a/top/x400/doc/X410/X410_FPGA_right.htm b/top/x400/doc/X410/X410_FPGA_right.htm new file mode 100644 index 0000000..0b6de9a --- /dev/null +++ b/top/x400/doc/X410/X410_FPGA_right.htm @@ -0,0 +1,25951 @@ + + + + + + + + +
    + +

    X410_FPGA

    + This documentation provides a description of the different register spaces available + for the USRP X4xx Open-Source FPGA target implementation, accessible through the + embedded ARM A53 processor in the RFSoC chip, and other UHD hosts. +

    The top is defined in HDL source file x410_rfdc_regs.v, x4xx.v.

    +

    P5 Content

    +

    Register map supplied for open-source projects

    +

    "All content provided is Copyright 2023 National Instruments Corporation. +For information on NI trademark guidelines, please see http://www.ni.com/legal/trademarks/. For the NI Patent Notice, please see http://www.ni.com/legal/patents/." +

    +
    + +

    ports

    + This section lists all common Processing System ports through + which the register maps in this project are accessed. Each input + port to the fabric will point to a regmap. +
    + + +

    Port ARM_M_AXI_HPM0 (input)

    + +

    + + Target Regmap = AXI_HPM0_REGMAP + +

    + +
    + +This is the main AXI4-Lite master interface that the PS + exposes to the kernel to interact with the FPGA fabric. + There are multiple endpoints connected to this interface. + +
    + +

    + This port is defined in HDL source file x410_rfdc_regs.v. +

    + +
    + +
    + + +

    Port ARM_S_AXI_HPC0 (output)

    + +

    + + Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW + +

    + +
    + +This is one of the two cache-coherent AXI slave ports available to + communicate from the fabric (master) to the PS (slave). + +
    + +

    + This port is defined in HDL source file x410_rfdc_regs.v. +

    + +
    + +
    + + +

    Port ARM_S_AXI_HPC1 (output)

    + +

    + + Source Window = PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW + +

    + +
    + +This is one of the two cache-coherent AXI slave ports available to + communicate from the fabric (master) to the PS (slave). + +
    + +

    + This port is defined in HDL source file x410_rfdc_regs.v. +

    + +
    + +
    + + +

    Port ARM_SPI1_CS3 (input)

    + +

    + + Target Regmap = MB_CPLD_PS_REGMAP + +

    + +
    + +This is the SPI1 interface + (see Zynq UltraScale+ Devices Register Reference) + of the PS. + With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.
    + The request format on SPI is defined as.
    + Write request: +
      +
    • 1'b1 = write +
    • 15 bit address +
    • 32 bit data (MOSI) +
    • 8 bit processing gap +
    • 5 bit padding +
    • 1 bit ack +
    • 2 bit status +
    + Read request: +
      +
    • 1'b0 = read +
    • 15 bit address +
    • 8 bit processing gap +
    • 32 bit data (MISO) +
    • 5 bit padding +
    • 1 bit ack +
    • 2 bit status +
    + +
    + +

    + This port is defined in HDL source file x410_rfdc_regs.v. +

    + +
    + +
    + +
    + +
    + +

    AXI_HPM0_REGMAP

    +
    +

    This is the map for the register space that the Processing System's +M_AXI_HPM0_FPD port (AXI4 master interface) has access to. +This port has a 40-bit address bus.

    +

    COMMON

    +
    +
    +
    + + +

    Offset 0x80000000: RPU Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    RPU
      offset=0x80000000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x80000000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    Space reserved for RPU access

    + +
    + +
    + +
    + + +

    Offset 0x1000000000: JTAG_ENGINE Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    JTAG_ENGINE
      offset=0x1000000000
      size=0x1000 (4 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000000000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    Register space for the JTAG engine for MB CPLD programming.

    + +
    + +
    + +
    + + +

    Offset 0x100003F000: RESERVED Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    RESERVED
      offset=0x100003F000
      size=0x1000 (4 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x100003F000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    Register space reserved for future use.

    + +
    + +
    + +
    + + +

    Offset 0x1000080000: MPM_ENDPOINT Window (R|W)

    +

      Target regmap = PL_CPLD_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    MPM_ENDPOINT
      offset=0x1000080000
      size=0x20000 (128 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000080000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    MPM endpoint fro MB/DB communication.

    + +
    + +
    + +
    + + +

    Offset 0x10000A0000: CORE_REGS Window (R|W)

    +

      Target regmap = CORE_REGS_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    CORE_REGS
      offset=0x10000A0000
      size=0x4000 (16 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    Register space reserved for mboard-regs (Core).

    + +
    + +
    + +
    + + +

    Offset 0x10000A4000: INT_ETH_DMA Window (R|W)

    +

      Target regmap = ETH_DMA_CTRL_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    INT_ETH_DMA
      offset=0x10000A4000
      size=0x6000 (24 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A4000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    AXI DMA engine for internal Ethernet interface.

    + +
    + +
    + +
    + + +

    Offset 0x10000AA000: INT_ETH_REGS Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    INT_ETH_REGS
      offset=0x10000AA000
      size=0x2000 (8 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000AA000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    Misc. registers for internal Ethernet.

    + +
    + +
    + +
    + + +

    Offset 0x1000100000: RFDC Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    RFDC
      offset=0x1000100000
      size=0x40000 (256 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000100000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    Register space occupied by the Xilinx RFDC IP block.

    + +
    + +
    + +
    + + +

    Offset 0x1000140000: RFDC_REGS Window (R|W)

    +

      Target regmap = RFDC_REGS_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    RFDC_REGS
      offset=0x1000140000
      size=0x20000 (128 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000140000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +
    +

    Register space for RFDC control/status registers.

    + +
    + +
    + +
    + +

    UHD_ONLY

    +
    +
      +
    • 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
      • +
    • 0_1 indicates QSFP0 - Lane1
      • +
    • 0_2 indicates QSFP0 - Lane2
      • +
    • 0_3 indicates QSFP0 - Lane3
      • +
    • 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
      • +
    • 1_1 indicates QSFP1 - Lane1
      • +
    • 1_2 indicates QSFP1 - Lane2
      • +
    • 1_3 indicates QSFP1 - Lane3
      • +
    +
    + + +

    Offset 0x1200000000: QSFP_0_0 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_0_0
      offset=0x1200000000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200000000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x1200010000: QSFP_0_1 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_0_1
      offset=0x1200010000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200010000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x1200020000: QSFP_0_2 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_0_2
      offset=0x1200020000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200020000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x1200030000: QSFP_0_3 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_0_3
      offset=0x1200030000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200030000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x1200040000: QSFP_1_0 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_1_0
      offset=0x1200040000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200040000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x1200050000: QSFP_1_1 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_1_1
      offset=0x1200050000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200050000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x1200060000: QSFP_1_2 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_1_2
      offset=0x1200060000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200060000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x1200070000: QSFP_1_3 Window (R|W)

    +

      Target regmap = QSFP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + + +
    QSFP_1_3
      offset=0x1200070000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200070000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + +
    + +
    + +

    MB_CPLD_PS_REGMAP

    +
    +

    This register map is available using the PS CPLD SPI interface.

    +

    MB_CPLD_PS_WINDOWS

    +
    +
    +
    + + +

    Offset 0x0000: PS_REGISTERS Window (R|W)

    +

      Target regmap = PS_CPLD_BASE_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + + +
    PS_REGISTERS
      offset=0x0000
      size=0x40 (64 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x000000 + +
    + +

    + +

    This window is defined in HDL source file mb_cpld.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x0040: RECONFIG Window (R|W)

    +

      Target regmap = RECONFIG_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + + +
    RECONFIG
      offset=0x0040
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x000040 + +
    + +

    + +

    This window is defined in HDL source file mb_cpld.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x0060: POWER_REGISTERS Window (R|W)

    +

      Target regmap = PS_POWER_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + + +
    POWER_REGISTERS
      offset=0x0060
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x000060 + +
    + +

    + +

    This window is defined in HDL source file mb_cpld.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + +

    PS_SPI_ENDPOINTS

    +
    +
    +
    + + +

    SPI_ENDPOINT Enumeration

    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    0 +

    PS_CS_MB_CPLD

    + +

    +
    + +
    1 +

    PS_CS_LMK32

    + +

    +
    + +
    2 +

    PS_CS_TPM

    + +

    +
    + +
    3 +

    PS_CS_PHASE_DAC

    + +

    +
    + +
    4 +

    PS_CS_DB0_CAL_EEPROM

    + +

    +
    + +
    5 +

    PS_CS_DB1_CAL_EEPROM

    + +

    +
    + +
    6 +

    PS_CS_CLK_AUX_DB

    + +

    +
    + +
    7 +

    PS_CS_IDLE

    + +

    +
    + +
    + +

    + This enumerated type is defined in HDL source file mb_cpld.v. +

    + +
    + +
    + +
    + +
    + +

    CMAC_REGMAP

    +
    +
    +

    XILINX_CMAC_REGISTERS

    +
    +

    100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.

    +
      +
    • http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
      • +
    +
    + +
    + +
    + +

    CONSTANTS_REGMAP

    + +

    CONSTANTS_GROUP

    + Basic registers containing version and capabilities information. +
    + + +

    CONSTANTS_ENUM Enumeration

    +This enumeration is used to create the constants held in the basic registers. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    1731576710x0A522D27 +

    PS_CPLD_SIGNATURE

    + +
    5380590280x20122114 +

    OLDEST_CPLD_REVISION

    + +
    5709506760x22080414 +

    CPLD_REVISION

    + +
    10714061510x3FDC5C47 +

    PL_CPLD_SIGNATURE

    + +
    + +

    + This enumerated type is defined in HDL source file mb_cpld.v. +

    + +
    + +
    + +
    + +
    + +

    CORE_REGS_REGMAP

    + This is the map for the registers that the CORE_REGS window has access to + from the ARM_AXI_HPM0_FPD port. + + The registers contained here conform the mboard-regs node that MPM uses + to manage general FPGA control/status calls, such as versioning, + timekeeper, GPIO, etc. + + The following diagram shows how the communication bus interacts with the + modules in CORE_REGS. +

    CORE_REGS

    + +
    + + +

    Offset 0x0000: GLOBAL_REGS Window (R|W)

    +

      Target regmap = GLOBAL_REGS_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + + +
    GLOBAL_REGS
      offset=0x0000
      size=0xC00 (3 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0000 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Window to access global registers in the FPGA. + +
    + +
    + +
    + + +

    Offset 0x0C00: VERSIONING_REGS Window (R|W)

    +

      Target regmap = VERSIONING_REGS_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + + +
    VERSIONING_REGS
      offset=0x0C00
      size=0x400 (1 Kbyte)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0C00 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Window to access versioning registers in the FPGA. + +
    + +
    + +
    + + +

    Offset 0x1000: TIMEKEEPER_A Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + + +
    TIMEKEEPER_A
      offset=0x1000
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A1000 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Window to access the timekeeper register map. + +
    + +
    + +
    + + +

    Offset 0x1100: TIMEKEEPER_B Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + + +
    TIMEKEEPER_B
      offset=0x1100
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A1100 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Window to access the timekeeper register map. + +
    + +
    + +
    + + +

    Offset 0x2000: DIO Window (R|W)

    +

      Target regmap = DIO_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + + +
    DIO
      offset=0x2000
      size=0x40 (64 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2000 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Window to access the DIO register map. + +
    + +
    + +
    + + + +
    + +

    CPLD_INTERFACE_REGMAP

    + +

    CPLD_INTERFACE_REGS

    + Basic registers containing version and capabilities information. +
    + + +

    Offset 0x0000: SIGNATURE_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|BASE
      0x000000
    + +    		 + + + + +
    SIGNATURE_REGISTER
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000080000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file cpld_interface_regs.v.

    + +
    + +
    + +Contains the product's signature. + +
    + + + + + + + + + +
    BitsName
    31..0 +

    PRODUCT_SIGNATURE

    +

    fixed value 0xCB1D1FAC

    + +
    + +
    + +
    + + +

    Offset 0x000C: SCRATCH_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|BASE
      0x000000
    + +    		 + + + + +
    SCRATCH_REGISTER
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x100008000C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file cpld_interface_regs.v.

    + +
    + +
    + +Read/write register for general software use. + +
    + +
    + +
    + +

    CPLD_SPI_CONTROL_REGS

    + Registers to control the SPI clock frequency of the CPLD interfaces. + The resulting clock frequency is calculated by fPRC2(divider+1). +
    + Note that the PLL Reference Clock (PRC) is depending on the RF clocks. +
    + + +

    Offset 0x0020: MOTHERBOARD_CPLD_DIVIDER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|BASE
      0x000000
    + +    		 + + + + +
    MOTHERBOARD_CPLD_DIVIDER
      offset=0x0020
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000080020 + +
    + +

    + +

    Initial Value = 0x00000002 +

    + +

    This register is defined in HDL source file cpld_interface_regs.v.

    + +
    + +
    + +Clock divider used for SPI transactions targeting the MB CPLD.
    + Minimum required value is 2. + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..0 +

    MB_DIVIDER   (initialvalue=2)

    +

    Divider value

    + +
    + +
    + +
    + + +

    Offset 0x0024: DAUGHTERBOARD_CPLD_DIVIDER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|BASE
      0x000000
    + +    		 + + + + +
    DAUGHTERBOARD_CPLD_DIVIDER
      offset=0x0024
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000080024 + +
    + +

    + +

    Initial Value = 0x00000005 +

    + +

    This register is defined in HDL source file cpld_interface_regs.v.

    + +
    + +
    + +Clock divider used for SPI transactions targeting any of the DB CPLDs.
    + Minimum required value is 5. + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..0 +

    DB_DIVIDER   (initialvalue=5)

    +

    Divider value

    + +
    + +
    + +
    + +

    IPASS_REGS

    + +
    + + +

    Offset 0x0010: IPASS_CONTROL Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|BASE
      0x000000
    + +    		 + + + + +
    IPASS_CONTROL
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000080010 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file cpld_interface_regs.v.

    + +
    + +
    + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    IPASS_ENABLE_TRANSFER

    +

    If 1 enables the forwarding of iPass cable present signal to MB CPLD + using ctrlport requests. On change from 0 to 1 the current status is + transferred to the MB CPLD via SPI ctrlport request initially.

    + +
    + +
    + +
    + +
    + +
    + +

    DIG_IFC_REGMAP

    + +

    SPI_OVER_GPIO_REGS

    + +
    + + +

    Offset 0x0000: SPI_SLAVE_CONFIG(3:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
      0x002000
    + +    		 + + + + +
    SPI_SLAVE_CONFIG
      offset=0x0000 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x00E000 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file x4xx_gpio_spi.v.
    +It uses RegType SPI_SETUP which is defined in HDL source file x4xx_gpio_spi.v.

    + +
    + +
    + +Controls SPI Transaction
    +Set of configuration registers for the supported slaves. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27 +

    MOSI_EDGE   (initialvalue=0)

    +

    Controls the edge in which the MOSI line is updated.
    + 0 = falling edge of SCLK.
    + 1 = rising edge of SCLK.

    + +
    26 +

    MISO_EDGE   (initialvalue=0)

    +

    Controls the edge in which the MISO line is latched.
    + 0 = falling edge of SCLK.
    + 1 = rising edge of SCLK.

    + +
    25..20 +

    SPI_LENGTH   (initialvalue=0)

    +

    Indicates the length of SPI transactions to this slave.

    + +
    19..15 +

    SLAVE_CS   (initialvalue=0)

    +

    Indicates which GPIO line to use for the CS signal.
    + 0-11 : Port A GPIO
    + 16-27: Port B GPIO

    + +
    14..10 +

    SLAVE_MISO   (initialvalue=0)

    +

    Indicates which GPIO line to use for the MISO signal.
    + 0-11 : Port A GPIO
    + 16-27: Port B GPIO

    + +
    9..5 +

    SLAVE_MOSI   (initialvalue=0)

    +

    Indicates which GPIO line to use for the MOSI signal.
    + 0-11 : Port A GPIO
    + 16-27: Port B GPIO

    + +
    4..0 +

    SLAVE_CLK   (initialvalue=0)

    +

    Indicates which GPIO line to use for the SCLK signal.
    + 0-11 : Port A GPIO
    + 16-27: Port B GPIO

    + +
    + +
    + +
    + + +

    Offset 0x0010: SPI_TRANSACTION_CONFIG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
      0x002000
    + +    		 + + + + +
    SPI_TRANSACTION_CONFIG
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x00E010 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_spi.v.

    + +
    + +
    + +Controls clock rate and target for subsequent SPI transactions. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..18 +

    Reserved

    +

    + +
    17..16 +

    SPI_SLAVE_SELECT   (initialvalue=0)

    +

    + +
    15..0 +

    SPI_CLK_DIV   (initialvalue=0)

    +

    Controls the rate for subsequent SPI transactions. SCLK = DataClk/[(SPI_CLK_DIV+1)]

    + +
    + +
    + +
    + + +

    Offset 0x0014: SPI_TRANSACTION_GO Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
      0x002000
    + +    		 + + + + +
    SPI_TRANSACTION_GO
      offset=0x0014
    + +    		 + + + + + +
    + + +Total Offset =
      0x00E014 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_spi.v.

    + +
    + +
    + +Starts a SPI transaction + +
    + + + + + + + + + +
    BitsName
    31..0w +

    SPI_DATA   (initialvalue=0)

    +

    Payload to be sent for the SPI transaction. If the payload is shorter than 32 bits, + it must be aligned to the MSbs in this field. LSbs are ignored in this scenario.

    + +
    + +
    + +
    + + +

    Offset 0x0018: SPI_STATUS Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
      0x002000
    + +    		 + + + + +
    SPI_STATUS
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x00E018 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_spi.v.

    + +
    + +
    + +Contains the status of the SPI engine. + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..25 +

    Reserved

    +

    + +
    24 +

    SPI_READY   (initialvalue=0)

    +

    Indicates the SPI engine is ready to start a new SPI transaction.

    + +
    23..0 +

    SPI_RESPONSE   (initialvalue=0)

    +

    Records the response of the last completed SPI transaction.

    + +
    + +
    + +
    + + +

    Offset 0x001C: CONTROLLER_INFO Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIGITAL_IFC_REGS
      0x002000
    + +    		 + + + + +
    CONTROLLER_INFO
      offset=0x001C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00E01C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_gpio_spi.v.

    + +
    + +
    + +Contains information pertaining this SPI controller block. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3..0 +

    SLAVE_COUNT

    +

    Indicates the number SPI slaves configurable by the controller.

    + +
    + +
    + +
    + +
    + +
    + +

    DIO_REGMAP

    + +

    DIO_REGS

    + Registers to control the GPIO buffer direction on the FPGA connected to + the DIO board. Further registers enable different sources to control and + read the GPIO lines as master. The following diagram shows how source + selection multiplexers are arranged, as well as an indicator for the + register that control them.
    + Front-Panel Programmable GPIOs
    + Make sure the GPIO lines between FPGA and GPIO board are not driven by + two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately. +
    + + +

    Offset 0x0000: DIO_MASTER_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    DIO_MASTER_REGISTER
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2000 + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D000 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Sets whether the DIO signal line is driven by this register interface + or the user application.
    + 0 = user application is master, 1 = output of SW_DIO_CONTROL is master + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0004: DIO_DIRECTION_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    DIO_DIRECTION_REGISTER
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2004 + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D004 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Set the direction of FPGA buffer connected to DIO ports on the DIO board.
    + Each bit represents one signal line. 0 = line is an input to the FPGA, + 1 = line is an output driven by the FPGA. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0008: DIO_INPUT_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    DIO_INPUT_REGISTER
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2008 + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D008 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Status of each bit at the FPGA input. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x000C: DIO_OUTPUT_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    DIO_OUTPUT_REGISTER
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A200C + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D00C + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Controls the values on each DIO signal line in case the line master is + set to PS in DIO_MASTER_REGISTER. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0010: DIO_SOURCE_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    DIO_SOURCE_REGISTER
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2010 + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D010 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Controls whether the DIO lines reflect the state of DIO_MASTER_REGISTER + or the radio blocks. 0 = DIO_MASTER_REGISTER, + 1 = Radio block output(DIO_OVERRIDE) + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0014: RADIO_SOURCE_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    RADIO_SOURCE_REGISTER
      offset=0x0014
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2014 + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D014 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Controls which radio block to use the ATR state from to determine the + state of the DIO lines. + 0 = Radio#0 + 1 = Radio#1 + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0018: INTERFACE_DIO_SELECT Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    INTERFACE_DIO_SELECT
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2018 + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D018 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Controls which of the two available digital interfaces controls the DIO lines. + 0 = Digital interface from Radio#0, + 1 = Digital Interface from Radio#1. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x001C: DIO_OVERRIDE Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    DIO_OVERRIDE
      offset=0x001C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A201C + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D01C + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Controls whether the radio input to the DIO_SOURCE_REGISTER mux + connects to the ATR control or a Digital interface block. The output + of the mux controlled by this bit goes to DIO_SOURCE_REGISTER. + 0 = Drive the ATR state(RADIO_SOURCE_REGISTER), 1 = Drive + Digital interface block(Output of INTERFACE_DIO_SELECT). + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0020: SW_DIO_CONTROL Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|DIO
      0x002000
    + +    		 + + + + +
    SW_DIO_CONTROL
      offset=0x0020
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A2020 + +
    + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|DIO_SOURCE_CONTROL
      0x001000
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D020 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_dio.v.
    +It uses RegType DIO_CONTROL_REG which is defined in HDL source file x4xx_dio.v.

    + +
    + +
    + +Holds a single bit setting for DIO lines in both ports. One bit per pin.
    +Controls which source is forwarded to the DIO_MASTER_REGISTER mux. + This configuration is applied independently for each DIO line. + 0 = MPM Ctrlport endpoint, 1 = PS Netlist DIO signal. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_PORT_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_PORT_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + +
    + +
    + +

    DMA_REGMAP

    +
    +
    +

    XILINX_DMA_REGISTERS

    +
    +

    Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11

    +
      +
    • https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
      • +
    +
    + +
    + +
    + +

    ETH_DMA_CTRL_REGMAP

    + This is the map that the nixge driver uses in Ethernet DMA to + move data between the Processing System's architecture and the fabric. + This map is a combination of two main components: a Xilix AXI DMA engine + and some registers for MAC/PHY control. +

    ETH_DMA_CTRL

    + +
    + + +

    Offset 0x0000: AXI_DMA_CTRL Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|INT_ETH_DMA
      0x10000A4000
    + +    		 + + + + + +
    AXI_DMA_CTRL
      offset=0x0000
      size=0x4000 (16 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A4000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +Refer to Xilinx' AXI DMA v7.1 IP product guide for further + information on this register map: + https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf + +
    + +
    + +
    + + +

    Offset 0x4000: ETH_IO_CTRL Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|INT_ETH_DMA
      0x10000A4000
    + +    		 + + + + + +
    ETH_IO_CTRL
      offset=0x4000
      size=0x2000 (8 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A8000 + +
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +MAC/PHY control for the Ethernet interface. + +
    + +
    + +
    + +
    + +
    + +

    GLOBAL_REGS_REGMAP

    + +

    GLOBAL_REGS

    + +
    + + +

    Offset 0x0000: COMPAT_NUM_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    COMPAT_NUM_REG
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Revision number + +
    + + + + + + + + + + + + + + +
    BitsName
    31..16 +

    COMPAT_MAJOR

    +

    + +
    15..0 +

    COMPAT_MINOR

    +

    + +
    + +
    + +
    + + +

    Offset 0x0004: DATESTAMP_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    DATESTAMP_REG
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0004 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Build datestamp (32-bit) + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..27 +

    DAY

    +

    + +
    26..23 +

    MONTH

    +

    + +
    22..17 +

    YEAR

    +

    This is the year number after 2000 (e.g. 2019 = d19).

    + +
    16..12 +

    HOUR

    +

    + +
    11..6 +

    MINUTES

    +

    + +
    5..0 +

    SECONDS

    +

    + +
    + +
    + +
    + + +

    Offset 0x0008: GIT_HASH_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    GIT_HASH_REG
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0008 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Git hash of source commit. + +
    + +
    + +
    + + +

    Offset 0x000C: SCRATCH_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    SCRATCH_REG
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A000C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Scratch register for testing. + +
    + +
    + +
    + + +

    Offset 0x0010: DEVICE_ID_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    DEVICE_ID_REG
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0010 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Register that contains the motherboard's device ID. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31 +

    PCIE_PRESENT_BIT

    +

    Set to 1 if PCI-Express core is present in FPGA design.

    + +
    30..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..0 +

    DEVICE_ID

    +

    + +
    + +
    + +
    + + +

    Offset 0x0014: RFNOC_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    RFNOC_INFO_REG
      offset=0x0014
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0014 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Register that provides information on the RFNoC protocol. + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..16 +

    CHDR_WIDTH

    +

    + +
    15..8 +

    RFNOC_PROTO_MAJOR

    +

    + +
    7..0 +

    RFNOC_PROTO_MINOR

    +

    + +
    + +
    + +
    + + +

    Offset 0x0018: CLOCK_CTRL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    CLOCK_CTRL_REG
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0018 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Control register for clocking resources. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    PPS_BRC_DELAY

    +

    Number of base reference clock cycles from appearance of the PPS + rising edge to the occurrence of the aligned edge of base reference + clock and PLL reference clock at the sample PLL output. This number + is the sum of the actual value based on PLL_SYNC_DELAY (also + accumulate the fixed amount of clock cycles) and if any the number of + cycles the SPLL requires from issuing of the SYNC signal to the + aligned edge (with LMK04832 = 0).
    + The number written to this register has to be reduced by 1 due to + HDL implementation.

    + +
    23..16 +

    PLL_SYNC_DELAY

    +

    Due to the HDL implementation the rising edge of the SYNC signal for + the LMK04832 is generated 2 clock cycles after the PPS rising edge. + This delay can be further increased by setting this delay value + (e.g. PLL_SYNC_DELAY=3 will result in a total delay of 5 clock cycles).
    + In case two X400 devices are connected using the PPS and reference clock the master delay value needs to be 3 clock cycles + higher than the slave delay value to align the LMK sync edges in time.

    + +
    15..10 +

    Reserved

    +

    + +
    9r +

    PLL_SYNC_DONE

    +

    Indicates the success of the PLL reset started by PLL_SYNC_TRIGGER. Reset on deassertion of PLL_SYNC_TRIGGER.

    + +
    8w +

    PLL_SYNC_TRIGGER

    +

    Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge. + There is no self reset on this trigger. + Keep this trigger asserted until PLL_SYNC_DONE is asserted.

    + +
    7..6 +

    Reserved

    +

    + +
    5..4 +

    TRIGGER_IO_SELECT   (initialvalue=TRIG_IO_INPUT)

    +

    IMPORTANT! SW must ensure any TRIG_IO consumers (downstream devices) ignore + and/or re-sync after enabling this port, since the output-enable is basically + asynchronous to the actual TRIG_IO driver.

    + +

    + The values for this bitfield are in the TRIG_IO_ENUM table. + (show here) +

    +
    + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    0 +

    TRIG_IO_INPUT

    + +
    1 +

    TRIG_IO_PPS_OUTPUT

    + +
    + +

    + This enumerated type is defined in HDL source file x4xx_global_regs.v. +

    + +
    + +
    + +
    3r +

    REFCLK_LOCKED

    +

    RESERVED. This bit is not implemented on X4xx and reads as 0.

    + +
    2 +

    REF_SELECT

    +

    RESERVED. This bit is not implemented on X4xx and reads as 0.

    + +
    1..0 +

    PPS_SELECT   (initialvalue=PPS_INT_25MHZ)

    +

    Select the source of the PPS signal. + For the internal generation the value depending on the base reference clock has to be chosen. + The external reference is taken from the PPS_IN pin and is independent of the base reference clock.

    + +

    + The values for this bitfield are in the PPS_ENUM table. + (show here) +

    +
    + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    0 +

    PPS_INT_25MHZ

    + +
    1 +

    PPS_INT_10MHZ

    + +
    2 +

    PPS_EXT

    + +
    + +

    + This enumerated type is defined in HDL source file x4xx_global_regs.v. +

    + +
    + +
    + +
    + +
    + +
    + + +

    Offset 0x001C: PPS_CTRL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    PPS_CTRL_REG
      offset=0x001C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A001C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Control registers for PPS generation. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31 +

    PPS_RC_ENABLED

    +

    Enables the PPS signal in radio clock domain. Please make sure that + the values of PPS_BRC_DELAY, PPS_PRC_DELAY and @.PRC_RC_DIVIDER are + set before enabling this bit. It is recommended to disable the PPS + for changes on the other values. Use a wait time of at least 1 second + before changing this value to ensure the values are stable for the + next PPS edge.

    + +
    30 +

    Reserved

    +

    + +
    29..28 +

    PRC_RC0_DIVIDER

    +

    Clock multiplier used to generate radio clock 0 from PLL reference clock. + The value written to the register has to be reduced by 2 due to + HDL implementation.

    + +
    27..26 +

    PRC_RC1_DIVIDER

    +

    Clock multiplier used to generate radio clock 1 from PLL reference clock. + The value written to the register has to be reduced by 2 due to + HDL implementation.

    + +
    25..0 +

    PPS_PRC_DELAY

    +

    The number of PLL reference clock cycles from one aligned edge to the + desired aligned edge to issue the PPS in radio clock domain. This + delay is configurable to any aligned edge within a maximum delay of 1 + second (period of PPS).
    + The value written to the register has to be reduced by 4 due to + HDL implementation.

    + +
    + +
    + +
    + + +

    Offset 0x0020: CHDR_CLK_RATE_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    CHDR_CLK_RATE_REG
      offset=0x0020
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0020 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns the RFNoC bus clock rate (CHDR). + +
    + + + + + + + + + +
    BitsName
    31..0 +

    CHDR_CLK

    +

    + +
    + +
    + +
    + + +

    Offset 0x0024: CHDR_CLK_COUNT_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    CHDR_CLK_COUNT_REG
      offset=0x0024
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0024 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns the count value of a free-running counter driven by the RFNoC + CHDR bus clock. + +
    + +
    + +
    + + +

    Offset 0x0028: BUILD_SEED_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    BUILD_SEED_REG
      offset=0x0028
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0028 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Build seed used for this compilation. Making this value readable + ensures that compilation results are affected by the value in this + register. + +
    + +
    + +
    + + +

    Offset 0x0038: GPS_CTRL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    GPS_CTRL_REG
      offset=0x0038
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0038 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +RESERVED. This register is not implemented on X4xx. GPS is connected + to the PS via a UART. + +
    + +
    + +
    + + +

    Offset 0x003C: GPS_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    GPS_STATUS_REG
      offset=0x003C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A003C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +RESERVED. This register is not implemented on X4xx. GPS is connected + to the PS via a UART. + +
    + +
    + +
    + + +

    Offset 0x0040: DBOARD_CTRL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    DBOARD_CTRL_REG
      offset=0x0040
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0040 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +RESERVED. This register is not implemented on X4xx. + +
    + +
    + +
    + + +

    Offset 0x0044: DBOARD_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    DBOARD_STATUS_REG
      offset=0x0044
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0044 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +RESERVED. This register is not implemented on X4xx. + +
    + +
    + +
    + + +

    Offset 0x0048: NUM_TIMEKEEPERS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    NUM_TIMEKEEPERS_REG
      offset=0x0048
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0048 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Register that specifies the number of timekeepers in the core. + +
    + +
    + +
    + + +

    Offset 0x004C: SERIAL_NUM_LOW_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    SERIAL_NUM_LOW_REG
      offset=0x004C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A004C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Least significant bytes of 8 byte serial number + +
    + +
    + +
    + + +

    Offset 0x0050: SERIAL_NUM_HIGH_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    SERIAL_NUM_HIGH_REG
      offset=0x0050
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0050 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Most significant bytes of 8 byte serial number + +
    + +
    + +
    + + +

    Offset 0x0054: MFG_TEST_CTRL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    MFG_TEST_CTRL_REG
      offset=0x0054
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0054 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Control register for mfg_test functions. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..2 +

    Reserved

    +

    + +
    1 +

    MFG_TEST_EN_FABRIC_CLK

    +

    When enabled, routes data_clk to FPGA_REF_CLK output port. + When disabled, the FPGA_REF_CLK output is driven to 0.

    + +
    0 +

    MFG_TEST_EN_GTY_RCV_CLK

    +

    When enabled, routes data_clk to GTY_RCV_CLK output port. + When disabled, the GTY_RCV_CLK output is driven to 0.

    + +
    + +
    + +
    + + +

    Offset 0x0058: MFG_TEST_STATUS_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    MFG_TEST_STATUS_REG
      offset=0x0058
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0058 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Status register for mfg_test functions. + +
    + + + + + + + + + + + + + + +
    BitsName
    31..26 +

    Reserved

    +

    + +
    25..0 +

    MFG_TEST_FPGA_AUX_REF_FREQ

    +

    Report the time between rising edges on the FPGA_REF_CLK + input port in 40 MHz Clock ticks. If the count extends + to 1.2 seconds without an edge, the value reported is set + to zero.

    + +
    + +
    + +
    + + +

    Offset 0x0060: QSFP_PORT_0_0_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_0_0_INFO_REG
      offset=0x0060
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0060 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP0 Lane0. + +
    + +
    + +
    + + +

    Offset 0x0064: QSFP_PORT_0_1_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_0_1_INFO_REG
      offset=0x0064
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0064 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP0 Lane1. + +
    + +
    + +
    + + +

    Offset 0x0068: QSFP_PORT_0_2_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_0_2_INFO_REG
      offset=0x0068
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0068 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP0 Lane2. + +
    + +
    + +
    + + +

    Offset 0x006C: QSFP_PORT_0_3_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_0_3_INFO_REG
      offset=0x006C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A006C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP0 Lane3. + +
    + +
    + +
    + + +

    Offset 0x0070: QSFP_PORT_1_0_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_1_0_INFO_REG
      offset=0x0070
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0070 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP1 Lane0. + +
    + +
    + +
    + + +

    Offset 0x0074: QSFP_PORT_1_1_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_1_1_INFO_REG
      offset=0x0074
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0074 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP1 Lane1. + +
    + +
    + +
    + + +

    Offset 0x0078: QSFP_PORT_1_2_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_1_2_INFO_REG
      offset=0x0078
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A0078 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP1 Lane2. + +
    + +
    + +
    + + +

    Offset 0x007C: QSFP_PORT_1_3_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|GLOBAL_REGS
      0x000000
    + +    		 + + + + +
    QSFP_PORT_1_3_INFO_REG
      offset=0x007C
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A007C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_global_regs.v.

    + +
    + +
    + +Returns information from the QSFP1 Lane3. + +
    + +
    + +
    + +
    + +
    + +

    GPIO_ATR_REGMAP

    + +

    GPIO_ATR_REGS

    + Describes the behavior of GPIO lines when controlled by the ATR state. +
    + + +

    Offset 0x0000: ATR_STATE(15:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
      0x000000
    + +    		 + + + + +
    ATR_STATE
      offset=0x0000 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x00C000 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file x4xx_gpio_atr.v.
    +It uses RegType GPIO_ATR_STATE which is defined in HDL source file x4xx_gpio_atr.v.

    + +
    + +
    + +Holds a single bit setting for GPIO lines in both ports for a particular ATR sate
    +Describes GPIO behavior for the different ATR states. When ATR_OPTION + is set to use the DB states, TX and RX states for RF0 and RF1 are + combined to create a single vector. This creates 16 different + combinations, each with its own register. When ATR_OPTION is set to + classic ATR, offsets 0x00-0x03 in this register group will be driven + in accordance with the state of RF0, and offsets 0x04-0x07 will be + driven in accordance with the state of RF1. + CLASSIC ATR MAPPING: Idle[RF0:0x00; RF1:0x04], RX[RF0:0x01; RF1:0x05], + TX[RF0:0x02; RF1:0x06], FDX[RF0:0x03; RF1:0x07] + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    GPIO_STATE_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    GPIO_STATE_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0040: CLASSIC_ATR_CONFIG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
      0x000000
    + +    		 + + + + +
    CLASSIC_ATR_CONFIG
      offset=0x0040
    + +    		 + + + + + +
    + + +Total Offset =
      0x00C040 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_atr.v.

    + +
    + +
    + +Controls the RF state mapping of each GPIO line when classic + ATR mode is active. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    RF_SELECT_B   (initialvalue=0)

    +

    Set which RF channel's state to reflect in the pins of + HDMI connector B when ATR_OPTION is set to classic ATR. + Controlled in a per-pin basis. + 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) + 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    RF_SELECT_A   (initialvalue=0)

    +

    Set which RF channel's state to reflect in the pins for + HDMI connector A when ATR_OPTION is set to classic ATR. + Controlled in a per-pin basis. + 0 = RF0 State(GPIO_ATR_STATE 0x00-0x03) + 1 = RF1 State(GPIO_ATR_STATE 0x04-0x07)

    + +
    + +
    + +
    + + +

    Offset 0x0044: ATR_OPTION_REGISTRER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
      0x000000
    + +    		 + + + + +
    ATR_OPTION_REGISTRER
      offset=0x0044
    + +    		 + + + + + +
    + + +Total Offset =
      0x00C044 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_atr.v.

    + +
    + +
    + +Controls whether GPIO lines use the TX and RX state of an RF channel + (Classic ATR) or the daughterboard state the selector for the + ATR_STATE. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    ATR_OPTION   (initialvalue=0)

    +

    Sets the scheme in which RF states in the radio will control GPIO + lines. 0 = DB state is used. RF states are combined and the + GPIO state is driven based on all 16 ATR_STATE registers. + 1 = Each RF channel has its separate ATR state(Classic ATR). + Use register CLASSIC_ATR_CONFIG to indicate the RF channel + to which each GPIO line responds to.

    + +
    + +
    + +
    + + +

    Offset 0x0048: GPIO_DIR Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
      0x000000
    + +    		 + + + + +
    GPIO_DIR
      offset=0x0048
    + +    		 + + + + + +
    + + +Total Offset =
      0x00C048 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_atr.v.

    + +
    + +
    + +Controls the direction of each GPIO signal when controlled by the radio state. + 0 = GPIO pin set to input. 1 = GPIO pin set to output + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    GPIO_DIR_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    GPIO_DIR_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x004C: GPIO_DISABLED Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
      0x000000
    + +    		 + + + + +
    GPIO_DISABLED
      offset=0x004C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00C04C + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_atr.v.

    + +
    + +
    + +Disable ATR Control. DB state 0 will be reflected regardless of the ATR state. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    GPIO_DISABLED_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    GPIO_DISABLED_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0050: GPIO_IN Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + +
    RADIO_DIO_REGMAP|RADIO_GPIO_ATR_REGS
      0x000000
    + +    		 + + + + +
    GPIO_IN
      offset=0x0050
    + +    		 + + + + + +
    + + +Total Offset =
      0x00C050 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x4xx_gpio_atr.v.

    + +
    + +
    + +Reflects the logic state of each GPIO input. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    GPIO_IN_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    GPIO_IN_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + +
    + +
    + +

    JTAG_REGMAP

    +
    +
    +

    JTAG_REGS

    +
    +

    This register map is present for each JTAG module.

    +

    Basic operation would be:

    +
      +
    • poll ready until asserted
      • +
    • write / read data
      • +
    • write CONTROL register along with reset deasserted to start a transaction
      • +
    +

    For resetting the BITQ FSM, simply assert reset.

    +

    This operation seems a little strange, but it is what the axi_bitq driver +expects. This behavior has been implemented in previous products.

    +
    + + +

    Offset 0x0000: TX_DATA Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    + +    		 + + + + +
    TX_DATA
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088060 + +
    + +
    + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088080 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_jtag.v.

    + +
    + +
    + +
    +

    Data to be transmitted (TDI)

    + +
    + +
    + +
    + + +

    Offset 0x0004: STB_DATA Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    + +    		 + + + + +
    STB_DATA
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088064 + +
    + +
    + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088084 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_jtag.v.

    + +
    + +
    + +
    +

    Data to be transmitted (TMS)

    + +
    + +
    + +
    + + +

    Offset 0x0008: CONTROL Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    + +    		 + + + + +
    CONTROL
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088068 + +
    + +
    + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088088 + +
    + +

    + +

    Initial Value = 0x00000001 +

    + +

    This register is defined in HDL source file ctrlport_to_jtag.v.

    + +
    + +
    + +
    +

    JTAG module status and control

    + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31r +

    ready

    +

    +

    Bitq FSM is ready for input (no data transmission in progress).

    + +
    31w +

    reset

    +

    +

    When asserted ('1') a soft-reset for the bitq FSM is triggered, +preventing any transactions to take place.

    +

    Deassert this bit, along with values for prescalar and length +to trigger a new transaction (start strobe).

    + +
    30..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..13 +

    Reserved

    +

    + +
    12..8 +

    length

    +

    +

    (Number of bits - 1) to be transferred

    + +
    7..0 +

    prescalar   (initialvalue=true)

    +

    +

    Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value.

    + +
    + +
    + +
    + + +

    Offset 0x000C: RX_DATA Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    + +    		 + + + + +
    RX_DATA
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x100008806C + +
    + +
    + + + + +
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    + +    		 + + + + + +
    + + +Total Offset =
      0x100008808C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_jtag.v.

    + +
    + +
    + +
    +

    Received data (TDO)

    + +
    + +
    + +
    + +
    + +
    + +

    MB_CPLD_PL_REGMAP

    +
    +

    This register map is available using the PL CPLD SPI interface. +All protocol masters controller by this register map are running with a clock frequency of 50 MHz.

    +

    MB_CPLD_PL_WINDOWS

    +
    +
    +
    + + +

    Offset 0x0000: PL_REGISTERS Window (R|W)

    +

      Target regmap = PL_CPLD_BASE_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + + +
    PL_REGISTERS
      offset=0x0000
      size=0x40 (64 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088000 + +
    + +

    + +

    This window is defined in HDL source file mb_cpld.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x0060: JTAG_DB0 Window (R|W)

    +

      Target regmap = JTAG_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + + +
    JTAG_DB0
      offset=0x0060
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088060 + +
    + +

    + +

    This window is defined in HDL source file mb_cpld.v.

    + +
    + +
    + +
    +

    JTAG Master connected to first daugherboard's CPLD JTAG interface.

    +

    Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.

    + +
    + +
    + +
    + + +

    Offset 0x0080: JTAG_DB1 Window (R|W)

    +

      Target regmap = JTAG_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + + +
    JTAG_DB1
      offset=0x0080
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088080 + +
    + +

    + +

    This window is defined in HDL source file mb_cpld.v.

    + +
    + +
    + +
    +

    JTAG Master connected to second daugherboard's CPLD JTAG interface.

    +

    Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.

    + +
    + +
    + +
    + +
    + +
    + +

    NIXGE_REGMAP

    +
    +
    +

    XGE_MAC_REGS

    +
    +

    nixge (maps to 10g mac if present)

    +
    + + +

    Offset 0x0000: PORT_INFO Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    PORT_INFO
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    COMPAT_NUM

    +

    +

    Constant indicating version for this space. +Not used by the NIXGE driver (12/4/2020)

    + +
    23..18 +

    Reserved

    +

    + +
    17 +

    ACTIVITY

    +

    +

    Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.

    + +
    16 +

    LINK_UP

    +

    +

    Generically means that a connection with a peer has been established. Specific +meaning varies based on the MGT_PROTOCOL.

    + +
    15..8 +

    MGT_PROTOCOL

    +

    +

    Constant indicating what flavor of communication this port is using

    +
      +
    • 0 = NONE
      • +
    • 1 = 1GbE
      • +
    • 2 = 10GbE
      • +
    • 3 = Aurora
      • +
    • 4 = WhiteRabbit
      • +
    • 5 = 100GbE
      • +

    + +
    7..0 +

    PORTNUM

    +

    +

    Constant indicating which port this register is hooked to

    +
      +
    • 0 = QSFP0
      • +
    • 1 = QSFP1
      • +

    + +
    + +
    + +
    + + +

    Offset 0x0004: MAC_CTRL_STATUS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    MAC_CTRL_STATUS
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078004 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Definition of this register depends on Protocol

    +

    10GBE

    +

    READ - Status

    +
      +
    • 0 = status_crc_error
      • +
    • 1 = status_fragment_error
      • +
    • 2 = status_txdfifo_ovflow
      • +
    • 3 = status_txdfifo_udflow
      • +
    • 4 = status_rxdfifo_ovflow
      • +
    • 5 = status_rxdfifo_udflow
      • +
    • 6 = status_pause_frame_rx
      • +
    • 7 = status_local_fault
      • +
    • 8 = status_remote_fault
      • +
    +

    WRITE - Ctl

    +
      +
    • 0 = ctrl_tx_enable
      • +
    +

    100 GBE

    +

    READ - Status

    +
      +
    • 0 = tx_ovfout - Sets if TX overflow reported by CMAC + (Stays set till MAC is reset). This is a fatal error
      • +
    • 1 = tx_unfout - Sets if TX underflow reported by CMAC + (Stays set till MAC is reset). This is a fatal error
      • +
    • 2 = stat_rx_aligned - goes high when CMAC has finished + alignment, and is ready to start reception of traffic.
      • +
    • 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID) + but upstream is trying to hold(TREADY)off we drop a packet. + Upstream circuitry should detect this when traffic is forked + between CHDR and CPU, so this bit will only set if there is a + HW design error.
      • +
    • 4 = auto_config_done - This bit goes high when the auto_config + state machine finishes operation. It is very similiar to + stat_rx_alligned, but waits for extra writes which occur + after allignement to complete.
      • +
    • 24:16 = pause_mask - readable version of pause_mask bellow.
      • +
    +

    WRITE - Ctl

    +
      +
    • 0 = auto_enable - Defaults to ON after reset - Enables a + state machine that performs CMAC register writes to + bring up the MAC without SW intervention.
      • +
    • 24:16 = pause_mask - A second layer of enables(the first being + register in the CMAC) on the pause_request mechanic. Bits + 7:0 of enable pause on PFC7:0. Bit 8 enables global pause + request (not priority controlled). The mask is used for TX + and RX.
      • +
    + +
    + +
    + +
    + + +

    Offset 0x0008: MAC_PHY_STATUS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    MAC_PHY_STATUS
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008008 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018008 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028008 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038008 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048008 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058008 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068008 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078008 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Definition of this register depends on Protocol

    +

    10GBE

    +

    *READ - Status *

    +
      +
    • 0 = core_status 0 - link_up
      • +
    • 1 = core_status 1
      • +
    • 2 = core_status 2
      • +
    • 3 = core_status 3
      • +
    • 4 = core_status 4
      • +
    • 5 = core_status 5
      • +
    • 6 = core_status 6
      • +
    • 7 = core_status 7
      • +
    +

    100 GBE

    +

    READ - Status

    +
      +
    • 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
      • +
    • 1 = usr_rx_reset - RX PLL's have locked
      • +
    + +
    + +
    + +
    + + +

    Offset 0x000C: MAC_LED_CTL Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    MAC_LED_CTL
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000800C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001800C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002800C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003800C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004800C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005800C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006800C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007800C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..2 +

    Reserved

    +

    + +
    1 +

    identify_value

    +

    +

    When identify_enable is set, this value controls the activity LED.

    + +
    0 +

    identify_enable

    +

    +

    When set identify_value is used to control the activity LED. +When clear the activity LED set on any TX or RX traffic to the mgt

    + +
    + +
    + +
    + + +

    Offset 0x0010: ETH_MDIO_BASE Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    ETH_MDIO_BASE
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078010 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    The x4xx family of products does not use MDIO.

    + +
    + +
    + +
    + + +

    Offset 0x0020: AURORA_OVERRUNS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    AURORA_OVERRUNS
      offset=0x0020
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078020 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Only valid if the protocol is Aurora.

    + +
    + +
    + +
    + + +

    Offset 0x0024: AURORA_CHECKSUM_ERRORS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    AURORA_CHECKSUM_ERRORS
      offset=0x0024
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008024 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018024 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028024 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038024 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048024 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058024 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068024 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078024 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Only valid if the protocol is Aurora.

    + +
    + +
    + +
    + + +

    Offset 0x0028: AURORA_BIST_CHECKER_SAMPS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    AURORA_BIST_CHECKER_SAMPS
      offset=0x0028
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008028 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018028 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028028 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038028 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048028 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058028 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068028 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078028 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Only valid if the protocol is Aurora.

    + +
    + +
    + +
    + + +

    Offset 0x002C: AURORA_BIST_CHECKER_ERRORS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + +
    AURORA_BIST_CHECKER_ERRORS
      offset=0x002C
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000802C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001802C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002802C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003802C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004802C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005802C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006802C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007802C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Only valid if the protocol is Aurora.

    + +
    + +
    + +
    + +

    XGE_MAC_WINDOW

    +
    +
    +
    + + +

    Offset 0x1000: XGE_MAC Window (R|W)

    +

      Target regmap = XGE_MAC_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|NIXGE
      0x008000
    + +    		 + + + + + +
    XGE_MAC
      offset=0x1000
      size=0x1000 (4 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200009000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200019000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200029000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200039000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200049000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200059000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200069000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200079000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + +
    + +
    + +

    PL_CPLD_BASE_REGMAP

    + +

    MB_CPLD_LED_REGS

    + Register Map to control QSFP LEDs. +
    + + +

    Offset 0x0020: LED_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|PL_REGISTERS
      0x000000
    + +    		 + + + + +
    LED_REGISTER
      offset=0x0020
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088020 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file pl_cpld_regs.v.

    + +
    + +
    + +Provides to the LEDs of the QSFP ports. + Write access will directly change the LED status. + The LED lights up if the corresponding bit is set. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    15..12 +

    QSFP1_LED_ACTIVE

    +

    Active LEDs of QSFP port 1

    + +
    11..8 +

    QSFP1_LED_LINK

    +

    Link LEDs of QSFP port 1

    + +
    7..4 +

    QSFP0_LED_ACTIVE

    +

    Active LEDs of QSFP port 0

    + +
    3..0 +

    QSFP0_LED_LINK

    +

    Link LEDs of QSFP port 0

    + +
    + +
    + +
    + +

    PL_CMI_REGS

    + Cable present status register. +
    + + +

    Offset 0x0030: CABLE_PRESENT_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|PL_REGISTERS
      0x000000
    + +    		 + + + + +
    CABLE_PRESENT_REG
      offset=0x0030
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088030 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file pl_cpld_regs.v.

    + +
    + +
    + +Information from FPGA about the cable present status. + +
    + + + + + + + + + + + + + + +
    BitsName
    1 +

    IPASS1_CABLE_PRESENT

    +

    Set to 1 if cable present in iPass 1 connector.

    + +
    0 +

    IPASS0_CABLE_PRESENT

    +

    Set to 1 if cable present in iPass 0 connector.

    + +
    + +
    + +
    + +

    PL_CPLD_BASE_REGS

    + Basic registers containing version and capabilities information. +
    + + +

    Offset 0x0000: SIGNATURE_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|PL_REGISTERS
      0x000000
    + +    		 + + + + +
    SIGNATURE_REGISTER
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file pl_cpld_regs.v.

    + +
    + +
    + +Contains the product's signature. + +
    + + + + + + + + + +
    BitsName
    31..0 +

    PRODUCT_SIGNATURE

    +

    Fixed value PL_CPLD_SIGNATURE of CONSTANTS_REGMAP

    + +
    + +
    + +
    + + +

    Offset 0x0004: REVISION_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|PL_REGISTERS
      0x000000
    + +    		 + + + + +
    REVISION_REGISTER
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088004 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file pl_cpld_regs.v.

    + +
    + +
    + +Contains the CPLD revision (see CPLD_REVISION of CONSTANTS_REGMAP) + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    REVISION_YY

    +

    Contains revision year code.

    + +
    23..16 +

    REVISION_MM

    +

    Contains revision month code.

    + +
    15..8 +

    REVISION_DD

    +

    Contains revision day code.

    + +
    7..0 +

    REVISION_HH

    +

    Contains revision hour code.

    + +
    + +
    + +
    + + +

    Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|PL_REGISTERS
      0x000000
    + +    		 + + + + +
    OLDEST_COMPATIBLE_REVISION_REGISTER
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088008 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file pl_cpld_regs.v.

    + +
    + +
    + +This register returns (in YYMMDDHH format) the oldest revision + that is still compatible with this one. Compatible means that + registers or register bits may have been added, but not + modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP). + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    OLD_REVISION_YY

    +

    Contains revision year code.

    + +
    23..16 +

    OLD_REVISION_MM

    +

    Contains revision month code.

    + +
    15..8 +

    OLD_REVISION_DD

    +

    Contains revision day code.

    + +
    7..0 +

    OLD_REVISION_HH

    +

    Contains revision hour code.

    + +
    + +
    + +
    + + +

    Offset 0x000C: SCRATCH_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|PL_REGISTERS
      0x000000
    + +    		 + + + + +
    SCRATCH_REGISTER
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x100008800C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file pl_cpld_regs.v.

    + +
    + +
    + +Read/write register for general software use. + +
    + +
    + +
    + + +

    Offset 0x0010: GIT_HASH_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + + +
    MB_CPLD_PL_REGMAP|PL_REGISTERS
      0x000000
    + +    		 + + + + +
    GIT_HASH_REGISTER
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088010 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file pl_cpld_regs.v.

    + +
    + +
    + +Git hash of commit used to build this image.
    + Value equals 0xDEADBEEF if the git hash was not used during synthesis. + +
    + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    GIT_CLEAN

    +

    0x0 in case the git status was clean
    + 0xF in case there were uncommitted changes

    + +
    27..0 +

    GIT_HASH

    +

    7 hex digit hash code of the commit

    + +
    + +
    + +
    + +
    + +
    + +

    PL_CPLD_REGMAP

    + This register map is available from the PS via AXI and MPM endpoint. + Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation. +

    PL_CPLD_WINDOWS

    + +
    + + +

    Offset 0x0000: BASE Window (R|W)

    +

      Target regmap = CPLD_INTERFACE_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + + +
    BASE
      offset=0x0000
      size=0x40 (64 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000080000 + +
    + +

    + +

    This window is defined in HDL source file cpld_interface.v.

    + +
    + +
    + + + +
    + +
    + +
    + + +

    Offset 0x8000: MB_CPLD Window (R|W)

    +

      Target regmap = MB_CPLD_PL_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + + +
    MB_CPLD
      offset=0x8000
      size=0x8000 (32 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088000 + +
    + +

    + +

    This window is defined in HDL source file cpld_interface.v.

    + +
    + +
    + +All registers of the MB CPLD (PL part). + +
    + +
    + +
    + + +

    Offset 0x10000: DB0_CPLD Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + + +
    DB0_CPLD
      offset=0x10000
      size=0x8000 (32 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000090000 + +
    + +

    + +

    This window is defined in HDL source file cpld_interface.v.

    + +
    + +
    + +All registers of the first DB CPLD. Register map will be added later on. + +
    + +
    + +
    + + +

    Offset 0x18000: DB1_CPLD Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + + +
    DB1_CPLD
      offset=0x18000
      size=0x8000 (32 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000098000 + +
    + +

    + +

    This window is defined in HDL source file cpld_interface.v.

    + +
    + +
    + +All registers of the second DB CPLD. Register map will be added later on. + +
    + +
    + +
    + +
    + +
    + +

    PL_DMA_MASTER_REGMAP

    + This is a regmap to document the different ports that have access to the PS system memory. + Each port may have different restrictions on system memory. See the corresponding window + for details +

    HPC0_DMA

    + +
    + + +

    Offset 0x0000: AXI_HPC0_WINDOW Window (R|W)

    +

      Target port = X410_FPGA|ARM_S_AXI_HPC0

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    AXI_HPC0_WINDOW
      offset=0x0000
      size=0x10000000000 (1024 Gbytes)
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +The HPC0 port of the PS is used for general purpose cache-coherent accesses + to the PS system memory. Different applications may use it for different + purposes. Its access is configured as follows:
    + + + + + + +
    Offset Size Description
    0x0008000000000x000800000000DDR_HIGH
    0x00000000 0x80000000 DDR_LOW
    0xFF000000 0x01000000 LPS_OCM
    0xC0000000 0x20000000 QSPI
    + +
    + +
    + +
    + +

    HPC1_DMA

    + +
    + + +

    Offset 0x0000: AXI_HPC1_WINDOW Window (R|W)

    +

      Target port = X410_FPGA|ARM_S_AXI_HPC1

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    AXI_HPC1_WINDOW
      offset=0x0000
      size=0x1000000000 (64 Gbytes)
    + +

    + +

    This window is defined in HDL source file common_regs.v.

    + +
    + +
    + +The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave + interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx. + Its access is configured as follows:
    + + + + + +
    Offset Size Description
    0x0008000000000x000800000000DDR_HIGH
    0x00000000 0x80000000 DDR_LOW
    0xC0000000 0x20000000 QSPI
    + +
    + +
    + +
    + +
    + +
    + +

    PS_CPLD_BASE_REGMAP

    + +

    DIO_REGS

    + Registers to control the GPIO buffer direction on the DIO board connected to the FPGA. + Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. + Set the direction in the FPGA's DIO register appropriately. +
    + + +

    Offset 0x0030: DIO_DIRECTION_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    DIO_DIRECTION_REGISTER
      offset=0x0030
    + +    		 + + + + + +
    + + +Total Offset =
      0x000030 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Set the direction of FPGA buffer connected to DIO ports on the DIO board.
    + Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA. + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    Reserved

    +

    + +
    27..16 +

    DIO_DIRECTION_B   (initialvalue=0)

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11..0 +

    DIO_DIRECTION_A   (initialvalue=0)

    +

    + +
    + +
    + +
    + +

    PS_CMI_REGS

    + Cable present status register. +
    + + +

    Offset 0x0034: SERIAL_NUM_LOW_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    SERIAL_NUM_LOW_REG
      offset=0x0034
    + +    		 + + + + + +
    + + +Total Offset =
      0x000034 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Least significant bytes of 5 byte serial number. + +
    + +
    + +
    + + +

    Offset 0x0038: SERIAL_NUM_HIGH_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    SERIAL_NUM_HIGH_REG
      offset=0x0038
    + +    		 + + + + + +
    + + +Total Offset =
      0x000038 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Most significant byte of 5 byte serial number. + +
    + +
    + +
    + + +

    Offset 0x003C: CMI_CONTROL_STATUS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    CMI_CONTROL_STATUS
      offset=0x003C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00003C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Control CMI communication and delivers information on the CMI link status. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31r +

    OTHER_SIDE_DETECTED

    +

    1 if an upstream CMI device has been detected.

    + +
    30..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    CMI_READY

    +

    Set if the device is ready to establish a PCI-Express link (affects CMI_CLP_READY bit).

    + +
    + +
    + +
    + +

    PS_CONTROL_REGS

    + Register Map to control MB CPLD functions. +
    + + +

    Offset 0x0020: PL_DB_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    PL_DB_REGISTER
      offset=0x0020
    + +    		 + + + + + +
    + + +Total Offset =
      0x000020 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Register to control the PL part DB SPI connection and reset generation. + The DB connection is clocked with PLL reference clock. Ensure this clock is stable + and enabled before starting any SPI request. + The PLL reference clock can be disabled if both DB connections are disabled or inactive. + To enable the DB connection, enable clock with one write access and release + reset with the next write access. + To disable the DB connection, assert reset with one write access and + disable clocks with the next write access. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..22 +

    Reserved

    +

    + +
    21w +

    ASSERT_RESET_DB1

    +

    Writing with this flag set asserts reset for DB 1 (overrides RELEASE_RESET_DB1)

    + +
    20w +

    ASSERT_RESET_DB0

    +

    Writing with this flag set asserts reset for DB 0 (overrides RELEASE_RESET_DB0)

    + +
    19..18 +

    Reserved

    +

    + +
    17w +

    RELEASE_RESET_DB1

    +

    Writing with this flag set releases DB 1 reset. (may be overwritten by ASSERT_RESET_DB1)

    + +
    16w +

    RELEASE_RESET_DB0

    +

    Writing with this flag set releases DB 0 reset. (may be overwritten by ASSERT_RESET_DB0)

    + +
    15 +

    Reserved

    +

    + +
    14w +

    DISABLE_PLL_REF_CLOCK

    +

    Writing with this flag set disables the PLL reference clock (overrides ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock.

    + +
    13w +

    DISABLE_CLOCK_DB1

    +

    Writing with this flag set disables DB 1 clock forwarding (overrides ENABLE_CLOCK_DB1)

    + +
    12w +

    DISABLE_CLOCK_DB0

    +

    Writing with this flag set disables DB 0 clock forwarding (overrides ENABLE_CLOCK_DB0)

    + +
    11 +

    Reserved

    +

    + +
    10w +

    ENABLE_PLL_REF_CLOCK

    +

    Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by DISABLE_PLL_REF_CLOCK)

    + +
    9w +

    ENABLE_CLOCK_DB1

    +

    Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB1)

    + +
    8w +

    ENABLE_CLOCK_DB0

    +

    Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by DISABLE_CLOCK_DB0)

    + +
    7..6 +

    Reserved

    +

    + +
    5r +

    DB1_RESET_ASSERTED

    +

    Indicates that reset is asserted for DB 1.

    + +
    4r +

    DB0_RESET_ASSERTED

    +

    Indicates that reset is asserted for DB 0.

    + +
    3 +

    Reserved

    +

    + +
    2r +

    PLL_REF_CLOCK_ENABLED

    +

    Indicates if the PLL reference clock for the PL interface is enabled.

    + +
    1r +

    DB1_CLOCK_ENABLED

    +

    Indicates if a clock is forwarded to DB 1.

    + +
    0r +

    DB0_CLOCK_ENABLED

    +

    Indicates if a clock is forwarded to DB 0.

    + +
    + +
    + +
    + +

    PS_CPLD_BASE_REGS

    + Basic registers containing version and capabilites information. +
    + + +

    Offset 0x0000: SIGNATURE_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    SIGNATURE_REGISTER
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x000000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Contains the product's signature. + +
    + + + + + + + + + +
    BitsName
    31..0 +

    PRODUCT_SIGNATURE

    +

    Fixed value PS_CPLD_SIGNATURE of CONSTANTS_REGMAP

    + +
    + +
    + +
    + + +

    Offset 0x0004: REVISION_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    REVISION_REGISTER
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x000004 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Contains the CPLD revision (see CPLD_REVISION of CONSTANTS_REGMAP). + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    REVISION_YY

    +

    Contains revision year code.

    + +
    23..16 +

    REVISION_MM

    +

    Contains revision month code.

    + +
    15..8 +

    REVISION_DD

    +

    Contains revision day code.

    + +
    7..0 +

    REVISION_HH

    +

    Contains revision hour code.

    + +
    + +
    + +
    + + +

    Offset 0x0008: OLDEST_COMPATIBLE_REVISION_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    OLDEST_COMPATIBLE_REVISION_REGISTER
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x000008 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +This register returns (in YYMMDDHH format) the oldest revision + that is still compatible with this one. Compatible means that + registers or register bits may have been added, but not + modified or deleted (see OLDEST_CPLD_REVISION of CONSTANTS_REGMAP). + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    OLD_REVISION_YY

    +

    Contains revision year code.

    + +
    23..16 +

    OLD_REVISION_MM

    +

    Contains revision month code.

    + +
    15..8 +

    OLD_REVISION_DD

    +

    Contains revision day code.

    + +
    7..0 +

    OLD_REVISION_HH

    +

    Contains revision hour code.

    + +
    + +
    + +
    + + +

    Offset 0x000C: SCRATCH_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    SCRATCH_REGISTER
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00000C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Read/write register for general software use. + +
    + +
    + +
    + + +

    Offset 0x0010: GIT_HASH_REGISTER Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|PS_REGISTERS
      0x000000
    + +    		 + + + + +
    GIT_HASH_REGISTER
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x000010 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_cpld_regs.v.

    + +
    + +
    + +Git hash of commit used to build this image.
    + Value equals 0xDEADBEEF if the git hash was not used during synthesis. + +
    + + + + + + + + + + + + + + +
    BitsName
    31..28 +

    GIT_CLEAN

    +

    0x0 in case the git status was clean
    + 0xF in case there were uncommitted changes

    + +
    27..0 +

    GIT_HASH

    +

    7 hex digit hash code of the commit

    + +
    + +
    + +
    + +
    + +
    + +

    PS_POWER_REGMAP

    + +

    PS_POWER_REGS

    + Registers to control power supplies on the motherboard. +
    + + +

    Offset 0x0000: IPASS_POWER_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|POWER_REGISTERS
      0x000060
    + +    		 + + + + +
    IPASS_POWER_REG
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x000060 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_power_regs.v.

    + +
    + +
    + +Controls the power supplies for the iPass connectors. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31r +

    IPASS_POWER_FAULT1

    +

    Asserted signal indicates a power fault in power switch for iPass + connector 1. Sticky bit. Asserted on occurrence. Reset using + IPASS_CLEAR_POWER_FAULT1.

    + +
    31w +

    IPASS_CLEAR_POWER_FAULT1

    +

    Clear IPASS_POWER_FAULT1.

    + +
    30r +

    IPASS_POWER_FAULT0

    +

    Asserted signal indicates a power fault in power switch for iPass + connector 0. Sticky bit. Asserted on occurrence. Reset using + IPASS_CLEAR_POWER_FAULT0.

    + +
    30w +

    IPASS_CLEAR_POWER_FAULT0

    +

    Clear IPASS_POWER_FAULT0.

    + +
    29..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    IPASS_DISABLE_POWER_BIT

    +

    Set to 1 to disable power for both iPass connectors.

    + +
    + +
    + +
    + + +

    Offset 0x0004: OSC_POWER_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|POWER_REGISTERS
      0x000060
    + +    		 + + + + +
    OSC_POWER_REG
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x000064 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ps_power_regs.v.

    + +
    + +
    + +Controls the power supplies for the oscillators. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..2 +

    Reserved

    +

    + +
    1 +

    OSC_122_88

    +

    Enables 5V power switch for the 122.88 MHz oscillator.

    + +
    0 +

    OSC_100

    +

    Enables 5V power switch for the 100 MHz oscillator.

    + +
    + +
    + +
    + +
    + +
    + +

    QSFP_REGMAP

    +
    +
    +

    QSFP_WINDOWS

    +
    +

    Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations

    +
      +
    • 1X10GB Ethernet - Using OpenCore XGE MAC
      • +
    • 1x100GB Ethernet - Using Xilinx CMAC
      • +
    • (future possible) - Xilinx Aurora (various rates and lane widths)
      • +
    • (future possible) - 4X10GB Ethernet
      • +
    +
    + + +

    Offset 0x0000: ETH_DMA Window (R|W)

    +

      Target regmap = DMA_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + + +
    ETH_DMA
      offset=0x0000
      size=0x4000 (16 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200000000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200010000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200020000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200030000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200040000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200050000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200060000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200070000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x8000: NIXGE Window (R|W)

    +

      Target regmap = NIXGE_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + + +
    NIXGE
      offset=0x8000
      size=0x2000 (8 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200008000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200018000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200028000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200038000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200048000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200058000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200068000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1200078000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0xA000: UIO Window (R|W)

    +

      Target regmap = UIO_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + + +
    UIO
      offset=0xA000
      size=0x2000 (8 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0xC000: CMAC Window (R|W)

    +

      Target regmap = CMAC_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + + +
    CMAC
      offset=0xC000
      size=0x2000 (8 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000C000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001C000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002C000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003C000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004C000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005C000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006C000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007C000 + +
    + +

    + +

    This window is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + +
    + +
    + +

    RADIO_CTRLPORT_REGMAP

    + +

    RADIO_CTRLPORT_WINDOWS

    + Each radio's CtrlPort peripheral interface is divided into the + following memory spaces. Note that the CtrlPort peripheral interface + starts at offset 0x80000 in the RFNoC Radio block's register space. + The following diagram displays the distribution of the CtrlPort + interface to the different modules it interacts with. + + + +

    Offset 0x0000: DB_WINDOW Window (R|W)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    DB_WINDOW
      offset=0x0000
      size=0x8000 (32 Kbytes)
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Daughterboard GPIO interface. Register access within this space + is directed to the associated daughterboard CPLD. + +
    + +
    + +
    + + +

    Offset 0x8000: RFDC_TIMING_WINDOW Window (R|W)

    +

      Target regmap = RFDC_TIMING_REGMAP

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    RFDC_TIMING_WINDOW
      offset=0x8000
      size=0x4000 (16 Kbytes)
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +RFDC timing control interface. + +
    + +
    + +
    + + +

    Offset 0xC000: DIO_WINDOW Window (R|W)

    +

      Target regmap = RADIO_DIO_REGMAP

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    DIO_WINDOW
      offset=0xC000
      size=0x4000 (16 Kbytes)
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +DIO control interface. Interacts with the DIO source selection + block, ATR-based DIO control and the DIO digital interface + +
    + +
    + +
    + + + +
    + +

    RADIO_DIO_REGMAP

    + This map contains register windows for controlling the different sources + that drive the state of DIO lines. +

    DIO_SOURCES

    + +
    + + +

    Offset 0x0000: RADIO_GPIO_ATR_REGS Window (R|W)

    +

      Target regmap = GPIO_ATR_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + + +
    RADIO_GPIO_ATR_REGS
      offset=0x0000
      size=0x1000 (4 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x00C000 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Contains controls for DIO behavior based on the ATR state of the accessed radio + +
    + +
    + +
    + + +

    Offset 0x1000: DIO_SOURCE_CONTROL Window (R|W)

    +

      Target regmap = DIO_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + + +
    DIO_SOURCE_CONTROL
      offset=0x1000
      size=0x1000 (4 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x00D000 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Window to access the DIO register map through the control port from the radio blocks. + +
    + +
    + +
    + + +

    Offset 0x2000: DIGITAL_IFC_REGS Window (R|W)

    +

      Target regmap = DIG_IFC_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|DIO_WINDOW
      0x00C000
    + +    		 + + + + + +
    DIGITAL_IFC_REGS
      offset=0x2000
      size=0x1000 (4 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x00E000 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Register space reserved for configuring a digital interface over the GPIO lines. + Currently, SPI is the only supported protocol. + +
    + +
    + +
    + +
    + +
    + +

    RECONFIG_REGMAP

    + +

    RECONFIG_REGS

    + These registers are used to upload and verify a new primary image to the + Max 10 FPGA on-chip flash when configured to support dual configuration + images. The steps below outline the process of verifying/preparing the + new image to be written, erasing the current image, writing the new + image, and verifying the new image was successfully written. +

    Prepare the data... +

    1. The Max 10 FPGA build should generate a *cfm0_auto.rpd + file The *.rpd file is a "raw programming + data" file holding all data related to the + configuration image (CFM0). There are two + important items to note regarding the addresses. + First the *rpd data uses byte addresses. + Second, the start/end addresses defined by + FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses

      2. +

    2. As a sanity check, verify the size of the raw + programming data for CFM0 correspond to the address + range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by + reading the values from FLASH_CFM0_START_ADDR_REG and + FLASH_CFM0_END_ADDR, subtract both values, add one and + multiply by four. +

      3. +

    3. Having passed the sanity check the *.rpd data must + now be manipulated into the form required by Altera's + on-chip flash IP. Two operations must be performed. + First the data must be converted from bytes to 32-bit + words. Second the bit order must be reversed. This is + illustrated in in the following table which shows byte + address and data from the *.rpd file compared to the + word address and data to be written to the on-chip + flash. + + + + + + + + + + +
      .Map Addr.Map DataFlash AddrFlash Data
      0x2B8000x010xAC000x8040C020
      0x2B8010x02
      0x2B8020x03
      0x2B8030x04
      0x2B8040x050xAC010xA060E010
      0x2B8050x06
      0x2B8060x07
      0x2B8070x08
      +

      4. +

    4. The resulting set of flash address data pairs should + be used when writing FLASH_ADDR_REG and + FLASH_WRITE_DATA_REG to update the CFM0 image. + However, prior to writing the new image the old image + must be erased. +

      5. +
    +

    +

    Erase the current primary flash image... +

    1. Read FLASH_STATUS_REG and verify no error bits are + asserted and that all read, write, and erase operations + are idle.

      2. +

    2. Disable write protection of the flash by strobing the + FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG. +

      3. +

    3. Verify write protection is disabled and no errors are + present by reading FLASH_STATUS_REG.

      4. +

    4. Initiate the erase operation by setting + FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of + FLASH_CONTROL_REG.

      5. +

    5. Poll the FLASH_ERASE_IDLE bit of + FLASH_STATUS_REG until it de-asserts indicating the + erase operation is complete, then verify the operation + was successful by checking that the FLASH_ERASE_ERR + bit is de-asserted. Erase operations are expected to + take a maximum of 350 msec. Upon completion of the erase + operation write protection will remain disabled. +

      6. +

    6. Erase additional sectors as required (see + FLASH_ERASE_SECTOR for details) by restarting with first + step.

      7. +
    +

    +

    Write the new primary flash image... +

    1. Read FLASH_STATUS_REG and verify no error bits are + asserted, all read, write, and erase operations are + idle, and write protection is disabled.
      2. +

    2. Set the target address for the write to the Max 10 + on-chip flash by writing value from + FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

      3. +

    3. Set the data to be written to this address by writing + the new 32-bit word of the new image to + FLASH_WRITE_DATA_REG.

      4. +

    4. Initiate the write by strobing FLASH_WRITE_STB of + FLASH_CONTROL_REG.

      5. +

    5. Poll the FLASH_WRITE_IDLE bit of + FLASH_STATUS_REG until it de-asserts indicating the + write operation is complete, then verify the operation + was successful by checking that the FLASH_WRITE_ERR + bit is de-asserted. Write operations are expected to + take a maximum of 550 usec.

      6. +

    6. Upon completion of the write operation return to step + 2, incrementing the target address by one, and writing + the next 32-bit word to Max10FlashWriteDatReg. If this + was the last write, indicated by writing to + FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step + to enable write protection.

      7. +

    7. After writing the new image enable write protection + by strobing the FLASH_ENABLE_WP_STB bit of + FLASH_CONTROL_REG.

      8. +
    +

    +

    Verify the new primary flash image... +

    1. Read FLASH_STATUS_REG and verify no error bits are + asserted and that all read, write, and erase operations + are idle.

      2. +

    2. Set the target address for the read in the Max 10 + on-chip flash by writing value from + FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.

      3. +

    3. Initiate the read by strobing FLASH_READ_STB of + FLASH_CONTROL_REG.

      4. +

    4. Poll the FLASH_READ_IDLE bit of + FLASH_STATUS_REG until it de-asserts indicating the + read operation is complete, then verify the operation + was successful by checking that the FLASH_READ_ERR + bit is de-asserted. There is no guidance on exactly how + long reads take to complete, but they are expected to be + fairly quick. A very conservative timeout on this + polling would be similar to that used for write + operations.

      5. +

    5. Upon completion of the read operation the resulting + data returned by the on-chip flash will be available in + Max10FlashReadDatReg. Read this register, compare to + expected value previously written, and ensure they + match.

      6. +

    6. Return to step 2, incrementing the target + address by one. If this was the last read verification + is complete and no further action is required.

      7. +
    +

    +

    After the flash has been erased, programmed, and verified, a power + cycle is required for the new image to become active. +

    +
    + + +

    FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration

    +These values are the start and end address of the CFM image flash + sector from Intel's On-Chip Flash IP Generator. + Be aware that three different values exist per each of the two + supported MAX10 variants: 10M04 and 10M08 + Note that the values given in the IP generator are byte based where + the values of this enum are U32 based (divided by 4). + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    40960x01000 +

    FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04

    + +
    81920x02000 +

    FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08

    + +
    399360x09C00 +

    FLASH_PRIMARY_IMAGE_START_ADDR_10M04

    + +
    440320x0AC00 +

    FLASH_PRIMARY_IMAGE_START_ADDR_10M08

    + +
    757750x127FF +

    FLASH_PRIMARY_IMAGE_END_ADDR_10M04

    + +
    798710x137FF +

    FLASH_PRIMARY_IMAGE_END_ADDR_10M08

    + +
    + +

    + This enumerated type is defined in HDL source file reconfig_engine.v. +

    + +
    + +
    + + +

    Offset 0x0000: FLASH_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|RECONFIG
      0x000040
    + +    		 + + + + +
    FLASH_STATUS_REG
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x000040 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..17 +

    Reserved

    +

    + +
    16 +

    FLASH_MEM_INIT_ENABLED

    +

    This bit is asserted when the flash can hold an image with memory + initialization.

    + +
    15..14 +

    Reserved

    +

    + +
    13 +

    FLASH_WRITE_ERR

    +

    This bit is asserted when write operation fails. Clear this error + by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In + the event of a write error... +

  • the primary configuration image may be corrupted, and + power cycling the board may result unknown behavior.
    • +
  • write protection of the flash will automatically be + re-enabled.
    • +
  • attempts to disable write protection will be ignored.
    • +
  • attempts to read/write/erase the flash will be ignored.

    • + +
    12 +

    FLASH_WRITE_IDLE

    +

    This bit is de-asserted when a write operation is in progress. Poll + this bit after strobing the FLASH_WRITE_STB bit of + FLASH_CONTROL_REG to determine when the write operation has + completed, then check the FLASH_WRITE_ERR bit to verify the + operation was successful.

    + +
    11..10 +

    Reserved

    +

    + +
    9 +

    FLASH_ERASE_ERR

    +

    This bit is asserted when an erase operation fails. Clear this + error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In + the event of an erase error... +

  • the primary configuration image may be corrupted, and + power cycling the board may result in unknown behavior.
    • +
  • write protection of the flash will automatically be + re-enabled.
    • +
  • attempts to disable write protection will be ignored.
    • +
  • attempts to read/write/erase the flash will be ignored.

    • + +
    8 +

    FLASH_ERASE_IDLE

    +

    This bit is de-asserted when an erase operation is in progress. Poll + this bit after strobing the FLASH_ERASE_STB bit of + FLASH_CONTROL_REG to determine when the erase operation has + completed, then check the FLASH_ERASE_ERR bit to verify the + operation was successful.

    + +
    7..6 +

    Reserved

    +

    + +
    5 +

    FLASH_READ_ERR

    +

    This bit is asserted when a read operation fails. Clear this error + by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the + event of a read error... +

  • the data in FLASH_READ_DATA_REG is invalid.
    • +
  • attempts to disable write protection will be ignored.
    • +
  • attempts to read/write/erase the flash will be ignored.

    • + +
    4 +

    FLASH_READ_IDLE

    +

    This bit is de-asserted when a read operation is in progress. Poll + this bit after strobing the FLASH_READ_STB bit of + FLASH_CONTROL_REG to determine when the read operation has + completed, then check the FLASH_READ_ERR bit to verify the + operation was successful.

    + +
    3..1 +

    Reserved

    +

    + +
    0 +

    FLASH_WP_ENABLED

    +

    This bit is asserted when the flash is write protected and + de-asserted when write protection is disabled. +

  • Write protection must be enabled prior to performing read + operations.
    • +
  • Write protection must be disabled prior to performing write and + erase operations.

    • + +
    + +
    + +
    + + +

    Offset 0x0004: FLASH_CONTROL_REG Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|RECONFIG
      0x000040
    + +    		 + + + + +
    FLASH_CONTROL_REG
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x000044 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..11 +

    Reserved

    +

    + +
    10w +

    CLEAR_FLASH_ERASE_ERROR_STB   (Strobe)

    +

    Strobe this bit to clear an erase error.

    + +
    9w +

    CLEAR_FLASH_WRITE_ERROR_STB   (Strobe)

    +

    Strobe this bit to clear a write error.

    + +
    8w +

    CLEAR_FLASH_READ_ERROR_STB   (Strobe)

    +

    Strobe this bit to clear a read error.

    + +
    7..5w +

    FLASH_ERASE_SECTOR   (Strobe)

    +

    Defines the sector to be erased. Has to be set latest with the + write access which starts the erase operation by strobing + FLASH_ERASE_STB.
    + With 10M04 variants, if the flash is configured to support memory + initialization (see FLASH_MEM_INIT_ENABLED flag) the sectors 2 + to 4 have to be erased. If the flag is not asserted only sector 4 + has to be erased. + With 10M08 variants, the sectors to be erased are 3 to 5 when + using memory initialization or only sector 5 otherwise.

    + +
    4w +

    FLASH_ERASE_STB   (Strobe)

    +

    Strobe this bit to erase the primary Max10 configuration image + (CFM0). +

  • Prior to strobing this bit verify no other write or erase + operations are in progress, write protection is disabled, and no + error bits are asserted by reading FLASH_STATUS_REG.
    • +
  • Attempts to erase the primary image while other write or erase + operations are in progress will be ignored. +
  • Attempts to erase the primary image when write protection is + enabled will be ignored.
    • +
  • Strobing this bit and FLASH_WRITE_STB simultaneously will + result both the erase and the write operation being ignored, both + corresponding error bits being set, and write protection being + re-enabled.
    • +
  • After strobing this bit poll the FLASH_ERASE_IDLE and + FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when + the erase operation is complete and if it was successful.

    • + +
    3w +

    FLASH_WRITE_STB   (Strobe)

    +

    Strobe this bit to write the data contained in + FLASH_WRITE_DATA_REG to the flash address identified in + FLASH_ADDR_REG. +

  • The flash must be erased before writing new data.
    • +
  • Prior to strobing this bit verify write protection is + disabled, no other write or erase operations are in progress, and + no error bits are asserted by reading FLASH_STATUS_REG.
    • +
  • Attempts to write data while other write or erase operations + are in progress will be ignored.
    • +
  • Attempts to write data with write protection enabled will be + ignored.
    • +
  • Strobing this bit and FLASH_ERASE_STB simultaneously will + result in both the write and erase operation being ignored, + both corresponding error bits being set, and write protection + being re-enabled.
    • +
  • After strobing this bit poll theMax10FlashWriteIdle and + FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when + the write operation is complete and if it was successful.

    • + +
    2w +

    FLASH_READ_STB   (Strobe)

    +

    Strobe this bit to read data from the flash address identified in + FLASH_ADDR_REG. +

  • Prior to strobing this bit verify no read, write, or erase + operations are in progress, no error bits are asserted, and + write protection is enabled by reading FLASH_STATUS_REG.
    • +
  • Attempts to read data while other operations are in progress + or while write protection is disabled will be ignored.
    • +
  • After strobing this bit poll the FLASH_READ_IDLE and + FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when + the read operation is complete and if it was successful.
    • +
  • Upon successful completion the data read from flash will be + available in FLASH_READ_DATA_REG.

    • + +
    1w +

    FLASH_DISABLE_WP_STB   (Strobe)

    +

    Strobe this bit to disable write protection to the section of the + Max 10 on-chip flash storing the primary configuration image + (CFM0). +

  • Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to + determine the current state of write protection.
    • +
  • Prior to strobing this bit verify no read operations are in + progress and no error bits are asserted by reading + FLASH_STATUS_REG.
    • +
  • Attempts to disable write protection while a read is in + progress will be ignored.
    • +
  • Attempts to disable write protection will be ignored if + this bit is strobed simultaneously with either FLASH_READ_STB + or FLASH_ENABLE_WP_STB.
    • +
  • Write protection must be disabled prior to performing erase or + write operations.
    • +
  • Upon completion of erase/write operations write protection + will remain disabled. When not actively erasing or writing a new + image write protection should be enabled to avoid data + corruption.

    • + +
    0w +

    FLASH_ENABLE_WP_STB   (Strobe)

    +

    Strobe this bit to enable write protection to the section of the + Max 10 on-chip flash storing the primary configuration image + (CFM0). +

  • Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to + determine the current state of write protection.
    • +
  • Prior to strobing this bit verify no write or erase operations + are in progress and no error bits are asserted by reading + FLASH_STATUS_REG.
    • +
  • Attempts to enable write protection while erase or write + operations are in progress will be ignored.
    • +
  • Write protection must be enabled prior to performing + read operations.
    • +
  • Write protection should be enabled after completing + write or erase operations to prevent data corruption.

    • + +
    + +
    + +
    + + +

    Offset 0x0008: FLASH_ADDR_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|RECONFIG
      0x000040
    + +    		 + + + + +
    FLASH_ADDR_REG
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x000048 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..17 +

    Reserved

    +

    + +
    16..0 +

    FLASH_ADDR

    +

    This field holds the target address for the next read or + write operation. Set this field prior to strobing the + FLASH_WRITE_STB and FLASH_READ_STB bits of + FLASH_CONTROL_REG. Valid addresses are defined by the + FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration.

    + +
    + +
    + +
    + + +

    Offset 0x000C: FLASH_WRITE_DATA_REG Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|RECONFIG
      0x000040
    + +    		 + + + + +
    FLASH_WRITE_DATA_REG
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00004C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0w +

    FLASH_WRITE_DATA

    +

    Data in this register will be written to the flash at the address + identified in FLASH_ADDR_REG when a successful write operation + is executed.

    + +
    + +
    + +
    + + +

    Offset 0x0010: FLASH_READ_DATA_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|RECONFIG
      0x000040
    + +    		 + + + + +
    FLASH_READ_DATA_REG
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x000050 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0 +

    FLASH_READ_DATA

    +

    This register contains data read from the flash address identified + in FLASH_ADDR_REG after a successful read operation is executed.

    + +
    + +
    + +
    + + +

    Offset 0x0014: FLASH_CFM0_START_ADDR_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|RECONFIG
      0x000040
    + +    		 + + + + +
    FLASH_CFM0_START_ADDR_REG
      offset=0x0014
    + +    		 + + + + + +
    + + +Total Offset =
      0x000054 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0 +

    FLASH_CFM0_START_ADDR

    +

    Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

    + +
    + +
    + +
    + + +

    Offset 0x0018: FLASH_CFM0_END_ADDR_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_SPI1_CS3
    + +    		 + + + + +
    MB_CPLD_PS_REGMAP|RECONFIG
      0x000040
    + +    		 + + + + +
    FLASH_CFM0_END_ADDR_REG
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x000058 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file reconfig_engine.v.

    + +
    + +
    + + + +
    + + + + + + + + + +
    BitsName
    31..0 +

    FLASH_CFM0_END_ADDR

    +

    Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM).

    + +
    + +
    + +
    + +
    + +
    + +

    RFDC_REGS_REGMAP

    + +

    RFDC_REGS

    + These are the registers located within the RFDC block design + that provide control and status support for the RF chain. +
    + + +

    FABRIC_DSP_BW_ENUM Enumeration

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x000 +

    FABRIC_DSP_BW_NONE

    + +
    1000x064 +

    FABRIC_DSP_BW_100M

    + +
    2000x0C8 +

    FABRIC_DSP_BW_200M

    + +
    4000x190 +

    FABRIC_DSP_BW_400M

    + +
    10000x3E8 +

    FABRIC_DSP_BW_FULL

    + +
    + +

    + This enumerated type is defined in HDL source file common_regs.v. +

    + +
    + +
    + + +

    Offset 0x0000: MMCM Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + + +
    MMCM
      offset=0x0000
      size=0x10000 (64 Kbytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000140000 + +
    + +

    + +

    This window is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +Register space for controlling the data clock MMCM instance + within the RFDC block design. + Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the + regiter space description in chapter 2. + (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf) + +
    + +
    + +
    + + +

    Offset 0x10000: INVERT_DB0_IQ_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    INVERT_DB0_IQ_REG
      offset=0x10000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000150000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +Control register for inverting I/Q data. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11 +

    INVERT_DB0_DAC3_IQ

    +

    + +
    10 +

    INVERT_DB0_DAC2_IQ

    +

    + +
    9 +

    INVERT_DB0_DAC1_IQ

    +

    + +
    8 +

    INVERT_DB0_DAC0_IQ

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    INVERT_DB0_ADC3_IQ

    +

    + +
    2 +

    INVERT_DB0_ADC2_IQ

    +

    + +
    1 +

    INVERT_DB0_ADC1_IQ

    +

    + +
    0 +

    INVERT_DB0_ADC0_IQ

    +

    + +
    + +
    + +
    + + +

    Offset 0x10800: INVERT_DB1_IQ_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    INVERT_DB1_IQ_REG
      offset=0x10800
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000150800 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +Control register for inverting I/Q data. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11 +

    INVERT_DB1_DAC3_IQ

    +

    + +
    10 +

    INVERT_DB1_DAC2_IQ

    +

    + +
    9 +

    INVERT_DB1_DAC1_IQ

    +

    + +
    8 +

    INVERT_DB1_DAC0_IQ

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    INVERT_DB1_ADC3_IQ

    +

    + +
    2 +

    INVERT_DB1_ADC2_IQ

    +

    + +
    1 +

    INVERT_DB1_ADC1_IQ

    +

    + +
    0 +

    INVERT_DB1_ADC0_IQ

    +

    + +
    + +
    + +
    + + +

    Offset 0x11000: MMCM_RESET_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    MMCM_RESET_REG
      offset=0x11000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000151000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +Control register for resetting the data clock MMCM. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    RESET_MMCM

    +

    Write a '1' to this bit to reset the MMCM. Then write a + '0' to place the MMCM out of reset.

    + +
    + +
    + +
    + + +

    Offset 0x12000: RF_RESET_CONTROL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RF_RESET_CONTROL_REG
      offset=0x12000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000152000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.
    +It uses RegType RF_RESET_CONTROL_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +Control register for the RF reset controller. + Verify the FSM ID before polling starting any reset sequence. + To use the SW reset triggers: Wait until DB*_DONE is de-asserted. + Assert either the *_RESET or *_ENABLE bitfields. + Wait until DB*_DONE is asserted to release the trigger. + The DB*_DONE signal should then de-assert.
    + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..10 +

    Reserved

    +

    + +
    9 +

    DAC_ENABLE

    +

    Write a '1' to this bit to trigger the enable sequence for + the daughterboard 0 DAC chain. Write a '0' once + db0_dac_seq_done is asserted.

    + +
    8 +

    DAC_RESET

    +

    Write a '1' to this bit to trigger a reset for the + daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done + is asserted.

    + +
    7..6 +

    Reserved

    +

    + +
    5 +

    ADC_ENABLE

    +

    Write a '1' to this bit to trigger the enable sequence for + the daughterboard 0 ADC chain. Write a '0' once + db0_adc_seq_done is asserted.

    + +
    4 +

    ADC_RESET

    +

    Write a '1' to this bit to trigger a reset for the + daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done + is asserted.

    + +
    3..1 +

    Reserved

    +

    + +
    0 +

    FSM_RESET

    +

    Write a '1' to this bit to reset the RF reset controller. + Write a '0' once db0_fsm_reset_done asserts.

    + +
    + +
    + +
    + + +

    Offset 0x12008: RF_RESET_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RF_RESET_STATUS_REG
      offset=0x12008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000152008 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.
    +It uses RegType RF_RESET_STATUS_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +Status register for the RF reset controller. + Verify the FSM ID before polling starting any reset sequence. + Refer to RF*_RESET_CONTROL_REG for instructions on how to use + the status bits in this register.
    + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11 +

    DAC_SEQ_DONE

    +

    This bit asserts ('1') when the DB0 DAC chain reset sequence + is completed. The bitfield deasserts ('0') after + deasserting the issued triggered (enable or reset).

    + +
    10..8 +

    Reserved

    +

    + +
    7 +

    ADC_SEQ_DONE

    +

    This bit asserts ('1') when the DB0 ADC chain reset sequence + is completed. The bitfield deasserts ('0') after + deasserting the issued triggered (enable or reset).

    + +
    6..4 +

    Reserved

    +

    + +
    3 +

    FSM_RESET_DONE

    +

    This bit asserts ('1') when the DB0 RF reset controller FSM + reset sequence is completed. The bitfield deasserts ('0') + after deasserting db0_fsm_reset.

    + +
    2..0 +

    Reserved

    +

    + +
    + +
    + +
    + + +

    Offset 0x13000: RF_AXI_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RF_AXI_STATUS_REG
      offset=0x13000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000153000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.
    +It uses RegType RF_AXI_STATUS_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +Status register for the RF AXI-Stream interfaces.
    + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..30 +

    USER_ADC_TREADY_DB1

    +

    This bitfield is wired to the user's ADC (DB1) AXI-Stream + TReady handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    29..28 +

    USER_ADC_TVALID_DB1

    +

    This bitfield is wired to the user's ADC (DB1) AXI-Stream + TValid handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    27..26 +

    RFDC_ADC_I_TVALID_DB1

    +

    This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream + TValid handshake signals (I portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    25..24 +

    RFDC_ADC_Q_TVALID_DB1

    +

    This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream + TValid handshake signals (Q portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    23..22 +

    RFDC_ADC_I_TREADY_DB1

    +

    This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream + TReady handshake signals (I portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    21..20 +

    RFDC_ADC_Q_TREADY_DB1

    +

    This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream + TReady handshake signals (Q portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    19..18 +

    RFDC_DAC_TVALID_DB1

    +

    This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream + TValid handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    17..16 +

    RFDC_DAC_TREADY_DB1

    +

    This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream + TReady handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    15..14 +

    USER_ADC_TREADY

    +

    This bitfield is wired to the user's ADC (DB0) AXI-Stream + TReady handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    13..12 +

    USER_ADC_TVALID

    +

    This bitfield is wired to the user's ADC (DB0) AXI-Stream + TValid handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    11..10 +

    RFDC_ADC_I_TVALID

    +

    This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream + TValid handshake signals (I portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    9..8 +

    RFDC_ADC_Q_TVALID

    +

    This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream + TValid handshake signals (Q portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    7..6 +

    RFDC_ADC_I_TREADY

    +

    This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream + TReady handshake signals (I portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    5..4 +

    RFDC_ADC_Q_TREADY

    +

    This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream + TReady handshake signals (Q portion). The LSB is channel 0 + and the MSB is channel 1.

    + +
    3..2 +

    RFDC_DAC_TVALID

    +

    This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream + TValid handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    1..0 +

    RFDC_DAC_TREADY

    +

    This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream + TReady handshake signals. The LSB is channel 0 and the MSB + is channel 1.

    + +
    + +
    + +
    + + +

    Offset 0x13008: FABRIC_DSP_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    FABRIC_DSP_REG
      offset=0x13008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000153008 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.
    +It uses RegType FABRIC_DSP_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +This register provides information to the driver on the type + of DSP that is instantiated in the fabric.
    + The X410 platform supports multiple RF daughterboards, each requiring + a different fabric RF DSP chain that works with specific RFDC settings. + Each bandwidth DSP chain has a unique identifier (BW in MHz), this + information is conveyed in this register to let the driver + configure the RFDC with the proper settings. + Also, channel count for the DSP module is included.
    + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..20 +

    FABRIC_DSP_BW   (initialvalue=FABRIC_DSP_BW_NONE)

    +

    Fabric DSP BW in MHz for both daughterboards.

    + +

    + The values for this bitfield are in the FABRIC_DSP_BW_ENUM table. + (show here) +

    +
    + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x000 +

    FABRIC_DSP_BW_NONE

    + +
    1000x064 +

    FABRIC_DSP_BW_100M

    + +
    2000x0C8 +

    FABRIC_DSP_BW_200M

    + +
    4000x190 +

    FABRIC_DSP_BW_400M

    + +
    10000x3E8 +

    FABRIC_DSP_BW_FULL

    + +
    + +

    + This enumerated type is defined in HDL source file common_regs.v. +

    + +
    + +
    + +
    19..18 +

    FABRIC_DSP_RESERVED_DB1   (initialvalue=0)

    +

    Reserved for future use.

    + +
    17..14 +

    FABRIC_DSP_TX_CNT_DB1   (initialvalue=0)

    +

    Fabric DSP TX channel count for daughterboard 0.

    + +
    13..10 +

    FABRIC_DSP_RX_CNT_DB1   (initialvalue=0)

    +

    Fabric DSP RX channel count for daughterboard 0.

    + +
    9..8 +

    FABRIC_DSP_RESERVED   (initialvalue=0)

    +

    Reserved for future use.

    + +
    7..4 +

    FABRIC_DSP_TX_CNT   (initialvalue=0)

    +

    Fabric DSP TX channel count for daughterboard 0.

    + +
    3..0 +

    FABRIC_DSP_RX_CNT   (initialvalue=0)

    +

    Fabric DSP RX channel count for daughterboard 0.

    + +
    + +
    + +
    + + +

    Offset 0x14000: CALIBRATION_DATA Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    CALIBRATION_DATA
      offset=0x14000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000154000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +The fields of this register provide data to all the DAC channels when enabled + by the CALIBRATION_ENABLE register. + +
    + + + + + + + + + + + + + + +
    BitsName
    31..16 +

    Q_DATA

    +

    + +
    15..0 +

    I_DATA

    +

    + +
    + +
    + +
    + + +

    Offset 0x14008: CALIBRATION_ENABLE Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    CALIBRATION_ENABLE
      offset=0x14008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000154008 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +This register enables calibration data in the DAC data path for each of the + four channels. Each of these bits is normally '0'. When written '1', DAC data + for the corresponding channel will be constantly driven with the contents of + the CALIBRATION_DATA register. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..6 +

    Reserved

    +

    + +
    5 +

    ENABLE_CALIBRATION_DATA_3

    +

    Enables calibration data for channel 3.

    + +
    4 +

    ENABLE_CALIBRATION_DATA_2

    +

    Enables calibration data for channel 2.

    + +
    3..2 +

    Reserved

    +

    + +
    1 +

    ENABLE_CALIBRATION_DATA_1

    +

    Enables calibration data for channel 1.

    + +
    0 +

    ENABLE_CALIBRATION_DATA_0

    +

    Enables calibration data for channel 0.

    + +
    + +
    + +
    + + +

    Offset 0x15000: THRESHOLD_STATUS Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    THRESHOLD_STATUS
      offset=0x15000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000155000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +This register shows threshold status for the ADCs. Each bit reflects the + RFDC's real-time ADC status signals, which will assert when the ADC input + signal exceeds the programmed threshold value. The status will remain + asserted until cleared by software. + The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is + the location of the tile in the converter column and ZZ is either 01 (the + lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). + See also the Xilinx document PG269. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11 +

    ADC2_23_THRESHOLD2

    +

    + +
    10 +

    ADC2_23_THRESHOLD1

    +

    + +
    9 +

    ADC2_01_THRESHOLD2

    +

    + +
    8 +

    ADC2_01_THRESHOLD1

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    ADC0_23_THRESHOLD2

    +

    + +
    2 +

    ADC0_23_THRESHOLD1

    +

    + +
    1 +

    ADC0_01_THRESHOLD2

    +

    + +
    0 +

    ADC0_01_THRESHOLD1

    +

    + +
    + +
    + +
    + + +

    Offset 0x16000: RF_PLL_CONTROL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RF_PLL_CONTROL_REG
      offset=0x16000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000156000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +Enable RF MMCM outputs. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..17 +

    Reserved

    +

    + +
    16 +

    CLEAR_DATA_CLK_UNLOCKED

    +

    + +
    15..13 +

    Reserved

    +

    + +
    12 +

    ENABLE_RF_CLK_2X

    +

    + +
    11..9 +

    Reserved

    +

    + +
    8 +

    ENABLE_RF_CLK

    +

    + +
    7..5 +

    Reserved

    +

    + +
    4 +

    ENABLE_DATA_CLK_2X

    +

    + +
    3..1 +

    Reserved

    +

    + +
    0 +

    ENABLE_DATA_CLK

    +

    + +
    + +
    + +
    + + +

    Offset 0x16008: RF_PLL_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RF_PLL_STATUS_REG
      offset=0x16008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000156008 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.

    + +
    + +
    + +Data Clk Pll Status Register + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..21 +

    Reserved

    +

    + +
    20 +

    DATA_CLK_PLL_LOCKED

    +

    + +
    19..17 +

    Reserved

    +

    + +
    16 +

    DATA_CLK_PLL_UNLOCKED_STICKY

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..0 +

    Reserved

    +

    + +
    + +
    + +
    + + +

    Offset 0x17000: ADC_TILEMAP_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    ADC_TILEMAP_REG
      offset=0x17000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000157000 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.
    +It uses RegType ADC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +This register describes how the ADCs map to the respective tiles. It + lets us designate an ADC as channel 0, channel 1, etc. depending on + how those channels are externally connected to the RFSoC.
    + + For every channel, this register stores the tile number and the block + number of the converter. This can be used to then address the correct + converter in the various Xilinx interfaces/APIs.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..30 +

    ADC_TILEMAP_DB1_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 3, daughterboard 1.

    + +
    29..28 +

    ADC_TILEMAP_DB1_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 3, daughterboard 1.

    + +
    27..26 +

    ADC_TILEMAP_DB1_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 2, daughterboard 1.

    + +
    25..24 +

    ADC_TILEMAP_DB1_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 2, daughterboard 1.

    + +
    23..22 +

    ADC_TILEMAP_DB1_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 1, daughterboard 1.

    + +
    21..20 +

    ADC_TILEMAP_DB1_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 1, daughterboard 1.

    + +
    19..18 +

    ADC_TILEMAP_DB1_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 0, daughterboard 1.

    + +
    17..16 +

    ADC_TILEMAP_DB1_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 0, daughterboard 1.

    + +
    15..14 +

    ADC_TILEMAP_DB0_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 3, daughterboard 0.

    + +
    13..12 +

    ADC_TILEMAP_DB0_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 3, daughterboard 0.

    + +
    11..10 +

    ADC_TILEMAP_DB0_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 2, daughterboard 0.

    + +
    9..8 +

    ADC_TILEMAP_DB0_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 2, daughterboard 0.

    + +
    7..6 +

    ADC_TILEMAP_DB0_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 1, daughterboard 0.

    + +
    5..4 +

    ADC_TILEMAP_DB0_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 1, daughterboard 0.

    + +
    3..2 +

    ADC_TILEMAP_DB0_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 0, daughterboard 0.

    + +
    1..0 +

    ADC_TILEMAP_DB0_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 0, daughterboard 0.

    + +
    + +
    + +
    + + +

    Offset 0x17008: DAC_TILEMAP_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    DAC_TILEMAP_REG
      offset=0x17008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000157008 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.
    +It uses RegType DAC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +This register describes how the DACs map to the respective tiles. It + lets us designate an DAC as channel 0, channel 1, etc. depending on + how those channels are externally connected to the RFSoC.
    + + For every channel, this register stores the tile number and the block + number of the converter. This can be used to then address the correct + converter in the various Xilinx interfaces/APIs.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..30 +

    DAC_TILEMAP_DB1_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 3, daughterboard 1.

    + +
    29..28 +

    DAC_TILEMAP_DB1_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 3, daughterboard 1.

    + +
    27..26 +

    DAC_TILEMAP_DB1_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 2, daughterboard 1.

    + +
    25..24 +

    DAC_TILEMAP_DB1_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 2, daughterboard 1.

    + +
    23..22 +

    DAC_TILEMAP_DB1_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 1, daughterboard 1.

    + +
    21..20 +

    DAC_TILEMAP_DB1_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 1, daughterboard 1.

    + +
    19..18 +

    DAC_TILEMAP_DB1_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 0, daughterboard 1.

    + +
    17..16 +

    DAC_TILEMAP_DB1_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 0, daughterboard 1.

    + +
    15..14 +

    DAC_TILEMAP_DB0_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 3, daughterboard 0.

    + +
    13..12 +

    DAC_TILEMAP_DB0_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 3, daughterboard 0.

    + +
    11..10 +

    DAC_TILEMAP_DB0_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 2, daughterboard 0.

    + +
    9..8 +

    DAC_TILEMAP_DB0_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 2, daughterboard 0.

    + +
    7..6 +

    DAC_TILEMAP_DB0_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 1, daughterboard 0.

    + +
    5..4 +

    DAC_TILEMAP_DB0_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 1, daughterboard 0.

    + +
    3..2 +

    DAC_TILEMAP_DB0_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 0, daughterboard 0.

    + +
    1..0 +

    DAC_TILEMAP_DB0_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 0, daughterboard 0.

    + +
    + +
    + +
    + + +

    Offset 0x18000: RFDC_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RFDC_INFO_REG
      offset=0x18000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000158000 + +
    + +

    + +

    Initial Value = 0x00910091 +

    + +

    This register is defined in HDL source file x410_rfdc_regs.v.
    +It uses RegType RFDC_INFO_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +This register provides information about how the RFDC is connected to + the rest of the fabric.
    + Specifically, between the actual RFDC and the RFNoC infrastructure, + there may be additional resampling (if the RFDC resampler cannot handle + all the resampling itself) and it is important to know how wide the + connection from the RFDC gearbox FIFO to the rest of the design is. + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..26 +

    Reserved

    +

    + +
    25..23 +

    RFDC_INFO_SPC_TX_DB1   (initialvalue=1)

    +

    Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.

    + +
    22..20 +

    RFDC_INFO_SPC_RX_DB1   (initialvalue=1)

    +

    Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.

    + +
    19..16 +

    RFDC_INFO_XTRA_RESAMP_DB1   (initialvalue=1)

    +

    Additional resampling happening outside the RFDC for daughterboard 0.

    + +
    15..10 +

    Reserved

    +

    + +
    9..7 +

    RFDC_INFO_SPC_TX   (initialvalue=1)

    +

    Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.

    + +
    6..4 +

    RFDC_INFO_SPC_RX   (initialvalue=1)

    +

    Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.

    + +
    3..0 +

    RFDC_INFO_XTRA_RESAMP   (initialvalue=1)

    +

    Additional resampling happening outside the RFDC for daughterboard 0.

    + +
    + +
    + +
    + +
    + +
    + +

    RFDC_TIMING_REGMAP

    + +

    RFDC_TIMING_REGS

    + +
    + + +

    Offset 0x0000: NCO_RESET_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW
      0x008000
    + +    		 + + + + +
    NCO_RESET_REG
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x008000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file rfdc_timing_control.v.

    + +
    + +
    + +NCO reset control register. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..2 +

    Reserved

    +

    + +
    1r +

    NCO_RESET_DONE

    +

    When 1, indicates that the NCO reset has completed.

    + +
    0w +

    NCO_RESET_START   (Strobe)

    +

    Write a 1 to this bit to start a reset the RFDC's NCO.

    + +
    + +
    + +
    + + +

    Offset 0x0004: GEARBOX_RESET_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW
      0x008000
    + +    		 + + + + +
    GEARBOX_RESET_REG
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x008004 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file rfdc_timing_control.v.

    + +
    + +
    + +Gearbox reset control register. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..2 +

    Reserved

    +

    + +
    1w +

    DAC_RESET   (Strobe)

    +

    This reset is for the gearbox on the DAC data path that is used to + move data from one clock domain to another outside the RFDC. Write + a 1 to this bit to send a reset pulse to the DAC gearbox.

    + +
    0w +

    ADC_RESET   (Strobe)

    +

    This reset is for the gearbox on the ADC data path that is used to + move data from one clock domain to another outside the RFDC. Write + a 1 to this bit to send a reset pulse to the ADC gearbox.

    + +
    + +
    + +
    + +
    + +
    + +

    SPI_REGMAP

    +
    +
    +

    SPI_REGS

    +
    +

    This register map is present for each SPI master.

    +

    For information about the register content and the way to interact with the core see the +documentation +of the SPI master from opencores used internally.

    +

    The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider. +Only 64 bits of data are available via this register interface.

    +

    For the different SPI modes use the following table to derive the bits in CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CPOLCPHATX_NEGRX_NEG
    0010
    0101
    1001
    1110
    +
    + + +

    Offset 0x0000: RX_DATA_LOW Register (R)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + +
    RX_DATA_LOW
      offset=0x0000
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_spi.v.

    + +
    + +
    + +
    +

    Lower 32 bits of the received word. (RxWord[31:0])

    + +
    + +
    + +
    + + +

    Offset 0x0004: RX_DATA_HIGH Register (R)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + +
    RX_DATA_HIGH
      offset=0x0004
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_spi.v.

    + +
    + +
    + +
    +

    Higher 32 bits of the received word. (RxWord[63:32])

    + +
    + +
    + +
    + + +

    Offset 0x0008: TX_DATA_LOW Register (W)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + +
    TX_DATA_LOW
      offset=0x0008
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_spi.v.

    + +
    + +
    + +
    +

    Lower 32 bits of the received word. (TxWord[31:0])

    + +
    + +
    + +
    + + +

    Offset 0x000C: TX_DATA_HIGH Register (W)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + +
    TX_DATA_HIGH
      offset=0x000C
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_spi.v.

    + +
    + +
    + +
    +

    Higher 32 bits of the received word. (TxWord[63:32])

    + +
    + +
    + +
    + + +

    Offset 0x0010: CONTROL Register (R|W)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + +
    CONTROL
      offset=0x0010
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_spi.v.

    + +
    + +
    + +
    +

    Control register

    + +
    + +
    + +
    + + +

    Offset 0x0014: CLOCK_DIVIDER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + +
    CLOCK_DIVIDER
      offset=0x0014
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_spi.v.

    + +
    + +
    + +
    +
    + +
    + + + + + + + + + +
    BitsName
    7..0 +

    Divider

    +

    +

    Clock Divider.

    + +
    + +
    + +
    + + +

    Offset 0x0018: SLAVE_SELECT Register (R|W)

    + + (show extended info) +
    + + + + + + + + + +
    + + + + +
    SLAVE_SELECT
      offset=0x0018
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file ctrlport_to_spi.v.

    + +
    + +
    + +
    +
    + +
    + + + + + + + + + +
    BitsName
    15..0 +

    SS

    +

    +

    Slave select.

    + +
    + +
    + +
    + +
    + +
    + +

    UIO_REGMAP

    +
    +
    +

    UIO_REGS

    +
    +

    UIO

    +
    + + +

    Offset 0x0000: IP Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    IP
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A000 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A000 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Set this port's IP address

    + +
    + +
    + +
    + + +

    Offset 0x0004: UDP Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    UDP
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A004 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A004 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Set the UDP port for CHDR_traffic

    + +
    + +
    + +
    + + +

    Offset 0x0010: BRIDGE_MAC_LSB Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    BRIDGE_MAC_LSB
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A010 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A010 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    If BRIDGE_ENABLE is set use this MAC_ID

    + +
    + +
    + +
    + + +

    Offset 0x0014: BRIDGE_MAC_MSB Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    BRIDGE_MAC_MSB
      offset=0x0014
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A014 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A014 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A014 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A014 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A014 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A014 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A014 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A014 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    If BRIDGE_ENABLE is set use this MAC_ID

    + +
    + +
    + +
    + + +

    Offset 0x0018: BRIDGE_IP Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    BRIDGE_IP
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A018 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A018 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A018 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A018 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A018 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A018 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A018 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A018 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    If BRIDGE_ENABLE is set use this IP Address

    + +
    + +
    + +
    + + +

    Offset 0x001C: BRIDGE_UDP Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    BRIDGE_UDP
      offset=0x001C
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A01C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A01C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A01C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A01C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A01C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A01C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A01C + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A01C + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic

    + +
    + +
    + +
    + + +

    Offset 0x0020: BRIDGE_ENABLE Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    BRIDGE_ENABLE
      offset=0x0020
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A020 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A020 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Bit 0 Controls the following logic

    +
    always_comb begin : bridge_mux
+my_mac            = bridge_en ? bridge_mac_reg : mac_reg;
+my_ip             = bridge_en ? bridge_ip_reg : ip_reg;
+my_udp_chdr_port  = bridge_en ? bridge_udp_port : udp_port;
+end
+
    + +
    + +
    + +
    + + +

    Offset 0x0030: CHDR_DROPPED Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    CHDR_DROPPED
      offset=0x0030
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A030 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A030 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A030 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A030 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A030 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A030 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A030 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A030 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Count the number of Packets dropped that were addressed to the CHDR section.

    + +
    + +
    + +
    + + +

    Offset 0x0034: CPU_DROPPED Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    CPU_DROPPED
      offset=0x0034
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A034 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A034 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A034 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A034 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A034 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A034 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A034 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A034 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +

    Count the number of Packets dropped that were addressed to us, but not to the CHDR section.

    + +
    + +
    + +
    + + +

    Offset 0x0038: PAUSE Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|QSFP_0_0
      0x1200000000
    + +    		 + + + + +
    QSFP_REGMAP|UIO
      0x00A000
    + +    		 + + + + +
    PAUSE
      offset=0x0038
    + +    		 + + + + + +
    + + +Total Offset =
      0x120000A038 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_1
      0x1200010000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120001A038 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_2
      0x1200020000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120002A038 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_0_3
      0x1200030000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120003A038 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_0
      0x1200040000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120004A038 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_1
      0x1200050000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120005A038 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_2
      0x1200060000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120006A038 + +
    + +
    + + + + +
    AXI_HPM0_REGMAP|QSFP_1_3
      0x1200070000
    + +    		 + + + + + +
    + + +Total Offset =
      0x120007A038 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file uhd_regs.v.

    + +
    + +
    + +
    +
    + +
    + + + + + + + + + + + + + + +
    BitsName
    31..16 +

    pause_clear

    +

    +

    If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause. +Pause clear must be less than pause set or terrible things will happen. +The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only +used with 100Gb ethernet

    + +
    15..0 +

    pause_set

    +

    +

    If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only +used with 100Gb ethernet

    + +
    + +
    + +
    + +
    + +
    + +

    VERSIONING_REGS_REGMAP

    + +

    VERSIONING_CONSTANTS

    + +
    + + +

    CPLD_IFC_VERSION Enumeration

    +CPLD interface module.
    + For guidance on when to update these revision numbers, + please refer to the register map documentation accordingly: +
  • Current version: CURRENT_VERSION +
  • Oldest compatible version: OLDEST_COMPATIBLE_VERSION +
  • Version last modified: VERSION_LAST_MODIFIED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x00000000 +

    CPLD_IFC_CURRENT_VERSION_MINOR

    + +
    00x00000000 +

    CPLD_IFC_CURRENT_VERSION_BUILD

    + +
    00x00000000 +

    CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR

    + +
    00x00000000 +

    CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD

    + +
    20x00000002 +

    CPLD_IFC_CURRENT_VERSION_MAJOR

    + +
    20x00000002 +

    CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR

    + +
    5537198170x21011809 +

    CPLD_IFC_VERSION_LAST_MODIFIED_TIME

    + +
    + +

    + This enumerated type is defined in HDL source file cpld_interface_regs.v. +

    + + + +
    + + +

    DB_GPIO_IFC_VERSION Enumeration

    +Daughterboard GPIO interface.
    + For guidance on when to update these revision numbers, + please refer to the register map documentation accordingly: +
  • Current version: CURRENT_VERSION +
  • Oldest compatible version: OLDEST_COMPATIBLE_VERSION +
  • Version last modified: VERSION_LAST_MODIFIED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x00000000 +

    DB_GPIO_IFC_CURRENT_VERSION_MINOR

    + +
    00x00000000 +

    DB_GPIO_IFC_CURRENT_VERSION_BUILD

    + +
    00x00000000 +

    DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR

    + +
    00x00000000 +

    DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD

    + +
    10x00000001 +

    DB_GPIO_IFC_CURRENT_VERSION_MAJOR

    + +
    10x00000001 +

    DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR

    + +
    5379865820x20110616 +

    DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME

    + +
    + +

    + This enumerated type is defined in HDL source file db_gpio_interface.v. +

    + + + +
    + + +

    FPGA_VERSION Enumeration

    +FPGA version.
    + For guidance on when to update these revision numbers, + please refer to the register map documentation accordingly: +
  • Current version: CURRENT_VERSION +
  • Oldest compatible version: OLDEST_COMPATIBLE_VERSION +
  • Version last modified: VERSION_LAST_MODIFIED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x00000000 +

    FPGA_CURRENT_VERSION_MINOR

    + +
    00x00000000 +

    FPGA_CURRENT_VERSION_BUILD

    + +
    00x00000000 +

    FPGA_OLDEST_COMPATIBLE_VERSION_MINOR

    + +
    00x00000000 +

    FPGA_OLDEST_COMPATIBLE_VERSION_BUILD

    + +
    80x00000008 +

    FPGA_CURRENT_VERSION_MAJOR

    + +
    80x00000008 +

    FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR

    + +
    5874729130x23042011 +

    FPGA_VERSION_LAST_MODIFIED_TIME

    + +
    + +

    + This enumerated type is defined in HDL source file x4xx.v. +

    + + + +
    + + +

    RF_CORE_100M_VERSION Enumeration

    +100 MHz RF core.
    + For guidance on when to update these revision numbers, + please refer to the register map documentation accordingly: +
  • Current version: CURRENT_VERSION +
  • Oldest compatible version: OLDEST_COMPATIBLE_VERSION +
  • Version last modified: VERSION_LAST_MODIFIED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x00000000 +

    RF_CORE_100M_CURRENT_VERSION_MINOR

    + +
    00x00000000 +

    RF_CORE_100M_CURRENT_VERSION_BUILD

    + +
    00x00000000 +

    RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR

    + +
    00x00000000 +

    RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD

    + +
    10x00000001 +

    RF_CORE_100M_CURRENT_VERSION_MAJOR

    + +
    10x00000001 +

    RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR

    + +
    5379292390x20102617 +

    RF_CORE_100M_VERSION_LAST_MODIFIED_TIME

    + +
    + +

    + This enumerated type is defined in HDL source file rf_core_100m.v. +

    + + + +
    + + +

    RF_CORE_400M_VERSION Enumeration

    +400 MHz RF core.
    + For guidance on when to update these revision numbers, + please refer to the register map documentation accordingly: +
  • Current version: CURRENT_VERSION +
  • Oldest compatible version: OLDEST_COMPATIBLE_VERSION +
  • Version last modified: VERSION_LAST_MODIFIED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x00000000 +

    RF_CORE_400M_CURRENT_VERSION_MINOR

    + +
    00x00000000 +

    RF_CORE_400M_CURRENT_VERSION_BUILD

    + +
    00x00000000 +

    RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR

    + +
    00x00000000 +

    RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD

    + +
    10x00000001 +

    RF_CORE_400M_CURRENT_VERSION_MAJOR

    + +
    10x00000001 +

    RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR

    + +
    5379292390x20102617 +

    RF_CORE_400M_VERSION_LAST_MODIFIED_TIME

    + +
    + +

    + This enumerated type is defined in HDL source file rf_core_400m.v. +

    + + + + + +

    VERSIONING_REGS

    + +
    + + +

    COMPONENTS_INDEXES Enumeration

    +This enum contains indexes for all the components in the X410 + (both common and app-specific) which version information is + desired to be available for compatibility tracking purposes.
    + + + + + +
    Description Index range Max # of components
    Common components 0 to 23 24
    UHD-specific components 24 to 43 20
    LV-specific components 44 to 63 20
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    0 +

    FPGA_VERSION_INDEX

    + +
    1 +

    CPLD_IFC_INDEX

    + +
    2 +

    DB0_RF_CORE_INDEX

    + +
    3 +

    DB1_RF_CORE_INDEX

    + +
    4 +

    DB0_GPIO_IFC_INDEX

    + +
    5 +

    DB1_GPIO_IFC_INDEX

    + +
    + +

    + This enumerated type is defined in HDL source file x4xx_versioning_regs.v. +

    + +
    + +
    + + +

    Offset 0x0000: CURRENT_VERSION(63:0) Register Array (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|VERSIONING_REGS
      0x000C00
    + +    		 + + + + +
    CURRENT_VERSION
      offset=0x0000 + i*0x10
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x10000A0C00 + i*0x10 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file x4xx_versioning_regs.v.
    +It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

    + +
    + +
    + +Component's current version.
    + This register contains the current component's version implemented in HDL. + The current version shall be used to detect a component being too + old for the driver/software:
    + SW oldest compatible version > Component's current version --> Component is too old. + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..23 +

    MAJOR   (initialvalue=0)

    +

    Major number (max = 511): an increase reflects a breaking change.
    + IMPORTANT! MAJOR must always remain in sync between the component's + CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.

    + Update MAJOR when: +

  • the component has changed and requires a software changes as a result. +
  • the component's bitfields/registers have been modified or deleted. +
  • the component's bitfields/registers are initialized to different value (unexpected by software). +
  • new bitfields/registers are added that require software interaction for the component to operate.

    + +
    • 22..12 +

    MINOR   (initialvalue=0)

    +

    Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of.

    + Update MINOR when: +

  • a new feature is added to the component, which does not conflict with the driver. +
  • minor implementation changes were made to the component which are worth tracking. +
  • the component has added new bitfields/registers that do not require software interaction + (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to + previously undefined bits). +
  • MAJOR is updated (reset MINOR to 0).

    + +
    • 11..0 +

    BUILD   (initialvalue=0)

    +

    Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation, + but that should not impact the component's behavior
    + Eventually, this number is intended to be automatically incremented for any new build.

    + Meanwhile, update BUILD when: +

  • the component's source code changes are not captured by MAJOR or MINOR. +
  • MINOR or MAJOR are updated (reset BUILD to 0).

    + +
    • + +
    + +
    + + +

    Offset 0x0004: OLDEST_COMPATIBLE_VERSION(63:0) Register Array (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|VERSIONING_REGS
      0x000C00
    + +    		 + + + + +
    OLDEST_COMPATIBLE_VERSION
      offset=0x0004 + i*0x10
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x10000A0C04 + i*0x10 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file x4xx_versioning_regs.v.
    +It uses RegType VERSION_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

    + +
    + +
    + +Component's oldest compatible version.
    + This register contains the oldest compatible component's version, that is the oldest + component's implementation that is compatible with the current implementation.
    + The oldest compatible version shall be used to detect a component being too + new for the driver/software:
    + SW current version < Component's oldest compatible version --> Component is too new. + +
    + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..23 +

    MAJOR   (initialvalue=0)

    +

    Major number (max = 511): an increase reflects a breaking change.
    + IMPORTANT! MAJOR must always remain in sync between the component's + CURRENT_VERSION and OLDEST_COMPATIBLE_VERSION registers.

    + Update MAJOR when: +

  • the component has changed and requires a software changes as a result. +
  • the component's bitfields/registers have been modified or deleted. +
  • the component's bitfields/registers are initialized to different value (unexpected by software). +
  • new bitfields/registers are added that require software interaction for the component to operate.

    + +
    • 22..12 +

    MINOR   (initialvalue=0)

    +

    Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of.

    + Update MINOR when: +

  • a new feature is added to the component, which does not conflict with the driver. +
  • minor implementation changes were made to the component which are worth tracking. +
  • the component has added new bitfields/registers that do not require software interaction + (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to + previously undefined bits). +
  • MAJOR is updated (reset MINOR to 0).

    + +
    • 11..0 +

    BUILD   (initialvalue=0)

    +

    Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation, + but that should not impact the component's behavior
    + Eventually, this number is intended to be automatically incremented for any new build.

    + Meanwhile, update BUILD when: +

  • the component's source code changes are not captured by MAJOR or MINOR. +
  • MINOR or MAJOR are updated (reset BUILD to 0).

    + +
    • + +
    + +
    + + +

    Offset 0x0008: VERSION_LAST_MODIFIED(63:0) Register Array (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|VERSIONING_REGS
      0x000C00
    + +    		 + + + + +
    VERSION_LAST_MODIFIED
      offset=0x0008 + i*0x10
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x10000A0C08 + i*0x10 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_versioning_regs.v.
    +It uses RegType TIMESTAMP_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

    + +
    + +
    + +Component's versions update time.
    + This register provides the time stamp for the last modification to + the component's versions (current & oldest compatible). + The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    YY

    +

    This is the year number after 2000 (e.g. 2019 = 0x19).

    + +
    23..16 +

    MM

    +

    + +
    15..8 +

    DD

    +

    + +
    7..0 +

    HH

    +

    + +
    + +
    + +
    + + +

    Offset 0x000C: RESERVED(63:0) Register Array (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + +
    CORE_REGS_REGMAP|VERSIONING_REGS
      0x000C00
    + +    		 + + + + +
    RESERVED
      offset=0x000C + i*0x10
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x10000A0C0C + i*0x10 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x4xx_versioning_regs.v.
    +It uses RegType RESERVED_TYPE which is defined in HDL source file x4xx_versioning_regs.v.

    + +
    + +
    + +Reserved.
    + + +
    + +
    + +
    + + + +
    + +

    XGE_MAC_REGMAP

    +
    +
    +

    OPENCORE_XGE_REGISTERS

    +
    +

    10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf

    +
    + +
    + + + \ No newline at end of file diff --git a/top/x400/ip/Makefile.inc b/top/x400/ip/Makefile.inc index 89c06a1..eff9121 100644 --- a/top/x400/ip/Makefile.inc +++ b/top/x400/ip/Makefile.inc @@ -5,7 +5,6 @@ # include $(IP_DIR)/xge_pcs_pma/Makefile.inc -include $(IP_DIR)/x4xx_ps_rfdc_bd/Makefile.inc include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc @@ -14,11 +13,9 @@ include $(IP_DIR)/axi_inter_2x64_512_bd/Makefile.inc include $(IP_DIR)/axi_inter_4x64_512_bd/Makefile.inc include $(IP_DIR)/axi_inter_1x128_512_bd/Makefile.inc include $(IP_DIR)/axi_inter_2x128_512_bd/Makefile.inc -include $(IP_DIR)/ddr4_64bits/Makefile.inc -include $(IP_DIR)/adc_100m_bd/Makefile.inc -include $(IP_DIR)/adc_400m_bd/Makefile.inc -include $(IP_DIR)/dac_100m_bd/Makefile.inc -include $(IP_DIR)/dac_400m_bd/Makefile.inc +include $(IP_DIR)/axi_inter_4x128_512_bd/Makefile.inc +include $(IP_DIR)/axi_inter_1x512_512_bd/Makefile.inc +include $(IP_DIR)/axi_inter_2x512_512_bd/Makefile.inc include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc include $(IP_DIR)/fifo_short_2clk/Makefile.inc include $(IP_DIR)/fifo_4k_2clk/Makefile.inc @@ -27,6 +24,15 @@ include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc include $(IP_DIR)/hb47_1to2/Makefile.inc include $(IP_DIR)/hb47_2to1/Makefile.inc +ifdef X410 +include $(IP_DIR)/ddr4_64bits/Makefile.inc +include $(IP_DIR)/adc_100m_bd/Makefile.inc +include $(IP_DIR)/adc_400m_bd/Makefile.inc +include $(IP_DIR)/dac_100m_bd/Makefile.inc +include $(IP_DIR)/dac_400m_bd/Makefile.inc +include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc +endif + BD_SRCS = \ $(IP_X4XX_PS_RFDC_BD_SRCS) \ $(IP_X4XX_PS_RFDC_HDL_SRCS) \ @@ -40,21 +46,27 @@ $(IP_AXI_INTER_2X64_512_BD_SRCS) \ $(IP_AXI_INTER_4X64_512_BD_SRCS) \ $(IP_AXI_INTER_1X128_512_BD_SRCS) \ $(IP_AXI_INTER_2X128_512_BD_SRCS) \ -$(IP_ADC_100M_BD_SRCS) \ -$(IP_ADC_100M_HDL_SRCS) \ -$(IP_DAC_100M_BD_SRCS) \ -$(IP_DAC_100M_HDL_SRCS) \ -$(IP_ADC_400M_BD_SRCS) \ -$(IP_ADC_400M_HDL_SRCS) \ -$(IP_DAC_400M_BD_SRCS) \ -$(IP_DAC_400M_HDL_SRCS) \ +$(IP_AXI_INTER_4X128_512_BD_SRCS) \ +$(IP_AXI_INTER_1X512_512_BD_SRCS) \ +$(IP_AXI_INTER_2X512_512_BD_SRCS) \ $(IP_100G_BD_SRCS) \ $(IP_100G_HDL_SRCS) \ $(IP_AXI_ETH_DMA_BD_SRCS) \ $(IP_AXI_ETH_DMA_BD_HDL_SRCS) +ifdef X410 +BD_SRCS += \ +$(IP_ADC_100M_BD_SRCS) \ +$(IP_ADC_100M_HDL_SRCS) \ +$(IP_DAC_100M_BD_SRCS) \ +$(IP_DAC_100M_HDL_SRCS) \ +$(IP_ADC_400M_BD_SRCS) \ +$(IP_ADC_400M_HDL_SRCS) \ +$(IP_DAC_400M_BD_SRCS) \ +$(IP_DAC_400M_HDL_SRCS) +endif + IP_XCI_SRCS = \ -$(IP_DDR4_64BITS_SRCS) \ $(IP_XGE_PCS_PMA_SRCS) \ $(IP_AXI64_4K_2CLK_FIFO_SRCS) \ $(IP_FIFO_SHORT_2CLK_SRCS) \ @@ -62,6 +74,11 @@ $(IP_FIFO_4K_2CLK_SRCS) \ $(IP_HB47_1TO2_SRCS) \ $(IP_HB47_2TO1_SRCS) \ +ifdef X410 +IP_XCI_SRCS += \ +$(IP_DDR4_64BITS_SRCS) +endif + BD_OUTPUTS = \ $(BD_X4XX_PS_RFDC_BD_OUTS) \ $(BD_AXI_INTERCONNECT_APP_BD_OUTS) \ @@ -72,15 +89,21 @@ $(BD_AXI_INTER_2x64_512_BD_OUTS) \ $(BD_AXI_INTER_4x64_512_BD_OUTS) \ $(BD_AXI_INTER_1X128_512_BD_OUTS) \ $(BD_AXI_INTER_2X128_512_BD_OUTS) \ -$(BD_ADC_100M_BD_OUTS) \ -$(BD_ADC_400M_BD_OUTS) \ -$(BD_DAC_100M_BD_OUTS) \ -$(BD_DAC_400M_BD_OUTS) \ +$(BD_AXI_INTER_4x128_512_BD_OUTS) \ +$(BD_AXI_INTER_1X512_512_BD_OUTS) \ +$(BD_AXI_INTER_2X512_512_BD_OUTS) \ $(BD_100G_BD_OUTS) \ $(BD_AXI_ETH_DMA_BD_OUTS) +ifdef X410 +BD_OUTPUTS += \ +$(BD_ADC_100M_BD_OUTS) \ +$(BD_ADC_400M_BD_OUTS) \ +$(BD_DAC_100M_BD_OUTS) \ +$(BD_DAC_400M_BD_OUTS) +endif + IP_SYNTH_OUTPUTS = \ -$(IP_DDR4_64BITS_OUTS) \ $(IP_XGE_PCS_PMA_OUTS) \ $(IP_AXI64_4K_2CLK_FIFO_OUTS) \ $(IP_FIFO_SHORT_2CLK_OUTS) \ @@ -88,6 +111,11 @@ $(IP_FIFO_4K_2CLK_OUTS) \ $(IP_HB47_1TO2_OUTS) \ $(IP_HB47_2TO1_OUTS) \ +ifdef X410 +IP_SYNTH_OUTPUTS += \ +$(IP_DDR4_64BITS_OUTS) +endif + IP_HDL_SIM_SRCS = \ $(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \ $(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \ diff --git a/top/x400/ip/axi_inter_1x512_512_bd/Makefile.inc b/top/x400/ip/axi_inter_1x512_512_bd/Makefile.inc new file mode 100644 index 0000000..6d624fb --- /dev/null +++ b/top/x400/ip/axi_inter_1x512_512_bd/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTER_1X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_1x512_512_bd/, \ +axi_inter_1x512_512_bd.tcl \ +) + +IP_AXI_INTER_1X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \ +axi_inter_1x512_512_bd.tcl \ +) + +IP_AXI_INTER_1X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \ +axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.bd \ +) + +BD_AXI_INTER_1X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \ +axi_inter_1x512_512_bd.bd.out \ +axi_inter_1x512_512_bd/axi_inter_1x512_512_bd_ooc.xdc \ +axi_inter_1x512_512_bd/synth/axi_inter_1x512_512_bd.v \ +) + +.INTERMEDIATE: IP_AXI_INTER_1X512_512_BD_TRGT +$(IP_AXI_INTER_1X512_512_BD_SRCS) $(BD_AXI_INTER_1X512_512_BD_OUTS) $(IP_AXI_INTER_1X512_512_BDTCL_SRCS): IP_AXI_INTER_1X512_512_BD_TRGT + @: + +IP_AXI_INTER_1X512_512_BD_TRGT: $(IP_AXI_INTER_1X512_512_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_inter_1x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.tcl b/top/x400/ip/axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.tcl new file mode 100644 index 0000000..90050ca --- /dev/null +++ b/top/x400/ip/axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.tcl @@ -0,0 +1,314 @@ + +################################################################ +# This is a generated script based on design: axi_inter_1x512_512_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2021.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_inter_1x512_512_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-2-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_inter_1x512_512_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_clock_converter:2.1\ +xilinx.com:ip:axi_data_fifo:2.1\ +xilinx.com:ip:axi_register_slice:2.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set M_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4} \ + ] $M_AXI + + set S_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI + + + # Create ports + set M_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M_AXI} \ + CONFIG.ASSOCIATED_RESET {M_AXI_ARESETN} \ + ] $M_AXI_ACLK + set M_AXI_ARESETN [ create_bd_port -dir I -type rst M_AXI_ARESETN ] + set S_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S_AXI} \ + CONFIG.ASSOCIATED_RESET {S_AXI_ARESETN} \ + ] $S_AXI_ACLK + set S_AXI_ARESETN [ create_bd_port -dir I -type rst S_AXI_ARESETN ] + + # Create instance: axi_clock_converter_0, and set properties + set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] + + # Create instance: axi_data_fifo_0, and set properties + set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.READ_FIFO_DEPTH {512} \ + CONFIG.WRITE_FIFO_DEPTH {512} \ + ] $axi_data_fifo_0 + + # Create instance: axi_data_fifo_1, and set properties + set axi_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_1 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.READ_FIFO_DEPTH {512} \ + CONFIG.WRITE_FIFO_DEPTH {512} \ + ] $axi_data_fifo_1 + + # Create instance: axi_register_slice_0, and set properties + set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {1} \ + ] $axi_register_slice_0 + + # Create instance: axi_register_slice_2, and set properties + set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {2} \ + ] $axi_register_slice_2 + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI] + connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_data_fifo_0/S_AXI] + connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI] + connect_bd_intf_net -intf_net axi_data_fifo_1_M_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_data_fifo_1/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_data_fifo_1/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_ports M_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI] + + # Create port connections + connect_bd_net -net m_axi_aclk_0_1 [get_bd_ports M_AXI_ACLK] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_register_slice_2/aclk] + connect_bd_net -net m_axi_aresetn_0_1 [get_bd_ports M_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axi_register_slice_2/aresetn] + connect_bd_net -net s_axi_aclk_0_1 [get_bd_ports S_AXI_ACLK] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_data_fifo_1/aclk] [get_bd_pins axi_register_slice_0/aclk] + connect_bd_net -net s_axi_aresetn_0_1 [get_bd_ports S_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_data_fifo_1/aresetn] [get_bd_pins axi_register_slice_0/aresetn] + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/top/x400/ip/axi_inter_2x512_512_bd/Makefile.inc b/top/x400/ip/axi_inter_2x512_512_bd/Makefile.inc new file mode 100644 index 0000000..09c5118 --- /dev/null +++ b/top/x400/ip/axi_inter_2x512_512_bd/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTER_2X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x512_512_bd/, \ +axi_inter_2x512_512_bd.tcl \ +) + +IP_AXI_INTER_2X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \ +axi_inter_2x512_512_bd.tcl \ +) + +IP_AXI_INTER_2X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \ +axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.bd \ +) + +BD_AXI_INTER_2X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x512_512_bd/, \ +axi_inter_2x512_512_bd.bd.out \ +axi_inter_2x512_512_bd/axi_inter_2x512_512_bd_ooc.xdc \ +axi_inter_2x512_512_bd/synth/axi_inter_2x512_512_bd.v \ +) + +.INTERMEDIATE: IP_AXI_INTER_2X512_512_BD_TRGT +$(IP_AXI_INTER_2X512_512_BD_SRCS) $(BD_AXI_INTER_2X512_512_BD_OUTS) $(IP_AXI_INTER_2X512_512_BDTCL_SRCS): IP_AXI_INTER_2X512_512_BD_TRGT + @: + +IP_AXI_INTER_2X512_512_BD_TRGT: $(IP_AXI_INTER_2X512_512_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_inter_2x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.tcl b/top/x400/ip/axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.tcl new file mode 100644 index 0000000..dc6f951 --- /dev/null +++ b/top/x400/ip/axi_inter_2x512_512_bd/axi_inter_2x512_512_bd.tcl @@ -0,0 +1,380 @@ + +################################################################ +# This is a generated script based on design: axi_inter_2x512_512_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2021.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_inter_2x512_512_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-2-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_inter_2x512_512_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_clock_converter:2.1\ +xilinx.com:ip:axi_crossbar:2.1\ +xilinx.com:ip:axi_data_fifo:2.1\ +xilinx.com:ip:axi_register_slice:2.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4} \ + ] $M0_AXI + + set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S0_AXI + + set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S1_AXI + + + # Create ports + set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M0_AXI} \ + CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \ + ] $M0_AXI_ACLK + set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $M0_AXI_ARESETN + set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \ + CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN:S0_AXI_ARESETN} \ + ] $S0_AXI_ACLK + set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ] + + # Create instance: axi_clock_converter_0, and set properties + set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ] + + # Create instance: axi_crossbar_0, and set properties + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {2} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $axi_crossbar_0 + + # Create instance: axi_data_fifo_0, and set properties + set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.READ_FIFO_DEPTH {512} \ + CONFIG.WRITE_FIFO_DEPTH {512} \ + ] $axi_data_fifo_0 + + # Create instance: axi_data_fifo_1, and set properties + set axi_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_1 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.READ_FIFO_DEPTH {512} \ + CONFIG.WRITE_FIFO_DEPTH {512} \ + ] $axi_data_fifo_1 + + # Create instance: axi_data_fifo_2, and set properties + set axi_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_2 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.READ_FIFO_DEPTH {512} \ + CONFIG.WRITE_FIFO_DEPTH {512} \ + ] $axi_data_fifo_2 + + # Create instance: axi_register_slice_0, and set properties + set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {1} \ + ] $axi_register_slice_0 + + # Create instance: axi_register_slice_1, and set properties + set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {1} \ + ] $axi_register_slice_1 + + # Create instance: axi_register_slice_2, and set properties + set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {2} \ + ] $axi_register_slice_2 + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI] + connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI] + connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_data_fifo_0/S_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins axi_crossbar_0/M00_AXI] + connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI] + connect_bd_intf_net -intf_net axi_data_fifo_1_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_data_fifo_1/M_AXI] + connect_bd_intf_net -intf_net axi_data_fifo_2_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_data_fifo_2/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_data_fifo_1/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_data_fifo_2/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI] + + # Create port connections + connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_register_slice_2/aclk] + connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axi_register_slice_2/aresetn] + connect_bd_net -net s_axi_aclk_0_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_data_fifo_1/aclk] [get_bd_pins axi_data_fifo_2/aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] + connect_bd_net -net s_axi_aresetn_0_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_data_fifo_1/aresetn] [get_bd_pins axi_data_fifo_2/aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/top/x400/ip/axi_inter_4x128_512_bd/Makefile.inc b/top/x400/ip/axi_inter_4x128_512_bd/Makefile.inc new file mode 100644 index 0000000..371da52 --- /dev/null +++ b/top/x400/ip/axi_inter_4x128_512_bd/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTER_4X128_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_4x128_512_bd/, \ +axi_inter_4x128_512_bd.tcl \ +) + +IP_AXI_INTER_4X128_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \ +axi_inter_4x128_512_bd.tcl \ +) + +IP_AXI_INTER_4X128_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \ +axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.bd \ +) + +BD_AXI_INTER_4X128_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_4x128_512_bd/, \ +axi_inter_4x128_512_bd.bd.out \ +axi_inter_4x128_512_bd/axi_inter_4x128_512_bd_ooc.xdc \ +axi_inter_4x128_512_bd/synth/axi_inter_4x128_512_bd.v \ +) + +.INTERMEDIATE: IP_AXI_INTER_4X128_512_BD_TRGT +$(IP_AXI_INTER_4X128_512_BD_SRCS) $(BD_AXI_INTER_4X128_512_BD_OUTS) $(IP_AXI_INTER_4X128_512_BDTCL_SRCS): IP_AXI_INTER_4X128_512_BD_TRGT + @: + +IP_AXI_INTER_4X128_512_BD_TRGT: $(IP_AXI_INTER_4X128_512_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,axi_inter_4x128_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi) diff --git a/top/x400/ip/axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.tcl b/top/x400/ip/axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.tcl new file mode 100644 index 0000000..f88eb53 --- /dev/null +++ b/top/x400/ip/axi_inter_4x128_512_bd/axi_inter_4x128_512_bd.tcl @@ -0,0 +1,823 @@ + +################################################################ +# This is a generated script based on design: axi_inter_4x128_512_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2021.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source axi_inter_4x128_512_bd_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffve1156-2-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name axi_inter_4x128_512_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_crossbar:2.1\ +xilinx.com:ip:axi_dwidth_converter:2.1\ +xilinx.com:ip:axi_register_slice:2.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4} \ + ] $M0_AXI + + set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S0_AXI + + set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S1_AXI + + set S2_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S2_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S2_AXI + + set S3_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S3_AXI ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.FREQ_HZ {350000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S3_AXI + + + # Create ports + set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {M0_AXI} \ + CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \ + ] $M0_AXI_ACLK + set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $M0_AXI_ARESETN + set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI:S2_AXI:S3_AXI} \ + CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \ + ] $S0_AXI_ACLK + set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ] + + # Create instance: axi_crossbar_0, and set properties + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {4} \ + CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A00_ADDR_WIDTH {0} \ + CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A00_ADDR_WIDTH {0} \ + CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A00_ADDR_WIDTH {0} \ + CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A00_ADDR_WIDTH {0} \ + CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A00_ADDR_WIDTH {0} \ + CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A00_ADDR_WIDTH {0} \ + CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A00_ADDR_WIDTH {0} \ + CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A00_ADDR_WIDTH {0} \ + CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A00_ADDR_WIDTH {0} \ + CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A00_ADDR_WIDTH {0} \ + CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A00_ADDR_WIDTH {0} \ + CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A00_ADDR_WIDTH {0} \ + CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A00_ADDR_WIDTH {0} \ + CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A00_ADDR_WIDTH {0} \ + CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A00_ADDR_WIDTH {0} \ + CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {4} \ + CONFIG.S01_BASE_ID {0x00000004} \ + CONFIG.S02_BASE_ID {0x00000008} \ + CONFIG.S03_BASE_ID {0x0000000c} \ + CONFIG.S04_BASE_ID {0x00000010} \ + CONFIG.S05_BASE_ID {0x00000014} \ + CONFIG.S06_BASE_ID {0x00000018} \ + CONFIG.S07_BASE_ID {0x0000001c} \ + CONFIG.S08_BASE_ID {0x00000020} \ + CONFIG.S09_BASE_ID {0x00000024} \ + CONFIG.S10_BASE_ID {0x00000028} \ + CONFIG.S11_BASE_ID {0x0000002c} \ + CONFIG.S12_BASE_ID {0x00000030} \ + CONFIG.S13_BASE_ID {0x00000034} \ + CONFIG.S14_BASE_ID {0x00000038} \ + CONFIG.S15_BASE_ID {0x0000003c} \ + ] $axi_crossbar_0 + + # Create instance: axi_dwidth_converter_0, and set properties + set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ] + set_property -dict [ list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {128} \ + CONFIG.SI_ID_WIDTH {1} \ + CONFIG.SYNCHRONIZATION_STAGES {3} \ + ] $axi_dwidth_converter_0 + + # Create instance: axi_dwidth_converter_1, and set properties + set axi_dwidth_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_1 ] + set_property -dict [ list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {128} \ + CONFIG.SI_ID_WIDTH {1} \ + CONFIG.SYNCHRONIZATION_STAGES {3} \ + ] $axi_dwidth_converter_1 + + # Create instance: axi_dwidth_converter_2, and set properties + set axi_dwidth_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_2 ] + set_property -dict [ list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {128} \ + CONFIG.SI_ID_WIDTH {1} \ + CONFIG.SYNCHRONIZATION_STAGES {3} \ + ] $axi_dwidth_converter_2 + + # Create instance: axi_dwidth_converter_3, and set properties + set axi_dwidth_converter_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_3 ] + set_property -dict [ list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.MI_DATA_WIDTH {512} \ + CONFIG.SI_DATA_WIDTH {128} \ + CONFIG.SI_ID_WIDTH {1} \ + CONFIG.SYNCHRONIZATION_STAGES {3} \ + ] $axi_dwidth_converter_3 + + # Create instance: axi_register_slice_0, and set properties + set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_0 + + # Create instance: axi_register_slice_1, and set properties + set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_1 + + # Create instance: axi_register_slice_2, and set properties + set axi_register_slice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_2 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_2 + + # Create instance: axi_register_slice_3, and set properties + set axi_register_slice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_3 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {128} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_3 + + # Create instance: axi_register_slice_4, and set properties + set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_4 + + # Create instance: axi_register_slice_5, and set properties + set axi_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_5 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_5 + + # Create instance: axi_register_slice_6, and set properties + set axi_register_slice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_6 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_6 + + # Create instance: axi_register_slice_7, and set properties + set axi_register_slice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_7 ] + set_property -dict [ list \ + CONFIG.DATA_WIDTH {512} \ + CONFIG.ID_WIDTH {1} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_7 + + # Create instance: axi_register_slice_8, and set properties + set axi_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_8 ] + set_property -dict [ list \ + CONFIG.ID_WIDTH {4} \ + CONFIG.REG_AR {1} \ + CONFIG.REG_AW {1} \ + CONFIG.REG_B {1} \ + ] $axi_register_slice_8 + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_0_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI] + connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI] + connect_bd_intf_net -intf_net S_AXI_2_1 [get_bd_intf_ports S2_AXI] [get_bd_intf_pins axi_register_slice_2/S_AXI] + connect_bd_intf_net -intf_net S_AXI_3_1 [get_bd_intf_ports S3_AXI] [get_bd_intf_pins axi_register_slice_3/S_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_register_slice_8/S_AXI] + connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins axi_register_slice_4/S_AXI] + connect_bd_intf_net -intf_net axi_dwidth_converter_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/M_AXI] [get_bd_intf_pins axi_register_slice_5/S_AXI] + connect_bd_intf_net -intf_net axi_dwidth_converter_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/M_AXI] [get_bd_intf_pins axi_register_slice_6/S_AXI] + connect_bd_intf_net -intf_net axi_dwidth_converter_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_3/M_AXI] [get_bd_intf_pins axi_register_slice_7/S_AXI] + connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_2_M_AXI [get_bd_intf_pins axi_dwidth_converter_2/S_AXI] [get_bd_intf_pins axi_register_slice_2/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_3_M_AXI [get_bd_intf_pins axi_dwidth_converter_3/S_AXI] [get_bd_intf_pins axi_register_slice_3/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_4_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_register_slice_4/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_5_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_register_slice_5/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_6_M_AXI [get_bd_intf_pins axi_crossbar_0/S02_AXI] [get_bd_intf_pins axi_register_slice_6/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_7_M_AXI [get_bd_intf_pins axi_crossbar_0/S03_AXI] [get_bd_intf_pins axi_register_slice_7/M_AXI] + connect_bd_intf_net -intf_net axi_register_slice_8_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_8/M_AXI] + + # Create port connections + connect_bd_net -net S0_AXI_ACLK [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_dwidth_converter_1/s_axi_aclk] [get_bd_pins axi_dwidth_converter_2/s_axi_aclk] [get_bd_pins axi_dwidth_converter_3/s_axi_aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_2/aclk] [get_bd_pins axi_register_slice_3/aclk] + connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] + connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_dwidth_converter_0/m_axi_aclk] [get_bd_pins axi_dwidth_converter_1/m_axi_aclk] [get_bd_pins axi_dwidth_converter_2/m_axi_aclk] [get_bd_pins axi_dwidth_converter_3/m_axi_aclk] [get_bd_pins axi_register_slice_4/aclk] [get_bd_pins axi_register_slice_5/aclk] [get_bd_pins axi_register_slice_6/aclk] [get_bd_pins axi_register_slice_7/aclk] [get_bd_pins axi_register_slice_8/aclk] + connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/m_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/m_axi_aresetn] [get_bd_pins axi_register_slice_4/aresetn] [get_bd_pins axi_register_slice_5/aresetn] [get_bd_pins axi_register_slice_6/aresetn] [get_bd_pins axi_register_slice_8/aresetn] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v b/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v new file mode 100644 index 0000000..4e95205 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/common_regs.v @@ -0,0 +1,509 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: common_regs +// Description: +// Common registers definition within the x4xx_ps_rfdc_bd between +// different x4xx variants. + +//XmlParse xml_on +// +// +// This is the map for the register space that the Processing System's +// M_AXI_HPM0_FPD port (AXI4 master interface) has access to. +// This port has a 40-bit address bus. +// +// +// +// Space reserved for RPU access +// +// +// Register space for the JTAG engine for MB CPLD programming. +// +// +// Register space reserved for future use. +// +// +// MPM endpoint fro MB/DB communication. +// +// +// Register space reserved for mboard-regs (Core). +// +// +// AXI DMA engine for internal Ethernet interface. +// +// +// Misc. registers for internal Ethernet. +// +// +// Register space occupied by the Xilinx RFDC IP block. +// +// +// Register space for RFDC control/status registers. +// +// +// +// +// +// +// This is the map that the nixge driver uses in Ethernet DMA to +// move data between the Processing System's architecture and the fabric. +// This map is a combination of two main components: a Xilix AXI DMA engine +// and some registers for MAC/PHY control. +// +// +// +// +// Refer to Xilinx' AXI DMA v7.1 IP product guide for further +// information on this register map: +// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf +// +// +// +// MAC/PHY control for the Ethernet interface. +// +// +// +// +// +// This is a regmap to document the different ports that have access to the PS system memory. +// Each port may have different restrictions on system memory. See the corresponding window +// for details +// +// +// +// +// The HPC0 port of the PS is used for general purpose cache-coherent accesses +// to the PS system memory. Different applications may use it for different +// purposes. Its access is configured as follows: {br} +// {table border="1"} +// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr} +// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr} +// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr} +// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr} +// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr} +// {/table} +// +// +// +// +// +// +// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave +// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx. +// Its access is configured as follows: {br} +// {table border="1"} +// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr} +// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr} +// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr} +// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr} +// {/table} +// +// +// +// +// +// +// +// +// Control register for the RF reset controller. +// Verify the FSM ID before polling starting any reset sequence. +// To use the SW reset triggers: Wait until DB*_DONE is de-asserted. +// Assert either the *_RESET or *_ENABLE bitfields. +// Wait until DB*_DONE is asserted to release the trigger. +// The DB*_DONE signal should then de-assert.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// +// +// +// Write a '1' to this bit to reset the RF reset controller. +// Write a '0' once db0_fsm_reset_done asserts. +// +// +// +// +// Write a '1' to this bit to trigger a reset for the +// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done +// is asserted. +// +// +// +// +// Write a '1' to this bit to trigger the enable sequence for +// the daughterboard 0 ADC chain. Write a '0' once +// db0_adc_seq_done is asserted. +// +// +// +// +// Write a '1' to this bit to trigger a reset for the +// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done +// is asserted. +// +// +// +// +// Write a '1' to this bit to trigger the enable sequence for +// the daughterboard 0 DAC chain. Write a '0' once +// db0_dac_seq_done is asserted. +// +// +// +// +// +// +// Status register for the RF reset controller. +// Verify the FSM ID before polling starting any reset sequence. +// Refer to RF*_RESET_CONTROL_REG for instructions on how to use +// the status bits in this register.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// +// +// +// This bit asserts ('1') when the DB0 RF reset controller FSM +// reset sequence is completed. The bitfield deasserts ('0') +// after deasserting db0_fsm_reset. +// +// +// +// +// This bit asserts ('1') when the DB0 ADC chain reset sequence +// is completed. The bitfield deasserts ('0') after +// deasserting the issued triggered (enable or reset). +// +// +// +// +// This bit asserts ('1') when the DB0 DAC chain reset sequence +// is completed. The bitfield deasserts ('0') after +// deasserting the issued triggered (enable or reset). +// +// +// +// +// +// +// Status register for the RF AXI-Stream interfaces.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// +// +// +// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TReady handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TReady handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TValid handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream +// TValid handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the user's ADC (DB0) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// This bitfield is wired to the user's ADC (DB0) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TReady handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TReady handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TValid handshake signals (Q portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream +// TValid handshake signals (I portion). The LSB is channel 0 +// and the MSB is channel 1. +// +// +// +// +// This bitfield is wired to the user's ADC (DB1) AXI-Stream +// TValid handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// This bitfield is wired to the user's ADC (DB1) AXI-Stream +// TReady handshake signals. The LSB is channel 0 and the MSB +// is channel 1. +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// This register provides information to the driver on the type +// of DSP that is instantiated in the fabric.{BR/} +// The X410 platform supports multiple RF daughterboards, each requiring +// a different fabric RF DSP chain that works with specific RFDC settings. +// Each bandwidth DSP chain has a unique identifier (BW in MHz), this +// information is conveyed in this register to let the driver +// configure the RFDC with the proper settings. +// Also, channel count for the DSP module is included.{BR/} +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// +// +// Fabric DSP RX channel count for daughterboard 0. +// +// +// Fabric DSP TX channel count for daughterboard 0. +// +// +// Reserved for future use. +// +// +// Fabric DSP RX channel count for daughterboard 0. +// +// +// Fabric DSP TX channel count for daughterboard 0. +// +// +// Reserved for future use. +// +// +// Fabric DSP BW in MHz for both daughterboards. +// +// +// +// +// +// This register provides information about how the RFDC is connected to +// the rest of the fabric.{BR/} +// Specifically, between the actual RFDC and the RFNoC infrastructure, +// there may be additional resampling (if the RFDC resampler cannot handle +// all the resampling itself) and it is important to know how wide the +// connection from the RFDC gearbox FIFO to the rest of the design is. +// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is +// merely for documentation.{/b} +// +// +// Additional resampling happening outside the RFDC for daughterboard 0. +// +// +// Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0. +// +// +// Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0. +// +// +// Additional resampling happening outside the RFDC for daughterboard 0. +// +// +// Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1. +// +// +// Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1. +// +// +// +// +// +// This register describes how the ADCs map to the respective tiles. It +// lets us designate an ADC as channel 0, channel 1, etc. depending on +// how those channels are externally connected to the RFSoC.{BR/} +// +// For every channel, this register stores the tile number and the block +// number of the converter. This can be used to then address the correct +// converter in the various Xilinx interfaces/APIs. +// +// +// Tile number of the ADC for channel 0, daughterboard 0. +// +// +// Block number (within the tile) of the ADC for channel 0, daughterboard 0. +// +// +// Tile number of the ADC for channel 1, daughterboard 0. +// +// +// Block number (within the tile) of the ADC for channel 1, daughterboard 0. +// +// +// Tile number of the ADC for channel 2, daughterboard 0. +// +// +// Block number (within the tile) of the ADC for channel 2, daughterboard 0. +// +// +// Tile number of the ADC for channel 3, daughterboard 0. +// +// +// Block number (within the tile) of the ADC for channel 3, daughterboard 0. +// +// +// Tile number of the ADC for channel 0, daughterboard 1. +// +// +// Block number (within the tile) of the ADC for channel 0, daughterboard 1. +// +// +// Tile number of the ADC for channel 1, daughterboard 1. +// +// +// Block number (within the tile) of the ADC for channel 1, daughterboard 1. +// +// +// Tile number of the ADC for channel 2, daughterboard 1. +// +// +// Block number (within the tile) of the ADC for channel 2, daughterboard 1. +// +// +// Tile number of the ADC for channel 3, daughterboard 1. +// +// +// Block number (within the tile) of the ADC for channel 3, daughterboard 1. +// +// +// +// +// This register describes how the DACs map to the respective tiles. It +// lets us designate an DAC as channel 0, channel 1, etc. depending on +// how those channels are externally connected to the RFSoC.{BR/} +// +// For every channel, this register stores the tile number and the block +// number of the converter. This can be used to then address the correct +// converter in the various Xilinx interfaces/APIs. +// +// +// Tile number of the DAC for channel 0, daughterboard 0. +// +// +// Block number (within the tile) of the DAC for channel 0, daughterboard 0. +// +// +// Tile number of the DAC for channel 1, daughterboard 0. +// +// +// Block number (within the tile) of the DAC for channel 1, daughterboard 0. +// +// +// Tile number of the DAC for channel 2, daughterboard 0. +// +// +// Block number (within the tile) of the DAC for channel 2, daughterboard 0. +// +// +// Tile number of the DAC for channel 3, daughterboard 0. +// +// +// Block number (within the tile) of the DAC for channel 3, daughterboard 0. +// +// +// Tile number of the DAC for channel 0, daughterboard 1. +// +// +// Block number (within the tile) of the DAC for channel 0, daughterboard 1. +// +// +// Tile number of the DAC for channel 1, daughterboard 1. +// +// +// Block number (within the tile) of the DAC for channel 1, daughterboard 1. +// +// +// Tile number of the DAC for channel 2, daughterboard 1. +// +// +// Block number (within the tile) of the DAC for channel 2, daughterboard 1. +// +// +// Tile number of the DAC for channel 3, daughterboard 1. +// +// +// Block number (within the tile) of the DAC for channel 3, daughterboard 1. +// +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/uhd_regs.v b/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/uhd_regs.v new file mode 100644 index 0000000..329393b --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/common/regmap/uhd_regs.v @@ -0,0 +1,336 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: uhd_regs +// Description: +// Registers definition within the x4xx_ps_rfdc_bd IP. + +//XmlParse xml_on +// +// +// +// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187. +// +// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf +// +// +// +// + +//XmlParse xml_on +// +// +// +// +// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf +// +// +// +// + + +// +// +// +// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11 +// +// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf +// +// +// +// + +// +// +// +// +// +// +// nixge (maps to 10g mac if present) +// +// +// +// +// Constant indicating version for this space. +// Not used by the NIXGE driver (12/4/2020) +// +// +// +// +// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL. +// +// +// +// +// Generically means that a connection with a peer has been established. Specific +// meaning varies based on the MGT_PROTOCOL. +// +// +// +// +// Constant indicating what flavor of communication this port is using +// +// - 0 = NONE +// - 1 = 1GbE +// - 2 = 10GbE +// - 3 = Aurora +// - 4 = WhiteRabbit +// - 5 = 100GbE +// +// +// +// +// +// Constant indicating which port this register is hooked to +// +// - 0 = QSFP0 +// - 1 = QSFP1 +// +// +// +// +// +// +// Definition of this register depends on Protocol +// +// **10GBE** +// +// *READ - Status* +// +// - 0 = status_crc_error +// - 1 = status_fragment_error +// - 2 = status_txdfifo_ovflow +// - 3 = status_txdfifo_udflow +// - 4 = status_rxdfifo_ovflow +// - 5 = status_rxdfifo_udflow +// - 6 = status_pause_frame_rx +// - 7 = status_local_fault +// - 8 = status_remote_fault +// +// *WRITE - Ctl* +// +// - 0 = ctrl_tx_enable +// +// **100 GBE** +// +// *READ - Status* +// +// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC +// (Stays set till MAC is reset). This is a fatal error +// - 1 = tx_unfout - Sets if TX underflow reported by CMAC +// (Stays set till MAC is reset). This is a fatal error +// - 2 = stat_rx_aligned - goes high when CMAC has finished +// alignment, and is ready to start reception of traffic. +// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID) +// but upstream is trying to hold(TREADY)off we drop a packet. +// Upstream circuitry should detect this when traffic is forked +// between CHDR and CPU, so this bit will only set if there is a +// HW design error. +// - 4 = auto_config_done - This bit goes high when the auto_config +// state machine finishes operation. It is very similiar to +// stat_rx_alligned, but waits for extra writes which occur +// after allignement to complete. +// - 24:16 = pause_mask - readable version of pause_mask bellow. +// +// *WRITE - Ctl* +// +// - 0 = auto_enable - Defaults to ON after reset - Enables a +// state machine that performs CMAC register writes to +// bring up the MAC without SW intervention. +// - 24:16 = pause_mask - A second layer of enables(the first being +// register in the CMAC) on the pause_request mechanic. Bits +// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause +// request (not priority controlled). The mask is used for TX +// and RX. +// +// +// +// +// +// Definition of this register depends on Protocol +// +// **10GBE** +// +// *READ - Status * +// +// - 0 = core_status 0 - link_up +// - 1 = core_status 1 +// - 2 = core_status 2 +// - 3 = core_status 3 +// - 4 = core_status 4 +// - 5 = core_status 5 +// - 6 = core_status 6 +// - 7 = core_status 7 +// +// **100 GBE** +// +// *READ - Status* +// +// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets. +// - 1 = usr_rx_reset - RX PLL's have locked +// +// +// +// +// +// +// When set identify_value is used to control the activity LED. +// When clear the activity LED set on any TX or RX traffic to the mgt +// +// +// +// +// When identify_enable is set, this value controls the activity LED. +// +// +// +// +// +// The x4xx family of products does not use MDIO. +// +// +// +// +// Only valid if the protocol is Aurora. +// +// +// +// +// Only valid if the protocol is Aurora. +// +// +// +// +// Only valid if the protocol is Aurora. +// +// +// +// +// Only valid if the protocol is Aurora. +// +// +// +// +// +// +// +// +// UIO +// +// +// +// Set this port's IP address +// +// +// +// +// Set the UDP port for CHDR_traffic +// +// +// +// +// If BRIDGE_ENABLE is set use this MAC_ID +// +// +// +// +// If BRIDGE_ENABLE is set use this MAC_ID +// +// +// +// +// If BRIDGE_ENABLE is set use this IP Address +// +// +// +// +// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic +// +// +// +// +// Bit 0 Controls the following logic +// +//```verilog +// always_comb begin : bridge_mux +// my_mac = bridge_en ? bridge_mac_reg : mac_reg; +// my_ip = bridge_en ? bridge_ip_reg : ip_reg; +// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port; +// end +//``` +// +// +// +// +// +// Count the number of Packets dropped that were addressed to the CHDR section. +// +// +// +// +// Count the number of Packets dropped that were addressed to us, but not to the CHDR section. +// +// +// +// +// +// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only +// used with 100Gb ethernet +// +// +// +// +// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause. +// *Pause clear must be less than pause set or terrible things will happen.* +// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only +// used with 100Gb ethernet +// +// +// +// +// + +// +// +// +// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations +// +// - 1X10GB Ethernet - Using OpenCore XGE MAC +// - 1x100GB Ethernet - Using Xilinx CMAC +// - (future possible) - Xilinx Aurora (various rates and lane widths) +// - (future possible) - 4X10GB Ethernet +// +// +// +// +// +// +// +// + + +// +// +// +// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0 +// - 0_1 indicates QSFP0 - Lane1 +// - 0_2 indicates QSFP0 - Lane2 +// - 0_3 indicates QSFP0 - Lane3 +// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1 +// - 1_1 indicates QSFP1 - Lane1 +// - 1_2 indicates QSFP1 - Lane2 +// - 1_3 indicates QSFP1 - Lane3 +// +// +// +// +// +// +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc new file mode 100644 index 0000000..e400660 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc @@ -0,0 +1,52 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/, \ +x410_ps_rfdc_bd.tcl \ +) + +IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \ +capture_sysref.v \ +rf_nco_reset.vhd \ +rf_reset.vhd \ +sync_wrapper.v \ +axis_mux.vhd \ +gpio_to_axis_mux.vhd \ +) \ +$(addprefix $(BASE_DIR)/x400/rf/x410/, \ +x410_rf_reset_controller.vhd \ +x410_clock_gates.vhd \ +) \ +$(addprefix $(BASE_DIR)/../lib/control/, \ +synchronizer.v \ +synchronizer_impl.v \ +) \ +$(addprefix $(BASE_DIR)/x400/regmap/x410/, PkgRFDC_REGS_REGMAP.vhd ) + +IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \ +x410_ps_rfdc_bd.tcl \ +) + +IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \ +x410_ps_rfdc_bd/x410_ps_rfdc_bd.bd \ +) + +BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x410_ps_rfdc_bd/, \ +x410_ps_rfdc_bd.bd.out \ +x410_ps_rfdc_bd/x410_ps_rfdc_bd_ooc.xdc \ +x410_ps_rfdc_bd/synth/x410_ps_rfdc_bd.v \ +) + +EMPTY_IP_SRCS = + +.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT +$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT + @: + +IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,x410_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS)) diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/hdl_sources.tcl b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/hdl_sources.tcl new file mode 100644 index 0000000..e906a33 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/hdl_sources.tcl @@ -0,0 +1,14 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v +read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v +read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v +read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v +read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd +read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd +read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd +read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd +read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd +read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd +read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap/x410_rfdc_regs.v b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap/x410_rfdc_regs.v new file mode 100644 index 0000000..8b69957 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/regmap/x410_rfdc_regs.v @@ -0,0 +1,224 @@ +// +// Copyright 2022 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: x410_rfdc_regs +// Description: +// Registers definition within the x4xx_ps_rfdc_bd IP. + +//XmlParse xml_on +// +// +// +// This section lists all common Processing System ports through +// which the register maps in this project are accessed. Each input +// port to the fabric will point to a regmap. +// +// +// +// This is the main AXI4-Lite master interface that the PS +// exposes to the kernel to interact with the FPGA fabric. +// There are multiple endpoints connected to this interface. +// +// +// +// +// This is one of the two cache-coherent AXI slave ports available to +// communicate from the fabric (master) to the PS (slave). +// +// +// +// +// This is one of the two cache-coherent AXI slave ports available to +// communicate from the fabric (master) to the PS (slave). +// +// +// +// +// This is the SPI1 interface +// (see Zynq UltraScale+ Devices Register Reference) +// of the PS. +// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br} +// The request format on SPI is defined as.{br} +// {b}Write request:{/b} +// {ul} +// {li}1'b1 = write +// {li}15 bit address +// {li}32 bit data (MOSI) +// {li}8 bit processing gap +// {li}5 bit padding +// {li}1 bit ack +// {li}2 bit status +// {/ul} +// {b}Read request:{/b} +// {ul} +// {li}1'b0 = read +// {li}15 bit address +// {li}8 bit processing gap +// {li}32 bit data (MISO) +// {li}5 bit padding +// {li}1 bit ack +// {li}2 bit status +// {/ul} +// +// +// +// +// +// +// +// +// +// +// +// +// These are the registers located within the RFDC block design +// that provide control and status support for the RF chain. +// +// +// +// +// Register space for controlling the data clock MMCM instance +// within the RFDC block design. +// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the +// regiter space description in chapter 2. +// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf) +// +// +// +// +// Control register for inverting I/Q data. +// +// +// +// +// +// +// +// +// +// +// +// Control register for inverting I/Q data. +// +// +// +// +// +// +// +// +// +// +// +// Control register for resetting the data clock MMCM. +// +// +// Write a '1' to this bit to reset the MMCM. Then write a +// '0' to place the MMCM out of reset. +// +// +// +// +// +// +// +// +// +// +// +// The fields of this register provide data to all the DAC channels when enabled +// by the CALIBRATION_ENABLE register. +// +// +// +// +// +// +// +// +// +// This register enables calibration data in the DAC data path for each of the +// four channels. Each of these bits is normally '0'. When written '1', DAC data +// for the corresponding channel will be constantly driven with the contents of +// the CALIBRATION_DATA register. +// +// +// +// Enables calibration data for channel 0. +// +// +// +// +// Enables calibration data for channel 1. +// +// +// +// +// Enables calibration data for channel 2. +// +// +// +// +// Enables calibration data for channel 3. +// +// +// +// +// +// +// Enable RF MMCM outputs. +// +// +// +// +// +// +// +// +// +// +// Data Clk Pll Status Register +// +// +// +// +// +// +// +// This register shows threshold status for the ADCs. Each bit reflects the +// RFDC's real-time ADC status signals, which will assert when the ADC input +// signal exceeds the programmed threshold value. The status will remain +// asserted until cleared by software. +// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is +// the location of the tile in the converter column and ZZ is either 01 (the +// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). +// See also the Xilinx document PG269. +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/synthstub/x410_ps_rfdc_bd.vhd b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/synthstub/x410_ps_rfdc_bd.vhd new file mode 100644 index 0000000..adc1805 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/synthstub/x410_ps_rfdc_bd.vhd @@ -0,0 +1,411 @@ +------------------------------------------------------------------------------------------ +-- +-- File: x410_ps_rfdc_bd.vhd +-- Author: niBlockDesign::niBdExportStub +-- Original Project: HwBuildTools +-- Date: 27 September 2021 +-- +------------------------------------------------------------------------------------------ +-- (c) Copyright National Instruments Corporation +-- All Rights Reserved +-- National Instruments Internal Information +------------------------------------------------------------------------------------------ +-- +-- Purpose: This is an automatically generated stub file to match the entity +-- declaration for 'x410_ps_rfdc_bd'. This file was created using niBdExportStub +-- Do not modify this file directly! +-- +------------------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library unisim; +use unisim.vcomponents.all; + +entity x410_ps_rfdc_bd is +port ( + adc_data_out_resetn_dclk : out STD_LOGIC; + adc_enable_data_rclk : out STD_LOGIC; + adc_reset_pulse_dclk : in STD_LOGIC; + adc_rfdc_axi_resetn_rclk : out STD_LOGIC; + bus_clk : in STD_LOGIC; + bus_rstn : in STD_LOGIC; + clk40 : in STD_LOGIC; + clk40_rstn : in STD_LOGIC; + dac_data_in_resetn_dclk : out STD_LOGIC; + dac_data_in_resetn_dclk2x : out STD_LOGIC; + dac_data_in_resetn_rclk : out STD_LOGIC; + dac_data_in_resetn_rclk2x : out STD_LOGIC; + dac_reset_pulse_dclk : in STD_LOGIC; + data_clk : out STD_LOGIC; + data_clk_2x : out STD_LOGIC; + data_clock_locked : out STD_LOGIC; + enable_gated_clocks_clk40 : in STD_LOGIC; + enable_sysref_rclk : in STD_LOGIC; + fir_resetn_rclk2x : out STD_LOGIC; + gated_base_clks_valid_clk40 : out STD_LOGIC; + invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + irq0_lpd_rpu_n : in STD_LOGIC; + irq1_lpd_rpu_n : in STD_LOGIC; + jtag0_tck : inout STD_LOGIC; + jtag0_tdi : inout STD_LOGIC; + jtag0_tdo : in STD_LOGIC; + jtag0_tms : inout STD_LOGIC; + nco_reset_done_dclk : out STD_LOGIC; + pl_clk40 : out STD_LOGIC; + pl_clk100 : out STD_LOGIC; + pl_clk166 : out STD_LOGIC; + pl_clk200 : out STD_LOGIC; + pl_ps_irq0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + pl_ps_irq1 : in STD_LOGIC_VECTOR ( 5 downto 0 ); + pl_resetn0 : out STD_LOGIC; + pl_resetn1 : out STD_LOGIC; + pl_resetn2 : out STD_LOGIC; + pl_resetn3 : out STD_LOGIC; + pll_ref_clk_in : in STD_LOGIC; + pll_ref_clk_out : out STD_LOGIC; + rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 ); + rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 ); + rfdc_irq : out STD_LOGIC; + s_axi_hp0_aclk : in STD_LOGIC; + s_axi_hp1_aclk : in STD_LOGIC; + s_axi_hpc0_aclk : in STD_LOGIC; + start_nco_reset_dclk : in STD_LOGIC; + sysref_out_pclk : out STD_LOGIC; + sysref_out_rclk : out STD_LOGIC; + sysref_pl_in : in STD_LOGIC; + s_axi_hp0_aruser : in STD_LOGIC; + s_axi_hp0_awuser : in STD_LOGIC; + s_axi_hp0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_awlock : in STD_LOGIC; + s_axi_hp0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awvalid : in STD_LOGIC; + s_axi_hp0_awready : out STD_LOGIC; + s_axi_hp0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hp0_wlast : in STD_LOGIC; + s_axi_hp0_wvalid : in STD_LOGIC; + s_axi_hp0_wready : out STD_LOGIC; + s_axi_hp0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_bvalid : out STD_LOGIC; + s_axi_hp0_bready : in STD_LOGIC; + s_axi_hp0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_arlock : in STD_LOGIC; + s_axi_hp0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_arvalid : in STD_LOGIC; + s_axi_hp0_arready : out STD_LOGIC; + s_axi_hp0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_rlast : out STD_LOGIC; + s_axi_hp0_rvalid : out STD_LOGIC; + s_axi_hp0_rready : in STD_LOGIC; + s_axi_hp0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axis_eth_dma_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axis_eth_dma_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axis_eth_dma_tlast : in STD_LOGIC; + s_axis_eth_dma_tready : out STD_LOGIC; + s_axis_eth_dma_tvalid : in STD_LOGIC; + s_axi_hp1_aruser : in STD_LOGIC; + s_axi_hp1_awuser : in STD_LOGIC; + s_axi_hp1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_awlock : in STD_LOGIC; + s_axi_hp1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_awvalid : in STD_LOGIC; + s_axi_hp1_awready : out STD_LOGIC; + s_axi_hp1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hp1_wlast : in STD_LOGIC; + s_axi_hp1_wvalid : in STD_LOGIC; + s_axi_hp1_wready : out STD_LOGIC; + s_axi_hp1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_bvalid : out STD_LOGIC; + s_axi_hp1_bready : in STD_LOGIC; + s_axi_hp1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hp1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_arlock : in STD_LOGIC; + s_axi_hp1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp1_arvalid : in STD_LOGIC; + s_axi_hp1_arready : out STD_LOGIC; + s_axi_hp1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hp1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp1_rlast : out STD_LOGIC; + s_axi_hp1_rvalid : out STD_LOGIC; + s_axi_hp1_rready : in STD_LOGIC; + s_axi_hp1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_aruser : in STD_LOGIC; + s_axi_hpc0_awuser : in STD_LOGIC; + s_axi_hpc0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc0_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_awlock : in STD_LOGIC; + s_axi_hpc0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_awvalid : in STD_LOGIC; + s_axi_hpc0_awready : out STD_LOGIC; + s_axi_hpc0_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc0_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hpc0_wlast : in STD_LOGIC; + s_axi_hpc0_wvalid : in STD_LOGIC; + s_axi_hpc0_wready : out STD_LOGIC; + s_axi_hpc0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_bvalid : out STD_LOGIC; + s_axi_hpc0_bready : in STD_LOGIC; + s_axi_hpc0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc0_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_arlock : in STD_LOGIC; + s_axi_hpc0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc0_arvalid : in STD_LOGIC; + s_axi_hpc0_arready : out STD_LOGIC; + s_axi_hpc0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc0_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc0_rlast : out STD_LOGIC; + s_axi_hpc0_rvalid : out STD_LOGIC; + s_axi_hpc0_rready : in STD_LOGIC; + s_axi_hpc0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + adc0_clk_clk_n : in STD_LOGIC; + adc0_clk_clk_p : in STD_LOGIC; + adc2_clk_clk_n : in STD_LOGIC; + adc2_clk_clk_p : in STD_LOGIC; + m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_app_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_app_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_app_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_app_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_app_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_app_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_app_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_app_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + dac0_clk_clk_n : in STD_LOGIC; + dac0_clk_clk_p : in STD_LOGIC; + dac1_clk_clk_n : in STD_LOGIC; + dac1_clk_clk_p : in STD_LOGIC; + gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 ); + gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); + gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axi_eth_internal_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_eth_internal_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_eth_internal_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_eth_internal_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_eth_internal_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_eth_internal_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_eth_internal_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_eth_internal_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_eth_internal_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_eth_internal_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_eth_internal_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axis_eth_dma_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + m_axis_eth_dma_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axis_eth_dma_tlast : out STD_LOGIC; + m_axis_eth_dma_tready : in STD_LOGIC; + m_axis_eth_dma_tvalid : out STD_LOGIC; + m_axi_rpu_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_rpu_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rpu_awvalid : out STD_LOGIC; + m_axi_rpu_awready : in STD_LOGIC; + m_axi_rpu_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rpu_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_rpu_wvalid : out STD_LOGIC; + m_axi_rpu_wready : in STD_LOGIC; + m_axi_rpu_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rpu_bvalid : in STD_LOGIC; + m_axi_rpu_bready : out STD_LOGIC; + m_axi_rpu_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_rpu_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_rpu_arvalid : out STD_LOGIC; + m_axi_rpu_arready : in STD_LOGIC; + m_axi_rpu_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_rpu_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_rpu_rvalid : in STD_LOGIC; + m_axi_rpu_rready : out STD_LOGIC; + m_axi_core_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_core_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_core_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_core_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_core_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_core_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_core_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_core_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_core_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_core_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_core_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_mpm_ep_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_mpm_ep_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_awready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mpm_ep_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_mpm_ep_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_wready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_mpm_ep_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_bready : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_araddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); + m_axi_mpm_ep_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_mpm_ep_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch0_dout_i_tready : in STD_LOGIC; + adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC; + adc_tile224_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch0_dout_q_tready : in STD_LOGIC; + adc_tile224_ch0_dout_q_tvalid : out STD_LOGIC; + adc_tile224_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch1_dout_i_tready : in STD_LOGIC; + adc_tile224_ch1_dout_i_tvalid : out STD_LOGIC; + adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile224_ch1_dout_q_tready : in STD_LOGIC; + adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC; + adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch0_dout_i_tready : in STD_LOGIC; + adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC; + adc_tile226_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch0_dout_q_tready : in STD_LOGIC; + adc_tile226_ch0_dout_q_tvalid : out STD_LOGIC; + adc_tile226_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch1_dout_i_tready : in STD_LOGIC; + adc_tile226_ch1_dout_i_tvalid : out STD_LOGIC; + adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile226_ch1_dout_q_tready : in STD_LOGIC; + adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC; + dac_tile228_ch0_vout_v_n : out STD_LOGIC; + dac_tile228_ch0_vout_v_p : out STD_LOGIC; + dac_tile228_ch1_vout_v_n : out STD_LOGIC; + dac_tile228_ch1_vout_v_p : out STD_LOGIC; + dac_tile229_ch0_vout_v_n : out STD_LOGIC; + dac_tile229_ch0_vout_v_p : out STD_LOGIC; + dac_tile229_ch1_vout_v_n : out STD_LOGIC; + dac_tile229_ch1_vout_v_p : out STD_LOGIC; + dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile228_ch0_din_tvalid : in STD_LOGIC; + dac_tile228_ch0_din_tready : out STD_LOGIC; + dac_tile228_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile228_ch1_din_tvalid : in STD_LOGIC; + dac_tile228_ch1_din_tready : out STD_LOGIC; + dac_tile229_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile229_ch0_din_tvalid : in STD_LOGIC; + dac_tile229_ch0_din_tready : out STD_LOGIC; + dac_tile229_ch1_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile229_ch1_din_tvalid : in STD_LOGIC; + dac_tile229_ch1_din_tready : out STD_LOGIC; + s_axi_hpc1_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_awaddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc1_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc1_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_awlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc1_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axi_hpc1_wlast : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_araddr : in STD_LOGIC_VECTOR ( 48 downto 0 ); + s_axi_hpc1_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hpc1_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_arlock : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hpc1_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hpc1_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hpc1_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + s_axi_hpc1_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hpc1_rlast : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); + sysref_rf_in_diff_n : in STD_LOGIC; + sysref_rf_in_diff_p : in STD_LOGIC; + adc_tile224_ch0_vin_v_n : in STD_LOGIC; + adc_tile224_ch0_vin_v_p : in STD_LOGIC; + adc_tile224_ch1_vin_v_n : in STD_LOGIC; + adc_tile224_ch1_vin_v_p : in STD_LOGIC; + adc_tile226_ch0_vin_v_n : in STD_LOGIC; + adc_tile226_ch0_vin_v_p : in STD_LOGIC; + adc_tile226_ch1_vin_v_n : in STD_LOGIC; + adc_tile226_ch1_vin_v_p : in STD_LOGIC; + s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); + s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + end entity x410_ps_rfdc_bd; + +architecture stub of x410_ps_rfdc_bd is +begin +end architecture stub; diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl new file mode 100644 index 0000000..34cb12c --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl @@ -0,0 +1,3825 @@ + +################################################################ +# This is a generated script based on design: x410_ps_rfdc_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2021.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source x410_ps_rfdc_bd_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# capture_sysref, x410_clock_gates, rf_nco_reset, x410_rf_reset_controller, x410_rf_reset_controller, gpio_to_axis_mux + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name x410_ps_rfdc_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + + # Add USER_COMMENTS on $design_name + set_property USER_COMMENTS.comment_2 "reg_reset_mmcm: +[0] = mmcm_reset_n (default b0)" [get_bd_designs $design_name] + set_property USER_COMMENTS.comment_3 "reg_invert_iq: +[15:8] = invert DAC channels +[7:0] = invert ADC channels" [get_bd_designs $design_name] + set_property USER_COMMENTS.comment_4 "The ADC/DAC mappings need to match the RFDC settings, +but there's no clear way to pull them out of the RFDC configuration +above. This means that the values in these constants need to be +manually matched to the RFDC configuration object. + +The format of the ADC/DAC maps is documented in gen_x4xx_rfdc_regmap.py." [get_bd_designs $design_name] + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +ettus.com:ip:axi_bitq:1.0\ +xilinx.com:ip:zynq_ultra_ps_e:3.3\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:usp_rf_data_converter:2.5\ +xilinx.com:ip:xlslice:1.0\ +xilinx.com:ip:axi_protocol_converter:2.1\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:util_ds_buf:2.2\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +capture_sysref\ +x410_clock_gates\ +rf_nco_reset\ +x410_rf_reset_controller\ +x410_rf_reset_controller\ +gpio_to_axis_mux\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: rf_clock_buffers +proc create_hier_cell_rf_clock_buffers { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + + # Create pins + create_bd_pin -dir O -from 0 -to 0 rfdc_clk + create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x + create_bd_pin -dir I -from 0 -to 0 rfdc_clk_2x_ce + create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_2x_pll + create_bd_pin -dir I -from 0 -to 0 rfdc_clk_ce + create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll + + # Create instance: rfdc_clk_1x_buf, and set properties + set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_1x_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {BUFGCE} \ + ] $rfdc_clk_1x_buf + + # Create instance: rfdc_clk_2x_buf, and set properties + set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_2x_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {BUFGCE} \ + ] $rfdc_clk_2x_buf + + # Create port connections + connect_bd_net -net BUFGCE_I2_1 [get_bd_pins rfdc_clk_2x_pll] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_I] + connect_bd_net -net rfdc_clk_1 [get_bd_pins rfdc_clk_pll] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_I] + connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rfdc_clk] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_O] + connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rfdc_clk_2x] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_O] + connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins rfdc_clk_2x_ce] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_CE] + connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins rfdc_clk_ce] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_CE] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: calibration_muxes +proc create_hier_cell_calibration_muxes { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_1_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_2_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_3_0 + + + # Create pins + create_bd_pin -dir I -type clk s_axi_aclk_0 + create_bd_pin -dir I -type rst s_axi_config_aresetn + create_bd_pin -dir I -type clk s_axi_config_clk + + # Create instance: axi_gpio_data, and set properties + set axi_gpio_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_data ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_ALL_OUTPUTS_2 {1} \ + CONFIG.C_GPIO2_WIDTH {8} \ + CONFIG.C_IS_DUAL {1} \ + ] $axi_gpio_data + + # Create instance: constant0_1b, and set properties + set constant0_1b [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant0_1b ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $constant0_1b + + # Create instance: gpio_to_axis_mux_0, and set properties + set block_name gpio_to_axis_mux + set block_cell_name gpio_to_axis_mux_0 + if { [catch {set gpio_to_axis_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $gpio_to_axis_mux_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + set_property -dict [ list \ + CONFIG.kGpioWidth {32} \ + ] $gpio_to_axis_mux_0 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {256} \ + ] $xlconstant_1 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axis_0_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axis_1_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_1] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dac_tile228_ch0_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_0] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dac_tile228_ch1_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_1] + connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins S_AXI_1] [get_bd_intf_pins axi_gpio_data/S_AXI] + connect_bd_intf_net -intf_net dac_tile229_ch0_din_1 [get_bd_intf_pins dac_tile229_ch0_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_4] + connect_bd_intf_net -intf_net dac_tile229_ch1_din_1 [get_bd_intf_pins dac_tile229_ch1_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_5] + connect_bd_intf_net -intf_net gpio_to_axis_mux_0_m_axis_4 [get_bd_intf_pins m_axis_2_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_4] + connect_bd_intf_net -intf_net gpio_to_axis_mux_0_m_axis_5 [get_bd_intf_pins m_axis_3_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_5] + + # Create port connections + connect_bd_net -net Net [get_bd_pins s_axi_config_clk] [get_bd_pins axi_gpio_data/s_axi_aclk] + connect_bd_net -net Net1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins axi_gpio_data/s_axi_aresetn] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_data/gpio_io_o] [get_bd_pins gpio_to_axis_mux_0/gpio] + connect_bd_net -net axi_gpio_data_gpio2_io_o [get_bd_pins axi_gpio_data/gpio2_io_o] [get_bd_pins gpio_to_axis_mux_0/mux_select] + connect_bd_net -net constant0_1b_dout [get_bd_pins constant0_1b/dout] [get_bd_pins gpio_to_axis_mux_0/s_axis_tvalid_2] [get_bd_pins gpio_to_axis_mux_0/s_axis_tvalid_3] [get_bd_pins gpio_to_axis_mux_0/s_axis_tvalid_6] [get_bd_pins gpio_to_axis_mux_0/s_axis_tvalid_7] + connect_bd_net -net s_axi_aclk_0_1 [get_bd_pins s_axi_aclk_0] [get_bd_pins gpio_to_axis_mux_0/m_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_3_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_4_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_5_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_6_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_7_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_3_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_4_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_5_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_6_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_7_aclk] + connect_bd_net -net xlconstant_1_dout [get_bd_pins gpio_to_axis_mux_0/s_axis_tdata_2] [get_bd_pins gpio_to_axis_mux_0/s_axis_tdata_3] [get_bd_pins gpio_to_axis_mux_0/s_axis_tdata_6] [get_bd_pins gpio_to_axis_mux_0/s_axis_tdata_7] [get_bd_pins xlconstant_1/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: ThresholdRegister +proc create_hier_cell_ThresholdRegister { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + + # Create pins + create_bd_pin -dir I -from 0 -to 0 In0 + create_bd_pin -dir I -from 0 -to 0 In1 + create_bd_pin -dir I -from 0 -to 0 In2 + create_bd_pin -dir I -from 0 -to 0 In3 + create_bd_pin -dir I -from 0 -to 0 In5 + create_bd_pin -dir I -from 0 -to 0 In6 + create_bd_pin -dir I -from 0 -to 0 In7 + create_bd_pin -dir I -from 0 -to 0 In8 + create_bd_pin -dir I -type rst s_axi_config_aresetn + create_bd_pin -dir I -type clk s_axi_config_clk + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + CONFIG.C_GPIO_WIDTH {12} \ + ] $axi_gpio_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_WIDTH {4} \ + ] $xlconstant_0 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] + + # Create port connections + connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net In2_1 [get_bd_pins In2] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net In3_1 [get_bd_pins In3] [get_bd_pins xlconcat_0/In3] + connect_bd_net -net In5_1 [get_bd_pins In5] [get_bd_pins xlconcat_0/In5] + connect_bd_net -net In6_1 [get_bd_pins In6] [get_bd_pins xlconcat_0/In6] + connect_bd_net -net In7_1 [get_bd_pins In7] [get_bd_pins xlconcat_0/In7] + connect_bd_net -net In8_1 [get_bd_pins In8] [get_bd_pins xlconcat_0/In8] + connect_bd_net -net s_axi_config_aresetn_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] + connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] + connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_gpio_0/gpio_io_i] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In4] [get_bd_pins xlconstant_0/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: eth_dma_internal +proc create_hier_cell_eth_dma_internal { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_to_ps + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_eth_dma + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth_dma_ctrl + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_eth_dma + + + # Create pins + create_bd_pin -dir I -type clk bus_clk + create_bd_pin -dir I -type rst bus_rstn + create_bd_pin -dir I -type clk clk40 + create_bd_pin -dir I -type rst clk40_rstn + create_bd_pin -dir O -from 1 -to 0 irq + + # Create instance: axi_eth_dma_internal, and set properties + set axi_eth_dma_internal [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_eth_dma_internal ] + set_property -dict [ list \ + CONFIG.c_addr_width {36} \ + CONFIG.c_enable_multi_channel {0} \ + CONFIG.c_include_mm2s_dre {1} \ + CONFIG.c_include_s2mm {1} \ + CONFIG.c_include_s2mm_dre {1} \ + CONFIG.c_m_axi_mm2s_data_width {128} \ + CONFIG.c_m_axi_s2mm_data_width {128} \ + CONFIG.c_m_axis_mm2s_tdata_width {64} \ + CONFIG.c_micro_dma {0} \ + CONFIG.c_mm2s_burst_size {16} \ + CONFIG.c_s2mm_burst_size {16} \ + CONFIG.c_sg_include_stscntrl_strm {0} \ + ] $axi_eth_dma_internal + + # Create instance: pl_ps_irq1_concat, and set properties + set pl_ps_irq1_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pl_ps_irq1_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {2} \ + ] $pl_ps_irq1_concat + + # Create instance: smartconnect_dma, and set properties + set smartconnect_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_dma ] + set_property -dict [ list \ + CONFIG.NUM_SI {3} \ + ] $smartconnect_dma + + # Create interface connections + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_eth_dma] [get_bd_intf_pins axi_eth_dma_internal/M_AXIS_MM2S] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axis_eth_dma] [get_bd_intf_pins axi_eth_dma_internal/S_AXIS_S2MM] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_MM2S [get_bd_intf_pins axi_eth_dma_internal/M_AXI_MM2S] [get_bd_intf_pins smartconnect_dma/S01_AXI] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_S2MM [get_bd_intf_pins axi_eth_dma_internal/M_AXI_S2MM] [get_bd_intf_pins smartconnect_dma/S02_AXI] + connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_SG [get_bd_intf_pins axi_eth_dma_internal/M_AXI_SG] [get_bd_intf_pins smartconnect_dma/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_eth_dma_ctrl [get_bd_intf_pins s_axi_eth_dma_ctrl] [get_bd_intf_pins axi_eth_dma_internal/S_AXI_LITE] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins m_axi_to_ps] [get_bd_intf_pins smartconnect_dma/M00_AXI] + + # Create port connections + connect_bd_net -net axi_eth_dma_internal_mm2s_introut [get_bd_pins axi_eth_dma_internal/mm2s_introut] [get_bd_pins pl_ps_irq1_concat/In0] + connect_bd_net -net axi_eth_dma_internal_s2mm_introut [get_bd_pins axi_eth_dma_internal/s2mm_introut] [get_bd_pins pl_ps_irq1_concat/In1] + connect_bd_net -net bus_rstn_1 [get_bd_pins bus_rstn] [get_bd_pins smartconnect_dma/aresetn] + connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_eth_dma_internal/s_axi_lite_aclk] + connect_bd_net -net clk40_rstn_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_eth_dma_internal/axi_resetn] + connect_bd_net -net m_axi_sg_aclk_0_1 [get_bd_pins bus_clk] [get_bd_pins axi_eth_dma_internal/m_axi_mm2s_aclk] [get_bd_pins axi_eth_dma_internal/m_axi_s2mm_aclk] [get_bd_pins axi_eth_dma_internal/m_axi_sg_aclk] [get_bd_pins smartconnect_dma/aclk] + connect_bd_net -net xlconcat_0_dout [get_bd_pins irq] [get_bd_pins pl_ps_irq1_concat/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: axi_interconnect_common +proc create_hier_cell_axi_interconnect_common { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_app + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_core + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_dma_ctrl + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_jtag + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mpm_ep + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rf + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rpu + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_common + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_lpd + + + # Create pins + create_bd_pin -dir I -type clk clk40 + create_bd_pin -dir I -type rst clk40_rstn + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {7} \ + ] $axi_interconnect_0 + + # Create instance: axi_protocol_convert_0, and set properties + set axi_protocol_convert_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_jtag] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins m_axi_app] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins m_axi_rf] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins m_axi_mpm_ep] [get_bd_intf_pins axi_interconnect_0/M03_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins m_axi_core] [get_bd_intf_pins axi_interconnect_0/M04_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins m_axi_eth_dma_ctrl] [get_bd_intf_pins axi_interconnect_0/M05_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_pins m_axi_eth_internal] [get_bd_intf_pins axi_interconnect_0/M06_AXI] + connect_bd_intf_net -intf_net axi_protocol_convert_0_M_AXI [get_bd_intf_pins m_axi_rpu] [get_bd_intf_pins axi_protocol_convert_0/M_AXI] + connect_bd_intf_net -intf_net inst_zynq_ps_M_AXI_HPM0_FPD [get_bd_intf_pins s_axi_common] [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net s_axi_lpd_1 [get_bd_intf_pins s_axi_lpd] [get_bd_intf_pins axi_protocol_convert_0/S_AXI] + + # Create port connections + connect_bd_net -net M01_ARESETN_1 [get_bd_pins clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_protocol_convert_0/aresetn] + connect_bd_net -net clk40_1 [get_bd_pins clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_protocol_convert_0/aclk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rfdc +proc create_hier_cell_rfdc { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch0_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch0_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch0_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch1_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch0_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch1_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_config + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_rf_in + + + # Create pins + create_bd_pin -dir O adc_data_out_resetn_dclk + create_bd_pin -dir O adc_enable_data_rclk + create_bd_pin -dir I adc_reset_pulse_dclk + create_bd_pin -dir O adc_rfdc_axi_resetn_rclk + create_bd_pin -dir O dac_data_in_resetn_dclk + create_bd_pin -dir O dac_data_in_resetn_dclk2x + create_bd_pin -dir O dac_data_in_resetn_rclk + create_bd_pin -dir O dac_data_in_resetn_rclk2x + create_bd_pin -dir I dac_reset_pulse_dclk + create_bd_pin -dir O -type clk data_clk + create_bd_pin -dir O -type clk data_clk_2x + create_bd_pin -dir O data_clock_locked + create_bd_pin -dir I enable_gated_clocks_clk40 + create_bd_pin -dir I enable_sysref_rclk + create_bd_pin -dir O fir_resetn_rclk2x + create_bd_pin -dir O gated_base_clks_valid_clk40 + create_bd_pin -dir O nco_reset_done_dclk + create_bd_pin -dir I -type clk pll_ref_clk_in + create_bd_pin -dir O -type clk pll_ref_clk_out + create_bd_pin -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk + create_bd_pin -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk + create_bd_pin -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk + create_bd_pin -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk + create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk + create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk + create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk + create_bd_pin -dir O -from 0 -to 0 rfdc_clk + create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x + create_bd_pin -dir O -type intr rfdc_irq + create_bd_pin -dir I -type rst s_axi_config_aresetn + create_bd_pin -dir I -type clk s_axi_config_clk + create_bd_pin -dir I start_nco_reset_dclk + create_bd_pin -dir O sysref_out_pclk + create_bd_pin -dir O sysref_out_rclk + create_bd_pin -dir I sysref_pl_in + + # Create instance: ThresholdRegister + create_hier_cell_ThresholdRegister $hier_obj ThresholdRegister + + # Create instance: axi_interconnect_rf, and set properties + set axi_interconnect_rf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_rf ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ + CONFIG.NUM_MI {13} \ + CONFIG.STRATEGY {1} \ + ] $axi_interconnect_rf + + # Create instance: calibration_muxes + create_hier_cell_calibration_muxes $hier_obj calibration_muxes + + # Create instance: capture_sysref, and set properties + set block_name capture_sysref + set block_cell_name capture_sysref + if { [catch {set capture_sysref [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $capture_sysref eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + set_property -dict [ list \ + CONFIG.FREQ_HZ {61440000} \ + CONFIG.PHASE {0} \ + CONFIG.CLK_DOMAIN {x410_ps_rfdc_bd_pll_ref_clk_in} \ + ] [get_bd_pins /rfdc/capture_sysref/pll_ref_clk] + + set_property -dict [ list \ + CONFIG.FREQ_HZ {184320000} \ + CONFIG.PHASE {0} \ + CONFIG.CLK_DOMAIN {x410_ps_rfdc_bd_pll_ref_clk_in} \ + ] [get_bd_pins /rfdc/capture_sysref/rfdc_clk] + + # Create instance: clock_gates_0, and set properties + set block_name x410_clock_gates + set block_cell_name clock_gates_0 + if { [catch {set clock_gates_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $clock_gates_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: const_1, and set properties + set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] + + # Create instance: data_clock_mmcm, and set properties + set data_clock_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 data_clock_mmcm ] + set_property -dict [ list \ + CONFIG.AXI_DRP {true} \ + CONFIG.CLKIN1_JITTER_PS {162.76} \ + CONFIG.CLKOUT1_DRIVES {Buffer} \ + CONFIG.CLKOUT1_JITTER {116.960} \ + CONFIG.CLKOUT1_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {61.44} \ + CONFIG.CLKOUT2_DRIVES {Buffer} \ + CONFIG.CLKOUT2_JITTER {104.559} \ + CONFIG.CLKOUT2_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {122.88} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_DRIVES {Buffer} \ + CONFIG.CLKOUT3_JITTER {98.017} \ + CONFIG.CLKOUT3_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {184.32} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_DRIVES {Buffer} \ + CONFIG.CLKOUT4_JITTER {93.671} \ + CONFIG.CLKOUT4_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {245.76} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT5_DRIVES {Buffer} \ + CONFIG.CLKOUT5_JITTER {87.938} \ + CONFIG.CLKOUT5_PHASE_ERROR {124.626} \ + CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {368.64} \ + CONFIG.CLKOUT5_USED {true} \ + CONFIG.CLKOUT6_DRIVES {Buffer} \ + CONFIG.CLKOUT7_DRIVES {Buffer} \ + CONFIG.CLK_OUT1_PORT {pll_ref_clk_out} \ + CONFIG.CLK_OUT2_PORT {data_clk} \ + CONFIG.CLK_OUT3_PORT {rfdc_clk} \ + CONFIG.CLK_OUT4_PORT {data_clk_2x} \ + CONFIG.CLK_OUT5_PORT {rfdc_clk_2x} \ + CONFIG.ENABLE_CLOCK_MONITOR {false} \ + CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {16.276} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {12} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {8} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {6} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {4} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {5} \ + CONFIG.PHASE_DUTY_CONFIG {false} \ + CONFIG.PRIMITIVE {MMCM} \ + CONFIG.PRIM_IN_FREQ {61.44} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \ + CONFIG.USE_CLKFB_STOPPED {false} \ + CONFIG.USE_DYN_RECONFIG {true} \ + CONFIG.USE_INCLK_STOPPED {false} \ + CONFIG.USE_LOCKED {true} \ + CONFIG.USE_PHASE_ALIGNMENT {true} \ + CONFIG.USE_POWER_DOWN {false} \ + CONFIG.USE_RESET {true} \ + CONFIG.USE_SAFE_CLOCK_STARTUP {false} \ + ] $data_clock_mmcm + + # Create instance: reg_clock_gate_control, and set properties + set reg_clock_gate_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_clock_gate_control ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_clock_gate_control + + # Create instance: reg_invert_iq_radio0, and set properties + set reg_invert_iq_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_invert_iq_radio0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + ] $reg_invert_iq_radio0 + + # Create instance: reg_invert_iq_radio1, and set properties + set reg_invert_iq_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_invert_iq_radio1 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + ] $reg_invert_iq_radio1 + + # Create instance: reg_reset_mmcm, and set properties + set reg_reset_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_reset_mmcm ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + ] $reg_reset_mmcm + + # Create instance: reg_rf_axi_status, and set properties + set reg_rf_axi_status [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_axi_status ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {0} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rf_axi_status + + # Create instance: reg_rf_reset_control_radio0, and set properties + set reg_rf_reset_control_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_reset_control_radio0 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rf_reset_control_radio0 + + # Create instance: reg_rf_reset_control_radio1, and set properties + set reg_rf_reset_control_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_reset_control_radio1 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rf_reset_control_radio1 + + # Create instance: reg_rfdc_info, and set properties + set reg_rfdc_info [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rfdc_info ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + ] $reg_rfdc_info + + # Create instance: reg_rfdc_tile_mapping, and set properties + set reg_rfdc_tile_mapping [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rfdc_tile_mapping ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rfdc_tile_mapping + + # Create instance: rf_clock_buffers + create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers + + # Create instance: rf_data_converter, and set properties + set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ] + set_property -dict [ list \ + CONFIG.ADC0_Enable {1} \ + CONFIG.ADC0_Fabric_Freq {184.320} \ + CONFIG.ADC0_Multi_Tile_Sync {true} \ + CONFIG.ADC0_Outclk_Freq {184.320} \ + CONFIG.ADC0_Refclk_Freq {2949.120} \ + CONFIG.ADC0_Sampling_Rate {2.94912} \ + CONFIG.ADC1_Enable {0} \ + CONFIG.ADC1_Fabric_Freq {0.0} \ + CONFIG.ADC1_Multi_Tile_Sync {false} \ + CONFIG.ADC1_Outclk_Freq {15.625} \ + CONFIG.ADC1_Refclk_Freq {2000.000} \ + CONFIG.ADC1_Sampling_Rate {2.0} \ + CONFIG.ADC224_En {true} \ + CONFIG.ADC225_En {false} \ + CONFIG.ADC2_Enable {1} \ + CONFIG.ADC2_Fabric_Freq {184.320} \ + CONFIG.ADC2_Multi_Tile_Sync {true} \ + CONFIG.ADC2_Outclk_Freq {184.320} \ + CONFIG.ADC2_Refclk_Freq {2949.120} \ + CONFIG.ADC2_Sampling_Rate {2.94912} \ + CONFIG.ADC_Data_Type00 {1} \ + CONFIG.ADC_Data_Type01 {1} \ + CONFIG.ADC_Data_Type02 {1} \ + CONFIG.ADC_Data_Type03 {1} \ + CONFIG.ADC_Data_Type10 {0} \ + CONFIG.ADC_Data_Type11 {0} \ + CONFIG.ADC_Data_Type12 {0} \ + CONFIG.ADC_Data_Type13 {0} \ + CONFIG.ADC_Data_Type20 {1} \ + CONFIG.ADC_Data_Type21 {1} \ + CONFIG.ADC_Data_Type22 {1} \ + CONFIG.ADC_Data_Type23 {1} \ + CONFIG.ADC_Data_Width00 {8} \ + CONFIG.ADC_Data_Width01 {8} \ + CONFIG.ADC_Data_Width02 {8} \ + CONFIG.ADC_Data_Width03 {8} \ + CONFIG.ADC_Data_Width10 {8} \ + CONFIG.ADC_Data_Width11 {8} \ + CONFIG.ADC_Data_Width12 {8} \ + CONFIG.ADC_Data_Width13 {8} \ + CONFIG.ADC_Data_Width20 {8} \ + CONFIG.ADC_Data_Width21 {8} \ + CONFIG.ADC_Data_Width22 {8} \ + CONFIG.ADC_Data_Width23 {8} \ + CONFIG.ADC_Debug {false} \ + CONFIG.ADC_Decimation_Mode00 {2} \ + CONFIG.ADC_Decimation_Mode01 {2} \ + CONFIG.ADC_Decimation_Mode02 {2} \ + CONFIG.ADC_Decimation_Mode03 {2} \ + CONFIG.ADC_Decimation_Mode10 {0} \ + CONFIG.ADC_Decimation_Mode11 {0} \ + CONFIG.ADC_Decimation_Mode12 {0} \ + CONFIG.ADC_Decimation_Mode13 {0} \ + CONFIG.ADC_Decimation_Mode20 {2} \ + CONFIG.ADC_Decimation_Mode21 {2} \ + CONFIG.ADC_Decimation_Mode22 {2} \ + CONFIG.ADC_Decimation_Mode23 {2} \ + CONFIG.ADC_Dither00 {false} \ + CONFIG.ADC_Dither01 {false} \ + CONFIG.ADC_Dither02 {false} \ + CONFIG.ADC_Dither03 {false} \ + CONFIG.ADC_Dither10 {true} \ + CONFIG.ADC_Dither11 {true} \ + CONFIG.ADC_Dither12 {true} \ + CONFIG.ADC_Dither13 {true} \ + CONFIG.ADC_Dither20 {false} \ + CONFIG.ADC_Dither21 {false} \ + CONFIG.ADC_Dither22 {false} \ + CONFIG.ADC_Dither23 {false} \ + CONFIG.ADC_Mixer_Mode00 {0} \ + CONFIG.ADC_Mixer_Mode01 {0} \ + CONFIG.ADC_Mixer_Mode02 {0} \ + CONFIG.ADC_Mixer_Mode03 {0} \ + CONFIG.ADC_Mixer_Mode10 {2} \ + CONFIG.ADC_Mixer_Mode11 {2} \ + CONFIG.ADC_Mixer_Mode12 {2} \ + CONFIG.ADC_Mixer_Mode13 {2} \ + CONFIG.ADC_Mixer_Mode20 {0} \ + CONFIG.ADC_Mixer_Mode21 {0} \ + CONFIG.ADC_Mixer_Mode22 {0} \ + CONFIG.ADC_Mixer_Mode23 {0} \ + CONFIG.ADC_Mixer_Type00 {2} \ + CONFIG.ADC_Mixer_Type01 {2} \ + CONFIG.ADC_Mixer_Type02 {2} \ + CONFIG.ADC_Mixer_Type03 {2} \ + CONFIG.ADC_Mixer_Type10 {3} \ + CONFIG.ADC_Mixer_Type11 {3} \ + CONFIG.ADC_Mixer_Type12 {3} \ + CONFIG.ADC_Mixer_Type13 {3} \ + CONFIG.ADC_Mixer_Type20 {2} \ + CONFIG.ADC_Mixer_Type21 {2} \ + CONFIG.ADC_Mixer_Type22 {2} \ + CONFIG.ADC_Mixer_Type23 {2} \ + CONFIG.ADC_NCO_Freq00 {0.200} \ + CONFIG.ADC_NCO_Freq01 {0.200} \ + CONFIG.ADC_NCO_Freq02 {0.200} \ + CONFIG.ADC_NCO_Freq03 {0.200} \ + CONFIG.ADC_NCO_Freq10 {0.0} \ + CONFIG.ADC_NCO_Freq11 {0.0} \ + CONFIG.ADC_NCO_Freq12 {0.0} \ + CONFIG.ADC_NCO_Freq13 {0.0} \ + CONFIG.ADC_NCO_Freq20 {0.200} \ + CONFIG.ADC_NCO_Freq21 {0.200} \ + CONFIG.ADC_NCO_Freq22 {0.200} \ + CONFIG.ADC_NCO_Freq23 {0.200} \ + CONFIG.ADC_NCO_Freq30 {0.0} \ + CONFIG.ADC_NCO_Freq31 {0.0} \ + CONFIG.ADC_NCO_RTS {true} \ + CONFIG.ADC_RTS {true} \ + CONFIG.ADC_Slice00_Enable {true} \ + CONFIG.ADC_Slice01_Enable {true} \ + CONFIG.ADC_Slice02_Enable {true} \ + CONFIG.ADC_Slice03_Enable {true} \ + CONFIG.ADC_Slice10_Enable {false} \ + CONFIG.ADC_Slice11_Enable {false} \ + CONFIG.ADC_Slice12_Enable {false} \ + CONFIG.ADC_Slice13_Enable {false} \ + CONFIG.ADC_Slice20_Enable {true} \ + CONFIG.ADC_Slice21_Enable {true} \ + CONFIG.ADC_Slice22_Enable {true} \ + CONFIG.ADC_Slice23_Enable {true} \ + CONFIG.Axiclk_Freq {40} \ + CONFIG.Calibration_Freeze {true} \ + CONFIG.Converter_Setup {1} \ + CONFIG.DAC0_Band {0} \ + CONFIG.DAC0_Enable {1} \ + CONFIG.DAC0_Fabric_Freq {184.320} \ + CONFIG.DAC0_Multi_Tile_Sync {true} \ + CONFIG.DAC0_Outclk_Freq {184.320} \ + CONFIG.DAC0_Refclk_Freq {2949.120} \ + CONFIG.DAC0_Sampling_Rate {2.94912} \ + CONFIG.DAC1_Enable {1} \ + CONFIG.DAC1_Fabric_Freq {184.320} \ + CONFIG.DAC1_Multi_Tile_Sync {true} \ + CONFIG.DAC1_Outclk_Freq {184.320} \ + CONFIG.DAC1_Refclk_Freq {2949.120} \ + CONFIG.DAC1_Sampling_Rate {2.94912} \ + CONFIG.DAC228_En {true} \ + CONFIG.DAC_Data_Type00 {0} \ + CONFIG.DAC_Data_Type01 {0} \ + CONFIG.DAC_Data_Width00 {16} \ + CONFIG.DAC_Data_Width01 {16} \ + CONFIG.DAC_Data_Width02 {16} \ + CONFIG.DAC_Data_Width03 {16} \ + CONFIG.DAC_Data_Width10 {16} \ + CONFIG.DAC_Data_Width11 {16} \ + CONFIG.DAC_Debug {false} \ + CONFIG.DAC_Interpolation_Mode00 {2} \ + CONFIG.DAC_Interpolation_Mode01 {2} \ + CONFIG.DAC_Interpolation_Mode02 {0} \ + CONFIG.DAC_Interpolation_Mode03 {0} \ + CONFIG.DAC_Interpolation_Mode10 {2} \ + CONFIG.DAC_Interpolation_Mode11 {2} \ + CONFIG.DAC_Invsinc_Ctrl00 {false} \ + CONFIG.DAC_Mixer_Mode00 {0} \ + CONFIG.DAC_Mixer_Mode01 {0} \ + CONFIG.DAC_Mixer_Mode02 {2} \ + CONFIG.DAC_Mixer_Mode03 {2} \ + CONFIG.DAC_Mixer_Mode10 {0} \ + CONFIG.DAC_Mixer_Mode11 {0} \ + CONFIG.DAC_Mixer_Mode13 {2} \ + CONFIG.DAC_Mixer_Mode20 {2} \ + CONFIG.DAC_Mixer_Mode21 {2} \ + CONFIG.DAC_Mixer_Mode30 {2} \ + CONFIG.DAC_Mixer_Mode31 {2} \ + CONFIG.DAC_Mixer_Type00 {2} \ + CONFIG.DAC_Mixer_Type01 {2} \ + CONFIG.DAC_Mixer_Type02 {3} \ + CONFIG.DAC_Mixer_Type03 {3} \ + CONFIG.DAC_Mixer_Type10 {2} \ + CONFIG.DAC_Mixer_Type11 {2} \ + CONFIG.DAC_NCO_Freq00 {0.200} \ + CONFIG.DAC_NCO_Freq01 {0.200} \ + CONFIG.DAC_NCO_Freq10 {0.200} \ + CONFIG.DAC_NCO_Freq11 {0.200} \ + CONFIG.DAC_NCO_RTS {true} \ + CONFIG.DAC_Output_Current {1} \ + CONFIG.DAC_RTS {false} \ + CONFIG.DAC_Slice00_Enable {true} \ + CONFIG.DAC_Slice01_Enable {true} \ + CONFIG.DAC_Slice02_Enable {false} \ + CONFIG.DAC_Slice03_Enable {false} \ + CONFIG.DAC_Slice10_Enable {true} \ + CONFIG.DAC_Slice11_Enable {true} \ + CONFIG.mADC_Data_Type00 {0} \ + CONFIG.mADC_Data_Type01 {0} \ + CONFIG.mADC_Data_Type02 {0} \ + CONFIG.mADC_Data_Type03 {0} \ + CONFIG.mADC_Data_Width00 {8} \ + CONFIG.mADC_Data_Width01 {8} \ + CONFIG.mADC_Data_Width02 {8} \ + CONFIG.mADC_Data_Width03 {8} \ + CONFIG.mADC_Decimation_Mode00 {0} \ + CONFIG.mADC_Decimation_Mode01 {0} \ + CONFIG.mADC_Decimation_Mode02 {0} \ + CONFIG.mADC_Decimation_Mode03 {0} \ + CONFIG.mADC_Dither00 {true} \ + CONFIG.mADC_Dither01 {true} \ + CONFIG.mADC_Dither02 {true} \ + CONFIG.mADC_Dither03 {true} \ + CONFIG.mADC_Enable {0} \ + CONFIG.mADC_Fabric_Freq {0.0} \ + CONFIG.mADC_Mixer_Mode00 {2} \ + CONFIG.mADC_Mixer_Mode01 {2} \ + CONFIG.mADC_Mixer_Mode02 {2} \ + CONFIG.mADC_Mixer_Mode03 {2} \ + CONFIG.mADC_Mixer_Type00 {3} \ + CONFIG.mADC_Mixer_Type01 {3} \ + CONFIG.mADC_Mixer_Type02 {3} \ + CONFIG.mADC_Mixer_Type03 {3} \ + CONFIG.mADC_Multi_Tile_Sync {false} \ + CONFIG.mADC_NCO_Freq02 {0.0} \ + CONFIG.mADC_NCO_Freq03 {0.0} \ + CONFIG.mADC_Outclk_Freq {15.625} \ + CONFIG.mADC_Refclk_Freq {2000.000} \ + CONFIG.mADC_Sampling_Rate {2.0} \ + CONFIG.mADC_Slice00_Enable {false} \ + CONFIG.mADC_Slice01_Enable {false} \ + CONFIG.mADC_Slice02_Enable {false} \ + CONFIG.mADC_Slice03_Enable {false} \ + CONFIG.mDAC_Band {0} \ + CONFIG.mDAC_Data_Type00 {0} \ + CONFIG.mDAC_Data_Type01 {0} \ + CONFIG.mDAC_Data_Width00 {2} \ + CONFIG.mDAC_Data_Width01 {2} \ + CONFIG.mDAC_Data_Width02 {16} \ + CONFIG.mDAC_Data_Width03 {16} \ + CONFIG.mDAC_Enable {1} \ + CONFIG.mDAC_Fabric_Freq {368.640} \ + CONFIG.mDAC_Interpolation_Mode00 {8} \ + CONFIG.mDAC_Interpolation_Mode01 {8} \ + CONFIG.mDAC_Interpolation_Mode02 {0} \ + CONFIG.mDAC_Interpolation_Mode03 {0} \ + CONFIG.mDAC_Invsinc_Ctrl00 {false} \ + CONFIG.mDAC_Mixer_Mode00 {0} \ + CONFIG.mDAC_Mixer_Mode01 {0} \ + CONFIG.mDAC_Mixer_Mode02 {2} \ + CONFIG.mDAC_Mixer_Mode03 {2} \ + CONFIG.mDAC_Mixer_Type00 {2} \ + CONFIG.mDAC_Mixer_Type01 {2} \ + CONFIG.mDAC_Mixer_Type02 {3} \ + CONFIG.mDAC_Mixer_Type03 {3} \ + CONFIG.mDAC_Multi_Tile_Sync {false} \ + CONFIG.mDAC_NCO_Freq01 {0} \ + CONFIG.mDAC_Outclk_Freq {184.320} \ + CONFIG.mDAC_Refclk_Freq {2949.120} \ + CONFIG.mDAC_Sampling_Rate {2.94912} \ + CONFIG.mDAC_Slice00_Enable {true} \ + CONFIG.mDAC_Slice01_Enable {true} \ + CONFIG.mDAC_Slice02_Enable {false} \ + CONFIG.mDAC_Slice03_Enable {false} \ + ] $rf_data_converter + + # Create instance: rf_nco_reset_0, and set properties + set block_name rf_nco_reset + set block_cell_name rf_nco_reset_0 + if { [catch {set rf_nco_reset_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $rf_nco_reset_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: rf_reset_controller_0, and set properties + set block_name x410_rf_reset_controller + set block_cell_name rf_reset_controller_0 + if { [catch {set rf_reset_controller_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $rf_reset_controller_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: rf_reset_controller_1, and set properties + set block_name x410_rf_reset_controller + set block_cell_name rf_reset_controller_1 + if { [catch {set rf_reset_controller_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $rf_reset_controller_1 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: rfdc_adc_map, and set properties + set rfdc_adc_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_adc_map ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0b0000001001100000000000000100} \ + CONFIG.CONST_WIDTH {32} \ + ] $rfdc_adc_map + + # Create instance: rfdc_dac_map, and set properties + set rfdc_dac_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_dac_map ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0b0000010100010000000001000000} \ + CONFIG.CONST_WIDTH {32} \ + ] $rfdc_dac_map + + # Create instance: slice_iqswap_11_8_radio0, and set properties + set slice_iqswap_11_8_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_11_8_radio0 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {11} \ + CONFIG.DIN_TO {8} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_11_8_radio0 + + # Create instance: slice_iqswap_11_8_radio1, and set properties + set slice_iqswap_11_8_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_11_8_radio1 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {11} \ + CONFIG.DIN_TO {8} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_11_8_radio1 + + # Create instance: slice_iqswap_3_0_radio0, and set properties + set slice_iqswap_3_0_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_3_0_radio0 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_3_0_radio0 + + # Create instance: slice_iqswap_3_0_radio1, and set properties + set slice_iqswap_3_0_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_3_0_radio1 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_3_0_radio1 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_pins axi_interconnect_rf/M06_AXI] [get_bd_intf_pins calibration_muxes/S_AXI_1] + connect_bd_intf_net -intf_net adc0_clk_0_1 [get_bd_intf_pins adc0_clk] [get_bd_intf_pins rf_data_converter/adc0_clk] + connect_bd_intf_net -intf_net adc2_clk_0_1 [get_bd_intf_pins adc2_clk] [get_bd_intf_pins rf_data_converter/adc2_clk] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_rf/M00_AXI] [get_bd_intf_pins rf_data_converter/s_axi] + connect_bd_intf_net -intf_net axi_interconnect_rf_M01_AXI [get_bd_intf_pins axi_interconnect_rf/M01_AXI] [get_bd_intf_pins data_clock_mmcm/s_axi_lite] + connect_bd_intf_net -intf_net axi_interconnect_rf_M02_AXI [get_bd_intf_pins axi_interconnect_rf/M02_AXI] [get_bd_intf_pins reg_invert_iq_radio0/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M03_AXI [get_bd_intf_pins axi_interconnect_rf/M03_AXI] [get_bd_intf_pins reg_reset_mmcm/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M04_AXI [get_bd_intf_pins axi_interconnect_rf/M04_AXI] [get_bd_intf_pins reg_rf_reset_control_radio0/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M05_AXI [get_bd_intf_pins axi_interconnect_rf/M05_AXI] [get_bd_intf_pins reg_rf_axi_status/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M07_AXI [get_bd_intf_pins axi_interconnect_rf/M07_AXI] [get_bd_intf_pins reg_clock_gate_control/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M08_AXI [get_bd_intf_pins ThresholdRegister/S_AXI] [get_bd_intf_pins axi_interconnect_rf/M08_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M09_AXI [get_bd_intf_pins axi_interconnect_rf/M09_AXI] [get_bd_intf_pins reg_rfdc_tile_mapping/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M10_AXI [get_bd_intf_pins axi_interconnect_rf/M10_AXI] [get_bd_intf_pins reg_rfdc_info/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M11_AXI [get_bd_intf_pins axi_interconnect_rf/M11_AXI] [get_bd_intf_pins reg_invert_iq_radio1/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M12_AXI [get_bd_intf_pins axi_interconnect_rf/M12_AXI] [get_bd_intf_pins reg_rf_reset_control_radio1/S_AXI] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_0_0 [get_bd_intf_pins calibration_muxes/m_axis_0_0] [get_bd_intf_pins rf_data_converter/s00_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_1_0 [get_bd_intf_pins calibration_muxes/m_axis_1_0] [get_bd_intf_pins rf_data_converter/s01_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_2_0 [get_bd_intf_pins calibration_muxes/m_axis_2_0] [get_bd_intf_pins rf_data_converter/s10_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_3_0 [get_bd_intf_pins calibration_muxes/m_axis_3_0] [get_bd_intf_pins rf_data_converter/s11_axis] + connect_bd_intf_net -intf_net dac0_clk_0_1 [get_bd_intf_pins dac0_clk] [get_bd_intf_pins rf_data_converter/dac0_clk] + connect_bd_intf_net -intf_net dac1_clk_0_1 [get_bd_intf_pins dac1_clk] [get_bd_intf_pins rf_data_converter/dac1_clk] + connect_bd_intf_net -intf_net dac_tile228_ch0_din_1 [get_bd_intf_pins dac_tile228_ch0_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch0_din] + connect_bd_intf_net -intf_net dac_tile228_ch1_din_1 [get_bd_intf_pins dac_tile228_ch1_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch1_din] + connect_bd_intf_net -intf_net dac_tile229_ch0_din_1 [get_bd_intf_pins dac_tile229_ch0_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch0_din] + connect_bd_intf_net -intf_net dac_tile229_ch1_din_1 [get_bd_intf_pins dac_tile229_ch1_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch1_din] + connect_bd_intf_net -intf_net rf_data_converter_m00_axis [get_bd_intf_pins adc_tile224_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m00_axis] + connect_bd_intf_net -intf_net rf_data_converter_m01_axis [get_bd_intf_pins adc_tile224_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m01_axis] + connect_bd_intf_net -intf_net rf_data_converter_m02_axis [get_bd_intf_pins adc_tile224_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m02_axis] + connect_bd_intf_net -intf_net rf_data_converter_m03_axis [get_bd_intf_pins adc_tile224_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m03_axis] + connect_bd_intf_net -intf_net rf_data_converter_m20_axis [get_bd_intf_pins adc_tile226_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m20_axis] + connect_bd_intf_net -intf_net rf_data_converter_m21_axis [get_bd_intf_pins adc_tile226_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m21_axis] + connect_bd_intf_net -intf_net rf_data_converter_m22_axis [get_bd_intf_pins adc_tile226_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m22_axis] + connect_bd_intf_net -intf_net rf_data_converter_m23_axis [get_bd_intf_pins adc_tile226_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m23_axis] + connect_bd_intf_net -intf_net rf_data_converter_vout00 [get_bd_intf_pins dac_tile228_ch0_vout] [get_bd_intf_pins rf_data_converter/vout00] + connect_bd_intf_net -intf_net rf_data_converter_vout01 [get_bd_intf_pins dac_tile228_ch1_vout] [get_bd_intf_pins rf_data_converter/vout01] + connect_bd_intf_net -intf_net rf_data_converter_vout10 [get_bd_intf_pins dac_tile229_ch0_vout] [get_bd_intf_pins rf_data_converter/vout10] + connect_bd_intf_net -intf_net rf_data_converter_vout11 [get_bd_intf_pins dac_tile229_ch1_vout] [get_bd_intf_pins rf_data_converter/vout11] + connect_bd_intf_net -intf_net s_axi_config_1 [get_bd_intf_pins s_axi_config] [get_bd_intf_pins axi_interconnect_rf/S00_AXI] + connect_bd_intf_net -intf_net sysref_in_0_1 [get_bd_intf_pins sysref_rf_in] [get_bd_intf_pins rf_data_converter/sysref_in] + connect_bd_intf_net -intf_net vin0_01_0_1 [get_bd_intf_pins adc_tile224_ch0_vin] [get_bd_intf_pins rf_data_converter/vin0_01] + connect_bd_intf_net -intf_net vin0_23_0_1 [get_bd_intf_pins adc_tile224_ch1_vin] [get_bd_intf_pins rf_data_converter/vin0_23] + connect_bd_intf_net -intf_net vin2_01_0_1 [get_bd_intf_pins adc_tile226_ch0_vin] [get_bd_intf_pins rf_data_converter/vin2_01] + connect_bd_intf_net -intf_net vin2_23_0_1 [get_bd_intf_pins adc_tile226_ch1_vin] [get_bd_intf_pins rf_data_converter/vin2_23] + + # Create port connections + connect_bd_net -net M02_ARESETN_1 [get_bd_pins axi_interconnect_rf/M02_ARESETN] [get_bd_pins axi_interconnect_rf/M11_ARESETN] [get_bd_pins const_1/dout] [get_bd_pins reg_invert_iq_radio0/s_axi_aresetn] [get_bd_pins reg_invert_iq_radio1/s_axi_aresetn] + connect_bd_net -net adc_reset_pulse_dclk_1 [get_bd_pins adc_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dAdcResetPulse] [get_bd_pins rf_reset_controller_1/dAdcResetPulse] + connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_rclk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] + connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk] [get_bd_pins rf_nco_reset_0/dSysref] + connect_bd_net -net clk_in1_0_1 [get_bd_pins pll_ref_clk_in] [get_bd_pins data_clock_mmcm/clk_in1] + connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i] + connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid] + connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked] + connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_ce] + connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg1x] [get_bd_pins rf_clock_buffers/rfdc_clk_ce] + connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dDacResetPulse] [get_bd_pins rf_reset_controller_1/dDacResetPulse] + connect_bd_net -net data_clk_2x_pll [get_bd_pins clock_gates_0/DataClk2xPll] [get_bd_pins data_clock_mmcm/data_clk_2x] + connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins clock_gates_0/DataClk1x] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/DataClk] [get_bd_pins rf_reset_controller_1/DataClk] + connect_bd_net -net data_clock_mmcm_data_clk1 [get_bd_pins clock_gates_0/DataClk1xPll] [get_bd_pins data_clock_mmcm/data_clk] + connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins clock_gates_0/DataClk2x] [get_bd_pins rf_reset_controller_0/DataClk2x] [get_bd_pins rf_reset_controller_1/DataClk2x] + connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked] + connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins rfdc_clk] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_0/RfClk] [get_bd_pins rf_reset_controller_1/RfClk] + connect_bd_net -net data_clock_mmcm_rfdc_clk1 [get_bd_pins data_clock_mmcm/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk_pll] + connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins rfdc_clk_2x] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_clock_buffers/rfdc_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x] [get_bd_pins rf_reset_controller_1/RfClk2x] + connect_bd_net -net data_clock_mmcm_rfdc_clk_2x1 [get_bd_pins data_clock_mmcm/rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_pll] + connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk] + connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks] + connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_rclk] [get_bd_pins capture_sysref/enable_rclk] + connect_bd_net -net gpio2_io_i_0_2 [get_bd_pins rf_dsp_info_sclk] [get_bd_pins reg_rf_axi_status/gpio2_io_i] + connect_bd_net -net gpio_io_i_0_1 [get_bd_pins rf_axi_status_sclk] [get_bd_pins reg_rf_axi_status/gpio_io_i] + connect_bd_net -net reg_invert_iq_radio1_gpio_io_o [get_bd_pins reg_invert_iq_radio1/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio1/Din] [get_bd_pins slice_iqswap_3_0_radio1/Din] + connect_bd_net -net reg_reset_mmcm_gpio_io_o [get_bd_pins axi_interconnect_rf/M01_ARESETN] [get_bd_pins clock_gates_0/rPllReset_n] [get_bd_pins data_clock_mmcm/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/gpio_io_o] + connect_bd_net -net reg_rf_reset_control1_gpio_io_o [get_bd_pins clock_gates_0/rSoftwareControl] [get_bd_pins reg_clock_gate_control/gpio_io_o] + connect_bd_net -net reg_rf_reset_control_radio1_gpio_io_o [get_bd_pins reg_rf_reset_control_radio1/gpio_io_o] [get_bd_pins rf_reset_controller_1/cSoftwareControl] + connect_bd_net -net reg_rf_resets_gpio_io_o [get_bd_pins reg_rf_reset_control_radio0/gpio_io_o] [get_bd_pins rf_reset_controller_0/cSoftwareControl] + connect_bd_net -net rf_data_converter_adc0_01_over_threshold1 [get_bd_pins ThresholdRegister/In0] [get_bd_pins rf_data_converter/adc0_01_over_threshold1] + connect_bd_net -net rf_data_converter_adc0_01_over_threshold2 [get_bd_pins ThresholdRegister/In1] [get_bd_pins rf_data_converter/adc0_01_over_threshold2] + connect_bd_net -net rf_data_converter_adc0_23_over_threshold1 [get_bd_pins ThresholdRegister/In2] [get_bd_pins rf_data_converter/adc0_23_over_threshold1] + connect_bd_net -net rf_data_converter_adc0_23_over_threshold2 [get_bd_pins ThresholdRegister/In3] [get_bd_pins rf_data_converter/adc0_23_over_threshold2] + connect_bd_net -net rf_data_converter_adc0_nco_update_busy [get_bd_pins rf_data_converter/adc0_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc0xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_adc2_01_over_threshold1 [get_bd_pins ThresholdRegister/In5] [get_bd_pins rf_data_converter/adc2_01_over_threshold1] + connect_bd_net -net rf_data_converter_adc2_01_over_threshold2 [get_bd_pins ThresholdRegister/In6] [get_bd_pins rf_data_converter/adc2_01_over_threshold2] + connect_bd_net -net rf_data_converter_adc2_23_over_threshold1 [get_bd_pins ThresholdRegister/In7] [get_bd_pins rf_data_converter/adc2_23_over_threshold1] + connect_bd_net -net rf_data_converter_adc2_23_over_threshold2 [get_bd_pins ThresholdRegister/In8] [get_bd_pins rf_data_converter/adc2_23_over_threshold2] + connect_bd_net -net rf_data_converter_adc2_nco_update_busy [get_bd_pins rf_data_converter/adc2_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc2xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_dac0_nco_update_busy [get_bd_pins rf_data_converter/dac0_nco_update_busy] [get_bd_pins rf_nco_reset_0/cDac0xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_dac1_nco_update_busy [get_bd_pins rf_data_converter/dac1_nco_update_busy] [get_bd_pins rf_nco_reset_0/cDac1xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_irq [get_bd_pins rfdc_irq] [get_bd_pins rf_data_converter/irq] + connect_bd_net -net rf_nco_reset_0_cAdc0xNcoUpdateReq [get_bd_pins rf_data_converter/adc0_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc0xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cAdc2xNcoUpdateReq [get_bd_pins rf_data_converter/adc2_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc2xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cDac0xNcoUpdateReq [get_bd_pins rf_data_converter/dac0_nco_update_req] [get_bd_pins rf_nco_reset_0/cDac0xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cDac0xSysrefIntGating [get_bd_pins rf_data_converter/dac0_sysref_int_gating] [get_bd_pins rf_nco_reset_0/cDac0xSysrefIntGating] + connect_bd_net -net rf_nco_reset_0_cDac0xSysrefIntReenable [get_bd_pins rf_data_converter/dac0_sysref_int_reenable] [get_bd_pins rf_nco_reset_0/cDac0xSysrefIntReenable] + connect_bd_net -net rf_nco_reset_0_cDac1xNcoUpdateReq [get_bd_pins rf_data_converter/dac1_nco_update_req] [get_bd_pins rf_nco_reset_0/cDac1xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cNcoPhaseRst [get_bd_pins rf_data_converter/adc0_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc0_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_23_nco_phase_rst] [get_bd_pins rf_data_converter/dac00_nco_phase_rst] [get_bd_pins rf_data_converter/dac01_nco_phase_rst] [get_bd_pins rf_data_converter/dac10_nco_phase_rst] [get_bd_pins rf_data_converter/dac11_nco_phase_rst] [get_bd_pins rf_nco_reset_0/cNcoPhaseRst] + connect_bd_net -net rf_nco_reset_0_cNcoUpdateEn [get_bd_pins rf_data_converter/adc0_01_nco_update_en] [get_bd_pins rf_data_converter/adc0_23_nco_update_en] [get_bd_pins rf_data_converter/adc2_01_nco_update_en] [get_bd_pins rf_data_converter/adc2_23_nco_update_en] [get_bd_pins rf_data_converter/dac00_nco_update_en] [get_bd_pins rf_data_converter/dac01_nco_update_en] [get_bd_pins rf_data_converter/dac10_nco_update_en] [get_bd_pins rf_data_converter/dac11_nco_update_en] [get_bd_pins rf_nco_reset_0/cNcoUpdateEn] + connect_bd_net -net rf_nco_reset_0_dNcoResetDone [get_bd_pins nco_reset_done_dclk] [get_bd_pins rf_nco_reset_0/dNcoResetDone] + connect_bd_net -net rf_reset_controller_0_cSoftwareStatus [get_bd_pins reg_rf_reset_control_radio0/gpio2_io_i] [get_bd_pins rf_reset_controller_0/cSoftwareStatus] + connect_bd_net -net rf_reset_controller_0_d2DacFirReset_n [get_bd_pins dac_data_in_resetn_dclk2x] [get_bd_pins rf_reset_controller_0/d2DacFirReset_n] + connect_bd_net -net rf_reset_controller_0_dAdcDataOutReset_n [get_bd_pins adc_data_out_resetn_dclk] [get_bd_pins rf_reset_controller_0/dAdcDataOutReset_n] + connect_bd_net -net rf_reset_controller_0_dDacDataInReset_n [get_bd_pins dac_data_in_resetn_dclk] [get_bd_pins rf_reset_controller_0/dDacDataInReset_n] + connect_bd_net -net rf_reset_controller_0_r2AdcFirReset_n [get_bd_pins fir_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2AdcFirReset_n] + connect_bd_net -net rf_reset_controller_0_r2DacFirReset_n [get_bd_pins dac_data_in_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2DacFirReset_n] + connect_bd_net -net rf_reset_controller_0_rAdcEnableData [get_bd_pins adc_enable_data_rclk] [get_bd_pins rf_reset_controller_0/rAdcEnableData] + connect_bd_net -net rf_reset_controller_0_rAdcGearboxReset_n [get_bd_pins adc_rfdc_axi_resetn_rclk] [get_bd_pins rf_reset_controller_0/rAdcGearboxReset_n] + connect_bd_net -net rf_reset_controller_0_rAdcRfdcAxiReset_n [get_bd_pins rf_data_converter/m0_axis_aresetn] [get_bd_pins rf_reset_controller_0/rAdcRfdcAxiReset_n] + connect_bd_net -net rf_reset_controller_0_rDacGearboxReset_n [get_bd_pins dac_data_in_resetn_rclk] [get_bd_pins rf_reset_controller_0/rDacGearboxReset_n] + connect_bd_net -net rf_reset_controller_0_rDacRfdcAxiReset_n [get_bd_pins rf_data_converter/s0_axis_aresetn] [get_bd_pins rf_reset_controller_0/rDacRfdcAxiReset_n] + connect_bd_net -net rf_reset_controller_1_cSoftwareStatus [get_bd_pins reg_rf_reset_control_radio1/gpio2_io_i] [get_bd_pins rf_reset_controller_1/cSoftwareStatus] + connect_bd_net -net rf_reset_controller_1_rAdcRfdcAxiReset_n [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_reset_controller_1/rAdcRfdcAxiReset_n] + connect_bd_net -net rf_reset_controller_1_rDacRfdcAxiReset_n [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_1/rDacRfdcAxiReset_n] + connect_bd_net -net rf_rfdc_info_sclk_1 [get_bd_pins rf_rfdc_info_sclk] [get_bd_pins reg_rfdc_info/gpio_io_i] + connect_bd_net -net rfdc_adc_map_dout [get_bd_pins reg_rfdc_tile_mapping/gpio_io_i] [get_bd_pins rfdc_adc_map/dout] + connect_bd_net -net rfdc_regs_gpio_io_o [get_bd_pins reg_invert_iq_radio0/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio0/Din] [get_bd_pins slice_iqswap_3_0_radio0/Din] + connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/M09_ARESETN] [get_bd_pins axi_interconnect_rf/M10_ARESETN] [get_bd_pins axi_interconnect_rf/M12_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aresetn] [get_bd_pins reg_rfdc_info/s_axi_aresetn] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn] + connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/M09_ACLK] [get_bd_pins axi_interconnect_rf/M10_ACLK] [get_bd_pins axi_interconnect_rf/M12_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aclk] [get_bd_pins reg_rfdc_info/s_axi_aclk] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] [get_bd_pins rf_reset_controller_1/ConfigClk] + connect_bd_net -net slice_iqswap_11_8_radio0_Dout [get_bd_pins radio0_invert_dac_iq_r0clk] [get_bd_pins slice_iqswap_11_8_radio0/Dout] + connect_bd_net -net slice_iqswap_11_8_radio1_Dout [get_bd_pins radio1_invert_dac_iq_r1clk] [get_bd_pins slice_iqswap_11_8_radio1/Dout] + connect_bd_net -net slice_iqswap_3_0_radio0_Dout [get_bd_pins radio0_invert_adc_iq_r0clk] [get_bd_pins slice_iqswap_3_0_radio0/Dout] + connect_bd_net -net slice_iqswap_3_0_radio1_Dout [get_bd_pins radio1_invert_adc_iq_r1clk] [get_bd_pins slice_iqswap_3_0_radio1/Dout] + connect_bd_net -net start_nco_reset_rclk_1 [get_bd_pins start_nco_reset_dclk] [get_bd_pins rf_nco_reset_0/dStartNcoReset] + connect_bd_net -net sysref_in_0_2 [get_bd_pins sysref_pl_in] [get_bd_pins capture_sysref/sysref_in] + connect_bd_net -net xlconstant_0_dout [get_bd_pins rf_nco_reset_0/cAdc1xNcoUpdateBusy] [get_bd_pins rf_nco_reset_0/cAdc3xNcoUpdateBusy] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_1_dout [get_bd_pins reg_rfdc_tile_mapping/gpio2_io_i] [get_bd_pins rfdc_dac_map/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: ps +proc create_hier_cell_ps { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ps() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_app + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_core + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_internal + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mpm_ep + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rf + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_rpu + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_eth_dma + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hpc0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hpc1 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_eth_dma + + + # Create pins + create_bd_pin -dir I -type clk bus_clk + create_bd_pin -dir I -type rst bus_rstn + create_bd_pin -dir I -type clk clk40 + create_bd_pin -dir I -type rst clk40_rstn + create_bd_pin -dir I irq0_lpd_rpu_n + create_bd_pin -dir I irq1_lpd_rpu_n + create_bd_pin -dir IO jtag0_tck + create_bd_pin -dir IO jtag0_tdi + create_bd_pin -dir I jtag0_tdo + create_bd_pin -dir IO jtag0_tms + create_bd_pin -dir O -type clk pl_clk40 + create_bd_pin -dir O -type clk pl_clk100 + create_bd_pin -dir O -type clk pl_clk166 + create_bd_pin -dir O -type clk pl_clk200 + create_bd_pin -dir I -from 7 -to 0 -type intr pl_ps_irq0 + create_bd_pin -dir I -from 5 -to 0 pl_ps_irq1_1 + create_bd_pin -dir O -type rst pl_resetn0 + create_bd_pin -dir O -type rst pl_resetn1 + create_bd_pin -dir O -type rst pl_resetn2 + create_bd_pin -dir O -type rst pl_resetn3 + create_bd_pin -dir I -type clk s_axi_hp0_aclk + create_bd_pin -dir I -type clk s_axi_hp1_aclk + create_bd_pin -dir I -type clk s_axi_hpc0_aclk + + # Create instance: axi_interconnect_common + create_hier_cell_axi_interconnect_common $hier_obj axi_interconnect_common + + # Create instance: cpld_jtag_engine, and set properties + set cpld_jtag_engine [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 cpld_jtag_engine ] + + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.CLK_DOMAIN {x410_ps_rfdc_bd_clk40} \ + ] [get_bd_intf_pins /ps/cpld_jtag_engine/S_AXI] + + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.CLK_DOMAIN {x410_ps_rfdc_bd_clk40} \ + ] [get_bd_pins /ps/cpld_jtag_engine/S_AXI_ACLK] + + # Create instance: eth_dma_internal + create_hier_cell_eth_dma_internal $hier_obj eth_dma_internal + + # Create instance: hpc1_axi_interconnect, and set properties + set hpc1_axi_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 hpc1_axi_interconnect ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $hpc1_axi_interconnect + + # Create instance: inst_zynq_ps, and set properties + set inst_zynq_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 inst_zynq_ps ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {inout} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {slow} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {disable} \ + CONFIG.PSU_MIO_10_SLEW {slow} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {disable} \ + CONFIG.PSU_MIO_11_SLEW {slow} \ + CONFIG.PSU_MIO_12_DIRECTION {inout} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {slow} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {slow} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {slow} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {slow} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {slow} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {slow} \ + CONFIG.PSU_MIO_18_DIRECTION {inout} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {slow} \ + CONFIG.PSU_MIO_19_DIRECTION {inout} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {slow} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {slow} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {slow} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {slow} \ + CONFIG.PSU_MIO_22_DIRECTION {out} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {slow} \ + CONFIG.PSU_MIO_23_DIRECTION {out} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {slow} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {slow} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {slow} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {slow} \ + CONFIG.PSU_MIO_27_DIRECTION {inout} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {slow} \ + CONFIG.PSU_MIO_28_DIRECTION {inout} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {slow} \ + CONFIG.PSU_MIO_29_DIRECTION {inout} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {slow} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {slow} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {out} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {slow} \ + CONFIG.PSU_MIO_32_DIRECTION {out} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {slow} \ + CONFIG.PSU_MIO_33_DIRECTION {in} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {out} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {out} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {slow} \ + CONFIG.PSU_MIO_36_DIRECTION {inout} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {slow} \ + CONFIG.PSU_MIO_37_DIRECTION {inout} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {slow} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {slow} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {slow} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {slow} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {slow} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {slow} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {slow} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {slow} \ + CONFIG.PSU_MIO_44_DIRECTION {inout} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pulldown} \ + CONFIG.PSU_MIO_44_SLEW {slow} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {slow} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {slow} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {slow} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {slow} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {slow} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {slow} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {slow} \ + CONFIG.PSU_MIO_52_DIRECTION {in} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {in} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {slow} \ + CONFIG.PSU_MIO_55_DIRECTION {in} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {slow} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {slow} \ + CONFIG.PSU_MIO_58_DIRECTION {out} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {slow} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {slow} \ + CONFIG.PSU_MIO_5_DIRECTION {inout} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {slow} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {slow} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {slow} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {slow} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {slow} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {slow} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {slow} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {slow} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {slow} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {slow} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {slow} \ + CONFIG.PSU_MIO_6_DIRECTION {inout} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pulldown} \ + CONFIG.PSU_MIO_6_SLEW {slow} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {slow} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {slow} \ + CONFIG.PSU_MIO_7_DIRECTION {out} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {slow} \ + CONFIG.PSU_MIO_8_DIRECTION {out} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {slow} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {slow} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI\ +1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0\ +MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART\ +1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1\ +MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\ +0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3}\ + CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {1} \ + CONFIG.PSU__ACPU3__POWER__ON {1} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1199.988037} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ + CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ + CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1200} \ + CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {72} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {63} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ + CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {10} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ + CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {320} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \ + CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ + CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ + CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \ + CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {64} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ + CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ + CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ + CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ + CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ + CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {266.664001} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \ + CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ + CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {39.999599} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {10} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {40} \ + CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {166.664993} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {9} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {166.6667} \ + CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {DPLL} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {299.997009} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \ + CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {48} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ + CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ + CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {199.998001} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {4} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ + CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {33.333000} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {1} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {PSS_REF_CLK} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ + CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ + CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ + CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ + CONFIG.PSU__CRL_APB__USB3__ENABLE {0} \ + CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ + CONFIG.PSU__CSU_COHERENCY {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ + CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ + CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__AL {0} \ + CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ + CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ + CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ + CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ + CONFIG.PSU__DDRC__CL {16} \ + CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ + CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ + CONFIG.PSU__DDRC__COMPONENTS {Components} \ + CONFIG.PSU__DDRC__CWL {12} \ + CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ + CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ + CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ + CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ + CONFIG.PSU__DDRC__DDR4_T_REF_MODE {1} \ + CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {High (95 Max)} \ + CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ + CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ + CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ + CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ + CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ + CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ + CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ + CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ + CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ + CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ + CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ + CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ + CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ + CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ + CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ + CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ + CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ + CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ + CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ + CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ + CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ + CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ + CONFIG.PSU__DDRC__ECC {Disabled} \ + CONFIG.PSU__DDRC__ECC_SCRUB {0} \ + CONFIG.PSU__DDRC__ENABLE {1} \ + CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ + CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ + CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ + CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ + CONFIG.PSU__DDRC__FGRM {1X} \ + CONFIG.PSU__DDRC__FREQ_MHZ {1} \ + CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ + CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ + CONFIG.PSU__DDRC__LP_ASR {manual normal} \ + CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ + CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ + CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ + CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ + CONFIG.PSU__DDRC__PLL_BYPASS {0} \ + CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ + CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ + CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ + CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ + CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ + CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ + CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2400P} \ + CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ + CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ + CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ + CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ + CONFIG.PSU__DDRC__T_FAW {30.0} \ + CONFIG.PSU__DDRC__T_RAS_MIN {32} \ + CONFIG.PSU__DDRC__T_RC {45.32} \ + CONFIG.PSU__DDRC__T_RCD {16} \ + CONFIG.PSU__DDRC__T_RP {16} \ + CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ + CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ + CONFIG.PSU__DDRC__VREF {1} \ + CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {1} \ + CONFIG.PSU__DDR_QOS_ENABLE {0} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ + CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ + CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ + CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ + CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ + CONFIG.PSU__DDR__INTERFACE__FREQMHZ {600.000} \ + CONFIG.PSU__DEVICE_TYPE {RFSOC} \ + CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ + CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__DLL__ISUSED {1} \ + CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ + CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET0__PTP__ENABLE {0} \ + CONFIG.PSU__ENET0__TSU__ENABLE {0} \ + CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET1__PTP__ENABLE {0} \ + CONFIG.PSU__ENET1__TSU__ENABLE {0} \ + CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ + CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__ENET2__PTP__ENABLE {0} \ + CONFIG.PSU__ENET2__TSU__ENABLE {0} \ + CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ + CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ + CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ + CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__ENET3__PTP__ENABLE {0} \ + CONFIG.PSU__ENET3__TSU__ENABLE {0} \ + CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ + CONFIG.PSU__EN_EMIO_TRACE {0} \ + CONFIG.PSU__EP__IP {0} \ + CONFIG.PSU__EXPAND__CORESIGHT {0} \ + CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ + CONFIG.PSU__EXPAND__GIC {0} \ + CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ + CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ + CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ + CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ + CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__FPGA_PL0_ENABLE {1} \ + CONFIG.PSU__FPGA_PL1_ENABLE {1} \ + CONFIG.PSU__FPGA_PL2_ENABLE {1} \ + CONFIG.PSU__FPGA_PL3_ENABLE {1} \ + CONFIG.PSU__FP__POWER__ON {1} \ + CONFIG.PSU__FTM__CTI_IN_0 {0} \ + CONFIG.PSU__FTM__CTI_IN_1 {0} \ + CONFIG.PSU__FTM__CTI_IN_2 {0} \ + CONFIG.PSU__FTM__CTI_IN_3 {0} \ + CONFIG.PSU__FTM__CTI_OUT_0 {0} \ + CONFIG.PSU__FTM__CTI_OUT_1 {0} \ + CONFIG.PSU__FTM__CTI_OUT_2 {0} \ + CONFIG.PSU__FTM__CTI_OUT_3 {0} \ + CONFIG.PSU__FTM__GPI {0} \ + CONFIG.PSU__FTM__GPO {0} \ + CONFIG.PSU__GEM0_COHERENCY {0} \ + CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM1_COHERENCY {0} \ + CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM2_COHERENCY {0} \ + CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM3_COHERENCY {0} \ + CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__GEM__TSU__ENABLE {0} \ + CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ + CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ + CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ + CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ + CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ + CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {64} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {64} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[91:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {0} \ + CONFIG.PSU__GPU_PP1__POWER__ON {0} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 2 .. 3} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 36 .. 37} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND_COHERENCY {0} \ + CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {4} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__ECRC_CHECK {0} \ + CONFIG.PSU__PCIE__ECRC_ERR {0} \ + CONFIG.PSU__PCIE__ECRC_GEN {0} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ + CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MULTIHEADER {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ + CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL_CLK2_BUF {TRUE} \ + CONFIG.PSU__PL_CLK3_BUF {TRUE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {0} \ + CONFIG.PSU__PMU__GPO1__ENABLE {0} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {1} \ + CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ + CONFIG.PSU__PMU__GPO3__POLARITY {high} \ + CONFIG.PSU__PMU__GPO4__ENABLE {0} \ + CONFIG.PSU__PMU__GPO5__ENABLE {0} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {0} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__DEBUG {0} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000\ +;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware}\ + CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB\ +;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB\ +;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware}\ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ + CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {} \ + CONFIG.PSU__QSPI__PERIPHERAL__MODE {} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {