adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
42 lines
1.3 KiB
Makefile
42 lines
1.3 KiB
Makefile
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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XGE_PCS_PMA_SRCS = \
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$(IP_DIR)/xge_pcs_pma/ten_gige_phy.v \
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$(IP_DIR)/xge_pcs_pma/eth_10g.sv \
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$(IP_XGE_PCS_PMA_EXAMPLE_SRCS)
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IP_XGE_PCS_PMA_HDL_SIM_SRCS = $(IP_DIR)/xge_pcs_pma/model_10gbe.sv \
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$(wildcard $(addprefix $(IP_BUILD_DIR)/xge_pcs_pma/, \
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xge_pcs_pma.v \
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hdl/xxv_ethernet_v4_0_vl_rfs.sv \
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ip_0/hdl/*.v \
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ip_0/sim/*.v \
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xxv_ethernet_v4_0_0/*.v \
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))
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IP_XGE_PCS_PMA_EXAMPLE_SRCS = \
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$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_common_wrapper.v \
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$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_gt_gtye4_common_wrapper.v \
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$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/gtwizard_ultrascale_v1_7_gtye4_common.v \
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IP_XGE_PCS_PMA_SRCS = $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_BUILD_DIR)/xge_pcs_pma/xxv_ethernet_v4_0_0/xge_pcs_pma_wrapper.v
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IP_XGE_PCS_PMA_OUTS = \
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$(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci.out \
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$(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.v \
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$(IP_XGE_PCS_PMA_EXAMPLE_SRCS) : $(IP_XGE_PCS_PMA_OUTS)
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.INTERMEDIATE: IP_XGE_PCS_PMA_TRGT
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$(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS): IP_XGE_PCS_PMA_TRGT
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@:
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IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci
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$(call BUILD_VIVADO_IP_WITH_SUBCORES,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
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