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fpga: x400: Fix PRC divider register map

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Original-commit: 367adaa35e1f707be52011d491025193e4436eb1
This commit is contained in:
Mark Eid
2023-07-10 10:45:09 -06:00
committed by Humberto Jimenez
parent cde17c060f
commit 1b9a79381a
3 changed files with 21 additions and 21 deletions
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top/x400/doc/X410/X410_FPGA_right.htm
+7 -7
View File
@@ -6621,11 +6621,11 @@ Control registers for PPS generation.
<td> <td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p> <p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
<p>Enables the PPS signal in radio clock domain. Please make sure that <p>Enables the PPS signal in radio clock domain. Please make sure that
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a> and @.PRC_RC_DIVIDER are the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
set before enabling this bit. It is recommended to disable the PPS <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
for changes on the other values. Use a wait time of at least 1 second to disable the PPS for changes on the other values. Use a wait time of
before changing this value to ensure the values are stable for the at least 1 second before changing this value to ensure the values are
next PPS edge.</p> stable for the next PPS edge.</p>
</td> </td>
</tr> </tr>
@@ -7014,7 +7014,7 @@ Total Offset =</td></tr>
<div class="info"> <div class="info">
RESERVED. This register is not implemented on X4xx. GPS is connected RESERVED. This register is not implemented on X4xx. GPS is connected
to the PS via a UART. to the PS via a UART.
</div> </div>
@@ -7096,7 +7096,7 @@ Total Offset =</td></tr>
<div class="info"> <div class="info">
RESERVED. This register is not implemented on X4xx. GPS is connected RESERVED. This register is not implemented on X4xx. GPS is connected
to the PS via a UART. to the PS via a UART.
</div> </div>
top/x400/doc/X440/X440_FPGA_right.htm
+7 -7
View File
@@ -6907,11 +6907,11 @@ Control registers for PPS generation.
<td> <td>
<p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p> <p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
<p>Enables the PPS signal in radio clock domain. Please make sure that <p>Enables the PPS signal in radio clock domain. Please make sure that
the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a> and @.PRC_RC_DIVIDER are the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
set before enabling this bit. It is recommended to disable the PPS <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
for changes on the other values. Use a wait time of at least 1 second to disable the PPS for changes on the other values. Use a wait time of
before changing this value to ensure the values are stable for the at least 1 second before changing this value to ensure the values are
next PPS edge.</p> stable for the next PPS edge.</p>
</td> </td>
</tr> </tr>
@@ -7300,7 +7300,7 @@ Total Offset =</td></tr>
<div class="info"> <div class="info">
RESERVED. This register is not implemented on X4xx. GPS is connected RESERVED. This register is not implemented on X4xx. GPS is connected
to the PS via a UART. to the PS via a UART.
</div> </div>
@@ -7382,7 +7382,7 @@ Total Offset =</td></tr>
<div class="info"> <div class="info">
RESERVED. This register is not implemented on X4xx. GPS is connected RESERVED. This register is not implemented on X4xx. GPS is connected
to the PS via a UART. to the PS via a UART.
</div> </div>
top/x400/x4xx_global_regs.v
+7 -7
View File
@@ -603,11 +603,11 @@ endmodule
// <bitfield name="PPS_RC_ENABLED" range="31"> // <bitfield name="PPS_RC_ENABLED" range="31">
// <info> // <info>
// Enables the PPS signal in radio clock domain. Please make sure that // Enables the PPS signal in radio clock domain. Please make sure that
// the values of @.PPS_BRC_DELAY, @.PPS_PRC_DELAY and @.PRC_RC_DIVIDER are // the values of @.PPS_BRC_DELAY, @.PPS_PRC_DELAY, @.PRC_RC0_DIVIDER and
// set before enabling this bit. It is recommended to disable the PPS // @.PRC_RC1_DIVIDER are set before enabling this bit. It is recommended
// for changes on the other values. Use a wait time of at least 1 second // to disable the PPS for changes on the other values. Use a wait time of
// before changing this value to ensure the values are stable for the // at least 1 second before changing this value to ensure the values are
// next PPS edge. // stable for the next PPS edge.
// </info> // </info>
// </bitfield> // </bitfield>
// </register> // </register>
@@ -671,13 +671,13 @@ endmodule
// </register> // </register>
// <register name="GPS_CTRL_REG" offset="0x38" size="32"> // <register name="GPS_CTRL_REG" offset="0x38" size="32">
// <info> // <info>
// RESERVED. This register is not implemented on X4xx. GPS is connected // RESERVED. This register is not implemented on X4xx. GPS is connected
// to the PS via a UART. // to the PS via a UART.
// </info> // </info>
// </register> // </register>
// <register name="GPS_STATUS_REG" offset="0x3C" size="32" writable="false"> // <register name="GPS_STATUS_REG" offset="0x3C" size="32" writable="false">
// <info> // <info>
// RESERVED. This register is not implemented on X4xx. GPS is connected // RESERVED. This register is not implemented on X4xx. GPS is connected
// to the PS via a UART. // to the PS via a UART.
// </info> // </info>
// </register> // </register>