diff --git a/top/x400/doc/X410/X410_FPGA_right.htm b/top/x400/doc/X410/X410_FPGA_right.htm
index 0b6de9a..bbb4f5f 100644
--- a/top/x400/doc/X410/X410_FPGA_right.htm
+++ b/top/x400/doc/X410/X410_FPGA_right.htm
@@ -6621,11 +6621,11 @@ Control registers for PPS generation.
               <td>
                 <p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
                 <p>Enables the PPS signal in radio clock domain. Please make sure that
-          the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a> and @.PRC_RC_DIVIDER are
-          set before enabling this bit. It is recommended to disable the PPS
-          for changes on the other values. Use a wait time of at least 1 second
-          before changing this value to ensure the values are stable for the
-          next PPS edge.</p>
+          the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
+          <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
+          to disable the PPS for changes on the other values. Use a wait time of
+          at least 1 second before changing this value to ensure the values are
+          stable for the next PPS edge.</p>
             
               </td>
             </tr>
@@ -7014,7 +7014,7 @@ Total Offset =</td></tr>
 
 <div class="info">
 
-RESERVED. This register is not implemented on X4xx. GPS is connected 
+RESERVED. This register is not implemented on X4xx. GPS is connected
         to the PS via a UART.
 
 </div>
@@ -7096,7 +7096,7 @@ Total Offset =</td></tr>
 
 <div class="info">
 
-RESERVED. This register is not implemented on X4xx. GPS is connected 
+RESERVED. This register is not implemented on X4xx. GPS is connected
         to the PS via a UART.
 
 </div>
diff --git a/top/x400/doc/X440/X440_FPGA_right.htm b/top/x400/doc/X440/X440_FPGA_right.htm
index 0089b13..e9aa8c2 100644
--- a/top/x400/doc/X440/X440_FPGA_right.htm
+++ b/top/x400/doc/X440/X440_FPGA_right.htm
@@ -6907,11 +6907,11 @@ Control registers for PPS generation.
               <td>
                 <p><span class="name"><a name="GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_RC_ENABLED"></a>PPS_RC_ENABLED</span><span class="attr"> </span></p>
                 <p>Enables the PPS signal in radio clock domain. Please make sure that
-          the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a> and @.PRC_RC_DIVIDER are
-          set before enabling this bit. It is recommended to disable the PPS
-          for changes on the other values. Use a wait time of at least 1 second
-          before changing this value to ensure the values are stable for the
-          next PPS edge.</p>
+          the values of <a href="#GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG|PPS_BRC_DELAY">PPS_BRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PPS_PRC_DELAY">PPS_PRC_DELAY</a>, <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC0_DIVIDER">PRC_RC0_DIVIDER</a> and
+          <a href="#GLOBAL_REGS_REGMAP|PPS_CTRL_REG|PRC_RC1_DIVIDER">PRC_RC1_DIVIDER</a> are set before enabling this bit. It is recommended
+          to disable the PPS for changes on the other values. Use a wait time of
+          at least 1 second before changing this value to ensure the values are
+          stable for the next PPS edge.</p>
             
               </td>
             </tr>
@@ -7300,7 +7300,7 @@ Total Offset =</td></tr>
 
 <div class="info">
 
-RESERVED. This register is not implemented on X4xx. GPS is connected 
+RESERVED. This register is not implemented on X4xx. GPS is connected
         to the PS via a UART.
 
 </div>
@@ -7382,7 +7382,7 @@ Total Offset =</td></tr>
 
 <div class="info">
 
-RESERVED. This register is not implemented on X4xx. GPS is connected 
+RESERVED. This register is not implemented on X4xx. GPS is connected
         to the PS via a UART.
 
 </div>
diff --git a/top/x400/x4xx_global_regs.v b/top/x400/x4xx_global_regs.v
index 8c9e2f9..c4ca53d 100644
--- a/top/x400/x4xx_global_regs.v
+++ b/top/x400/x4xx_global_regs.v
@@ -603,11 +603,11 @@ endmodule
 //      <bitfield name="PPS_RC_ENABLED" range="31">
 //        <info>
 //          Enables the PPS signal in radio clock domain. Please make sure that
-//          the values of @.PPS_BRC_DELAY, @.PPS_PRC_DELAY and @.PRC_RC_DIVIDER are
-//          set before enabling this bit. It is recommended to disable the PPS
-//          for changes on the other values. Use a wait time of at least 1 second
-//          before changing this value to ensure the values are stable for the
-//          next PPS edge.
+//          the values of @.PPS_BRC_DELAY, @.PPS_PRC_DELAY, @.PRC_RC0_DIVIDER and
+//          @.PRC_RC1_DIVIDER are set before enabling this bit. It is recommended
+//          to disable the PPS for changes on the other values. Use a wait time of
+//          at least 1 second before changing this value to ensure the values are
+//          stable for the next PPS edge.
 //        </info>
 //      </bitfield>
 //    </register>
@@ -671,13 +671,13 @@ endmodule
 //    </register>
 //    <register name="GPS_CTRL_REG"        offset="0x38" size="32">
 //      <info>
-//        RESERVED. This register is not implemented on X4xx. GPS is connected 
+//        RESERVED. This register is not implemented on X4xx. GPS is connected
 //        to the PS via a UART.
 //      </info>
 //    </register>
 //    <register name="GPS_STATUS_REG"      offset="0x3C" size="32" writable="false">
 //      <info>
-//        RESERVED. This register is not implemented on X4xx. GPS is connected 
+//        RESERVED. This register is not implemented on X4xx. GPS is connected
 //        to the PS via a UART.
 //      </info>
 //    </register>