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fpga: x400: Fix PRC divider register map

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Original-commit: 367adaa35e1f707be52011d491025193e4436eb1
This commit is contained in:
Mark Eid
2023-07-10 10:45:09 -06:00
committed by Humberto Jimenez
parent cde17c060f
commit 1b9a79381a
3 changed files with 21 additions and 21 deletions
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top/x400/x4xx_global_regs.v
+7 -7
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@@ -603,11 +603,11 @@ endmodule
// <bitfield name="PPS_RC_ENABLED" range="31">
// <info>
// Enables the PPS signal in radio clock domain. Please make sure that
// the values of @.PPS_BRC_DELAY, @.PPS_PRC_DELAY and @.PRC_RC_DIVIDER are
// set before enabling this bit. It is recommended to disable the PPS
// for changes on the other values. Use a wait time of at least 1 second
// before changing this value to ensure the values are stable for the
// next PPS edge.
// the values of @.PPS_BRC_DELAY, @.PPS_PRC_DELAY, @.PRC_RC0_DIVIDER and
// @.PRC_RC1_DIVIDER are set before enabling this bit. It is recommended
// to disable the PPS for changes on the other values. Use a wait time of
// at least 1 second before changing this value to ensure the values are
// stable for the next PPS edge.
// </info>
// </bitfield>
// </register>
@@ -671,13 +671,13 @@ endmodule
// </register>
// <register name="GPS_CTRL_REG" offset="0x38" size="32">
// <info>
// RESERVED. This register is not implemented on X4xx. GPS is connected
// RESERVED. This register is not implemented on X4xx. GPS is connected
// to the PS via a UART.
// </info>
// </register>
// <register name="GPS_STATUS_REG" offset="0x3C" size="32" writable="false">
// <info>
// RESERVED. This register is not implemented on X4xx. GPS is connected
// RESERVED. This register is not implemented on X4xx. GPS is connected
// to the PS via a UART.
// </info>
// </register>