fpga: x400: Add 1x64, 2x64, and 1x128 DRAM interconnect

Original-commit: daf1ed2ad2fbb72f16a9909fa75a0ba9e2879583

top/x400/ip/Makefile.inc

@@ -9,7 +9,10 @@ include $(IP_DIR)/x4xx_ps_rfdc_bd/Makefile.inc
 include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc
 include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
 include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
+include $(IP_DIR)/axi_inter_1x64_512_bd/Makefile.inc
+include $(IP_DIR)/axi_inter_2x64_512_bd/Makefile.inc
 include $(IP_DIR)/axi_inter_4x64_512_bd/Makefile.inc
+include $(IP_DIR)/axi_inter_1x128_512_bd/Makefile.inc
 include $(IP_DIR)/axi_inter_2x128_512_bd/Makefile.inc
 include $(IP_DIR)/ddr4_64bits/Makefile.inc
 include $(IP_DIR)/adc_100m_bd/Makefile.inc
@@ -32,7 +35,10 @@ $(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
 $(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
 $(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \
 $(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
+$(IP_AXI_INTER_1X64_512_BD_SRCS) \
+$(IP_AXI_INTER_2X64_512_BD_SRCS) \
 $(IP_AXI_INTER_4X64_512_BD_SRCS) \
+$(IP_AXI_INTER_1X128_512_BD_SRCS) \
 $(IP_AXI_INTER_2X128_512_BD_SRCS) \
 $(IP_ADC_100M_BD_SRCS) \
 $(IP_ADC_100M_HDL_SRCS) \
@@ -61,7 +67,10 @@ $(BD_X4XX_PS_RFDC_BD_OUTS) \
 $(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
 $(BD_AXI_INTERCONNECT_ETH_BD_OUTS) \
 $(BD_AXI_INTERCONNECT_DMA_BD_OUTS) \
+$(BD_AXI_INTER_1x64_512_BD_OUTS) \
+$(BD_AXI_INTER_2x64_512_BD_OUTS) \
 $(BD_AXI_INTER_4x64_512_BD_OUTS) \
+$(BD_AXI_INTER_1X128_512_BD_OUTS) \
 $(BD_AXI_INTER_2X128_512_BD_OUTS) \
 $(BD_ADC_100M_BD_OUTS) \
 $(BD_ADC_400M_BD_OUTS)  \

top/x400/ip/axi_inter_1x128_512_bd/Makefile.inc

@@ -0,0 +1,32 @@
+#
+# Copyright 2023 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_AXI_INTER_1X128_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_1x128_512_bd/, \
+axi_inter_1x128_512_bd.tcl \
+)
+
+IP_AXI_INTER_1X128_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x128_512_bd/, \
+axi_inter_1x128_512_bd.tcl \
+)
+
+IP_AXI_INTER_1X128_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x128_512_bd/, \
+axi_inter_1x128_512_bd/axi_inter_1x128_512_bd.bd \
+)
+
+BD_AXI_INTER_1X128_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x128_512_bd/, \
+axi_inter_1x128_512_bd.bd.out \
+axi_inter_1x128_512_bd/axi_inter_1x128_512_bd_ooc.xdc \
+axi_inter_1x128_512_bd/synth/axi_inter_1x128_512_bd.v \
+)
+
+.INTERMEDIATE: IP_AXI_INTER_1X128_512_BD_TRGT
+$(IP_AXI_INTER_1X128_512_BD_SRCS) $(BD_AXI_INTER_1X128_512_BD_OUTS) $(IP_AXI_INTER_1X128_512_BDTCL_SRCS): IP_AXI_INTER_1X128_512_BD_TRGT
+	@:
+
+IP_AXI_INTER_1X128_512_BD_TRGT: $(IP_AXI_INTER_1X128_512_ORIG_SRCS)
+	$(call BUILD_VIVADO_BDTCL,axi_inter_1x128_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)

top/x400/ip/axi_inter_1x128_512_bd/axi_inter_1x128_512_bd.tcl

@@ -0,0 +1,288 @@
+
+################################################################
+# This is a generated script based on design: axi_inter_1x128_512_bd
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source axi_inter_1x128_512_bd_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name axi_inter_1x128_512_bd
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_dwidth_converter:2.1\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.DATA_WIDTH {512} \
+   CONFIG.FREQ_HZ {350000000} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4} \
+   ] $M0_AXI
+
+  set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.FREQ_HZ {350000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {1} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.MAX_BURST_LENGTH {256} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_READ_THREADS {1} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_THREADS {1} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {1} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $S0_AXI
+
+
+  # Create ports
+  set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
+   CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
+ ] $M0_AXI_ACLK
+  set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
+  set_property -dict [ list \
+   CONFIG.POLARITY {ACTIVE_LOW} \
+ ] $M0_AXI_ARESETN
+  set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {S0_AXI} \
+   CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
+ ] $S0_AXI_ACLK
+  set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
+
+  # Create instance: axi_dwidth_converter_0, and set properties
+  set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
+  set_property -dict [ list \
+   CONFIG.FIFO_MODE {2} \
+   CONFIG.MI_DATA_WIDTH {512} \
+   CONFIG.SI_DATA_WIDTH {128} \
+   CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axi_dwidth_converter_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net S0_AXI_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_dwidth_converter_0/S_AXI]
+  connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_dwidth_converter_0/M_AXI]
+
+  # Create port connections
+  connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_0/m_axi_aclk]
+  connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn]
+  connect_bd_net -net S0_AXI_ACLK_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk]
+  connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

top/x400/ip/axi_inter_1x64_512_bd/Makefile.inc

@@ -0,0 +1,32 @@
+#
+# Copyright 2023 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_AXI_INTER_1X64_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_1x64_512_bd/, \
+axi_inter_1x64_512_bd.tcl \
+)
+
+IP_AXI_INTER_1X64_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x64_512_bd/, \
+axi_inter_1x64_512_bd.tcl \
+)
+
+IP_AXI_INTER_1X64_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x64_512_bd/, \
+axi_inter_1x64_512_bd/axi_inter_1x64_512_bd.bd \
+)
+
+BD_AXI_INTER_1X64_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x64_512_bd/, \
+axi_inter_1x64_512_bd.bd.out \
+axi_inter_1x64_512_bd/axi_inter_1x64_512_bd_ooc.xdc \
+axi_inter_1x64_512_bd/synth/axi_inter_1x64_512_bd.v \
+)
+
+.INTERMEDIATE: IP_AXI_INTER_1X64_512_BD_TRGT
+$(IP_AXI_INTER_1X64_512_BD_SRCS) $(BD_AXI_INTER_1X64_512_BD_OUTS) $(IP_AXI_INTER_1X64_512_BDTCL_SRCS): IP_AXI_INTER_1X64_512_BD_TRGT
+	@:
+
+IP_AXI_INTER_1X64_512_BD_TRGT: $(IP_AXI_INTER_1X64_512_ORIG_SRCS)
+	$(call BUILD_VIVADO_BDTCL,axi_inter_1x64_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)

top/x400/ip/axi_inter_1x64_512_bd/axi_inter_1x64_512_bd.tcl

@@ -0,0 +1,288 @@
+
+################################################################
+# This is a generated script based on design: axi_inter_1x64_512_bd
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source axi_inter_1x64_512_bd_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name axi_inter_1x64_512_bd
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_dwidth_converter:2.1\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.DATA_WIDTH {512} \
+   CONFIG.FREQ_HZ {350000000} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4} \
+   ] $M0_AXI
+
+  set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.DATA_WIDTH {64} \
+   CONFIG.FREQ_HZ {350000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {1} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.MAX_BURST_LENGTH {256} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_READ_THREADS {1} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_THREADS {1} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {1} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $S0_AXI
+
+
+  # Create ports
+  set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
+   CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
+ ] $M0_AXI_ACLK
+  set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
+  set_property -dict [ list \
+   CONFIG.POLARITY {ACTIVE_LOW} \
+ ] $M0_AXI_ARESETN
+  set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {S0_AXI} \
+   CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
+ ] $S0_AXI_ACLK
+  set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
+
+  # Create instance: axi_dwidth_converter_0, and set properties
+  set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
+  set_property -dict [ list \
+   CONFIG.FIFO_MODE {2} \
+   CONFIG.MI_DATA_WIDTH {512} \
+   CONFIG.SI_DATA_WIDTH {64} \
+   CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axi_dwidth_converter_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net S0_AXI_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_dwidth_converter_0/S_AXI]
+  connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_dwidth_converter_0/M_AXI]
+
+  # Create port connections
+  connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_0/m_axi_aclk]
+  connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_0/m_axi_aresetn]
+  connect_bd_net -net S0_AXI_ACLK_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk]
+  connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

top/x400/ip/axi_inter_2x64_512_bd/Makefile.inc

@@ -0,0 +1,32 @@
+#
+# Copyright 2023 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_AXI_INTER_2X64_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_2x64_512_bd/, \
+axi_inter_2x64_512_bd.tcl \
+)
+
+IP_AXI_INTER_2X64_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_512_bd/, \
+axi_inter_2x64_512_bd.tcl \
+)
+
+IP_AXI_INTER_2X64_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_512_bd/, \
+axi_inter_2x64_512_bd/axi_inter_2x64_512_bd.bd \
+)
+
+BD_AXI_INTER_2X64_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_2x64_512_bd/, \
+axi_inter_2x64_512_bd.bd.out \
+axi_inter_2x64_512_bd/axi_inter_2x64_512_bd_ooc.xdc \
+axi_inter_2x64_512_bd/synth/axi_inter_2x64_512_bd.v \
+)
+
+.INTERMEDIATE: IP_AXI_INTER_2X64_512_BD_TRGT
+$(IP_AXI_INTER_2X64_512_BD_SRCS) $(BD_AXI_INTER_2X64_512_BD_OUTS) $(IP_AXI_INTER_2X64_512_BDTCL_SRCS): IP_AXI_INTER_2X64_512_BD_TRGT
+	@:
+
+IP_AXI_INTER_2X64_512_BD_TRGT: $(IP_AXI_INTER_2X64_512_ORIG_SRCS)
+	$(call BUILD_VIVADO_BDTCL,axi_inter_2x64_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)

top/x400/ip/axi_inter_2x64_512_bd/axi_inter_2x64_512_bd.tcl

@@ -0,0 +1,707 @@
+
+################################################################
+# This is a generated script based on design: axi_inter_2x64_512_bd
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source axi_inter_2x64_512_bd_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name axi_inter_2x64_512_bd
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+  # Add USER_COMMENTS on $design_name
+  set_property USER_COMMENTS.comment_0 "Note 1: The ID width of the AXI interconnect (xbar) master changes depending on the axi_interconnect optimization strategy. It will be zero for 'minimize area' and non-zero for 'maximize performance'.
+Note 2: I have explicitly set ID width to 1 on the input ports to match our AXI master and to 4 on the output block to match the DRAM slave." [get_bd_designs $design_name]
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_crossbar:2.1\
+xilinx.com:ip:axi_dwidth_converter:2.1\
+xilinx.com:ip:axi_register_slice:2.1\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set M0_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M0_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.DATA_WIDTH {512} \
+   CONFIG.FREQ_HZ {350000000} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.PROTOCOL {AXI4} \
+   ] $M0_AXI
+
+  set S0_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S0_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.DATA_WIDTH {64} \
+   CONFIG.FREQ_HZ {350000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {1} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.MAX_BURST_LENGTH {256} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_READ_THREADS {1} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_THREADS {1} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {1} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $S0_AXI
+
+  set S1_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S1_AXI ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {32} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.DATA_WIDTH {64} \
+   CONFIG.FREQ_HZ {350000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {1} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.MAX_BURST_LENGTH {256} \
+   CONFIG.NUM_READ_OUTSTANDING {2} \
+   CONFIG.NUM_READ_THREADS {1} \
+   CONFIG.NUM_WRITE_OUTSTANDING {2} \
+   CONFIG.NUM_WRITE_THREADS {1} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {1} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $S1_AXI
+
+
+  # Create ports
+  set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
+   CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
+ ] $M0_AXI_ACLK
+  set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
+  set_property -dict [ list \
+   CONFIG.POLARITY {ACTIVE_LOW} \
+ ] $M0_AXI_ARESETN
+  set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \
+   CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
+ ] $S0_AXI_ACLK
+  set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
+
+  # Create instance: axi_crossbar_0, and set properties
+  set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ]
+  set_property -dict [ list \
+   CONFIG.DATA_WIDTH {256} \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A00_ADDR_WIDTH {0} \
+   CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A00_ADDR_WIDTH {0} \
+   CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A00_ADDR_WIDTH {0} \
+   CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A00_ADDR_WIDTH {0} \
+   CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A00_ADDR_WIDTH {0} \
+   CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A00_ADDR_WIDTH {0} \
+   CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A00_ADDR_WIDTH {0} \
+   CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A00_ADDR_WIDTH {0} \
+   CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A00_ADDR_WIDTH {0} \
+   CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A00_ADDR_WIDTH {0} \
+   CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A00_ADDR_WIDTH {0} \
+   CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A00_ADDR_WIDTH {0} \
+   CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A00_ADDR_WIDTH {0} \
+   CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A00_ADDR_WIDTH {0} \
+   CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A00_ADDR_WIDTH {0} \
+   CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
+   CONFIG.NUM_MI {1} \
+   CONFIG.NUM_SI {2} \
+   CONFIG.S01_BASE_ID {0x00000001} \
+   CONFIG.S02_BASE_ID {0x00000002} \
+   CONFIG.S03_BASE_ID {0x00000003} \
+   CONFIG.S04_BASE_ID {0x00000004} \
+   CONFIG.S05_BASE_ID {0x00000005} \
+   CONFIG.S06_BASE_ID {0x00000006} \
+   CONFIG.S07_BASE_ID {0x00000007} \
+   CONFIG.S08_BASE_ID {0x00000008} \
+   CONFIG.S09_BASE_ID {0x00000009} \
+   CONFIG.S10_BASE_ID {0x0000000a} \
+   CONFIG.S11_BASE_ID {0x0000000b} \
+   CONFIG.S12_BASE_ID {0x0000000c} \
+   CONFIG.S13_BASE_ID {0x0000000d} \
+   CONFIG.S14_BASE_ID {0x0000000e} \
+   CONFIG.S15_BASE_ID {0x0000000f} \
+ ] $axi_crossbar_0
+
+  # Create instance: axi_dwidth_converter_0, and set properties
+  set axi_dwidth_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_0 ]
+  set_property -dict [ list \
+   CONFIG.FIFO_MODE {1} \
+   CONFIG.MI_DATA_WIDTH {256} \
+   CONFIG.SI_DATA_WIDTH {64} \
+   CONFIG.SI_ID_WIDTH {1} \
+   CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axi_dwidth_converter_0
+
+  # Create instance: axi_dwidth_converter_1, and set properties
+  set axi_dwidth_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_1 ]
+  set_property -dict [ list \
+   CONFIG.FIFO_MODE {1} \
+   CONFIG.MI_DATA_WIDTH {256} \
+   CONFIG.SI_DATA_WIDTH {64} \
+   CONFIG.SI_ID_WIDTH {1} \
+   CONFIG.SYNCHRONIZATION_STAGES {3} \
+ ] $axi_dwidth_converter_1
+
+  # Create instance: axi_dwidth_converter_4, and set properties
+  set axi_dwidth_converter_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dwidth_converter:2.1 axi_dwidth_converter_4 ]
+  set_property -dict [ list \
+   CONFIG.ACLK_ASYNC {1} \
+   CONFIG.FIFO_MODE {2} \
+   CONFIG.MI_DATA_WIDTH {512} \
+   CONFIG.SI_DATA_WIDTH {256} \
+   CONFIG.SI_ID_WIDTH {4} \
+   CONFIG.SYNCHRONIZATION_STAGES {2} \
+ ] $axi_dwidth_converter_4
+
+  # Create instance: axi_register_slice_0, and set properties
+  set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
+  set_property -dict [ list \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.REG_AR {1} \
+   CONFIG.REG_AW {1} \
+   CONFIG.REG_B {1} \
+ ] $axi_register_slice_0
+
+  # Create instance: axi_register_slice_1, and set properties
+  set axi_register_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_1 ]
+  set_property -dict [ list \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.REG_AR {1} \
+   CONFIG.REG_AW {1} \
+   CONFIG.REG_B {1} \
+ ] $axi_register_slice_1
+
+  # Create instance: axi_register_slice_4, and set properties
+  set axi_register_slice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_4 ]
+  set_property -dict [ list \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.REG_AR {1} \
+   CONFIG.REG_AW {1} \
+   CONFIG.REG_B {1} \
+ ] $axi_register_slice_4
+
+  # Create instance: axi_register_slice_5, and set properties
+  set axi_register_slice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_5 ]
+  set_property -dict [ list \
+   CONFIG.ID_WIDTH {1} \
+   CONFIG.REG_AR {1} \
+   CONFIG.REG_AW {1} \
+   CONFIG.REG_B {1} \
+ ] $axi_register_slice_5
+
+  # Create instance: axi_register_slice_8, and set properties
+  set axi_register_slice_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_8 ]
+  set_property -dict [ list \
+   CONFIG.ID_WIDTH {4} \
+   CONFIG.REG_AR {1} \
+   CONFIG.REG_AW {1} \
+   CONFIG.REG_B {1} \
+ ] $axi_register_slice_8
+
+  # Create instance: axi_register_slice_9, and set properties
+  set axi_register_slice_9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_9 ]
+  set_property -dict [ list \
+   CONFIG.ID_WIDTH {4} \
+   CONFIG.REG_AR {1} \
+   CONFIG.REG_AW {1} \
+   CONFIG.REG_B {1} \
+ ] $axi_register_slice_9
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net S0_AXI_1 [get_bd_intf_ports S0_AXI] [get_bd_intf_pins axi_register_slice_0/S_AXI]
+  connect_bd_intf_net -intf_net S1_AXI_1 [get_bd_intf_ports S1_AXI] [get_bd_intf_pins axi_register_slice_1/S_AXI]
+  connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_register_slice_8/S_AXI]
+  connect_bd_intf_net -intf_net axi_dwidth_converter_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/M_AXI] [get_bd_intf_pins axi_register_slice_4/S_AXI]
+  connect_bd_intf_net -intf_net axi_dwidth_converter_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/M_AXI] [get_bd_intf_pins axi_register_slice_5/S_AXI]
+  connect_bd_intf_net -intf_net axi_dwidth_converter_4_M_AXI [get_bd_intf_pins axi_dwidth_converter_4/M_AXI] [get_bd_intf_pins axi_register_slice_9/S_AXI]
+  connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_dwidth_converter_0/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
+  connect_bd_intf_net -intf_net axi_register_slice_1_M_AXI [get_bd_intf_pins axi_dwidth_converter_1/S_AXI] [get_bd_intf_pins axi_register_slice_1/M_AXI]
+  connect_bd_intf_net -intf_net axi_register_slice_4_M_AXI [get_bd_intf_pins axi_crossbar_0/S00_AXI] [get_bd_intf_pins axi_register_slice_4/M_AXI]
+  connect_bd_intf_net -intf_net axi_register_slice_5_M_AXI [get_bd_intf_pins axi_crossbar_0/S01_AXI] [get_bd_intf_pins axi_register_slice_5/M_AXI]
+  connect_bd_intf_net -intf_net axi_register_slice_8_M_AXI [get_bd_intf_pins axi_dwidth_converter_4/S_AXI] [get_bd_intf_pins axi_register_slice_8/M_AXI]
+  connect_bd_intf_net -intf_net axi_register_slice_9_M_AXI [get_bd_intf_ports M0_AXI] [get_bd_intf_pins axi_register_slice_9/M_AXI]
+
+  # Create port connections
+  connect_bd_net -net M0_AXI_ACLK_1 [get_bd_ports M0_AXI_ACLK] [get_bd_pins axi_dwidth_converter_4/m_axi_aclk] [get_bd_pins axi_register_slice_9/aclk]
+  connect_bd_net -net M0_AXI_ARESETN_1 [get_bd_ports M0_AXI_ARESETN] [get_bd_pins axi_dwidth_converter_4/m_axi_aresetn] [get_bd_pins axi_register_slice_9/aresetn]
+  connect_bd_net -net S0_AXI_ACLK_1 [get_bd_ports S0_AXI_ACLK] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_dwidth_converter_0/s_axi_aclk] [get_bd_pins axi_dwidth_converter_1/s_axi_aclk] [get_bd_pins axi_dwidth_converter_4/s_axi_aclk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins axi_register_slice_1/aclk] [get_bd_pins axi_register_slice_4/aclk] [get_bd_pins axi_register_slice_5/aclk] [get_bd_pins axi_register_slice_8/aclk]
+  connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_4/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_4/aresetn] [get_bd_pins axi_register_slice_5/aresetn] [get_bd_pins axi_register_slice_8/aresetn]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
+  assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

top/x400/x4xx_dram.v

@@ -18,7 +18,7 @@
 //   ENABLE_DRAM : Set to 1 to include the DRAM IP. Set to 0 to exclude it and
 //                 save resources.
 //   AXI_DWIDTH  : Data width of AXI interface to the DRAM. Can be 64 or 128.
-//   NUM_PORTS   : Number of AXI ports to support. Can be 0, 2, or 4.
+//   NUM_PORTS   : Number of AXI ports to support. Can be 0, 1, 2, or 4.
 //
 
 
@@ -140,6 +140,9 @@ module x4xx_dram #(
 
   if (!(
     (NUM_PORTS == 0                     ) ||
+    (NUM_PORTS == 1 && AXI_DWIDTH ==  64) ||
+    (NUM_PORTS == 1 && AXI_DWIDTH == 128) ||
+    (NUM_PORTS == 2 && AXI_DWIDTH ==  64) ||
     (NUM_PORTS == 2 && AXI_DWIDTH == 128) ||
     (NUM_PORTS == 4 && AXI_DWIDTH ==  64) ||
     (NUM_PORTS == 4 && AXI_DWIDTH == 128)
@@ -213,331 +216,637 @@ module x4xx_dram #(
       wire         dram0_axi_rvalid;
 
       if (AXI_DWIDTH == 64) begin : gen_axi_64
-        axi_inter_4x64_512_bd axi_inter_4x64_512_bd_i (
+        if (NUM_PORTS == 1) begin : gen_axi_1x64
-          .M0_AXI_ACLK    (dram0_ui_clk                                     ),
+          assign dram0_axi_arid = 4'b0;
-          .M0_AXI_ARESETN (~dram0_ui_clk_sync_rst                           ),
+          assign dram0_axi_awid = 4'b0;
-          .M0_AXI_araddr  (dram0_axi_araddr                                 ),
+          assign dram0_axi_bid  = 4'b0;
-          .M0_AXI_arburst (dram0_axi_arburst                                ),
+          assign dram0_axi_rid  = 4'b0;
-          .M0_AXI_arcache (dram0_axi_arcache                                ),
+          axi_inter_1x64_512_bd axi_inter_1x64_512_bd_i (
-          .M0_AXI_arid    (dram0_axi_arid                                   ),
+            .M0_AXI_ACLK    (dram0_ui_clk                                     ),
-          .M0_AXI_arlen   (dram0_axi_arlen                                  ),
+            .M0_AXI_ARESETN (~dram0_ui_clk_sync_rst                           ),
-          .M0_AXI_arlock  (dram0_axi_arlock                                 ),
+            .M0_AXI_araddr  (dram0_axi_araddr                                 ),
-          .M0_AXI_arprot  (dram0_axi_arprot                                 ),
+            .M0_AXI_arburst (dram0_axi_arburst                                ),
-          .M0_AXI_arqos   (dram0_axi_arqos                                  ),
+            .M0_AXI_arcache (dram0_axi_arcache                                ),
-          .M0_AXI_arready (dram0_axi_arready                                ),
+          //.M0_AXI_arid    (dram0_axi_arid                                   ),
-          .M0_AXI_arregion(                                                 ),
+            .M0_AXI_arlen   (dram0_axi_arlen                                  ),
-          .M0_AXI_arsize  (dram0_axi_arsize                                 ),
+            .M0_AXI_arlock  (dram0_axi_arlock                                 ),
-          .M0_AXI_arvalid (dram0_axi_arvalid                                ),
+            .M0_AXI_arprot  (dram0_axi_arprot                                 ),
-          .M0_AXI_awaddr  (dram0_axi_awaddr                                 ),
+            .M0_AXI_arqos   (dram0_axi_arqos                                  ),
-          .M0_AXI_awburst (dram0_axi_awburst                                ),
+            .M0_AXI_arready (dram0_axi_arready                                ),
-          .M0_AXI_awcache (dram0_axi_awcache                                ),
+            .M0_AXI_arregion(                                                 ),
-          .M0_AXI_awid    (dram0_axi_awid                                   ),
+            .M0_AXI_arsize  (dram0_axi_arsize                                 ),
-          .M0_AXI_awlen   (dram0_axi_awlen                                  ),
+            .M0_AXI_arvalid (dram0_axi_arvalid                                ),
-          .M0_AXI_awlock  (dram0_axi_awlock                                 ),
+            .M0_AXI_awaddr  (dram0_axi_awaddr                                 ),
-          .M0_AXI_awprot  (dram0_axi_awprot                                 ),
+            .M0_AXI_awburst (dram0_axi_awburst                                ),
-          .M0_AXI_awqos   (dram0_axi_awqos                                  ),
+            .M0_AXI_awcache (dram0_axi_awcache                                ),
-          .M0_AXI_awready (dram0_axi_awready                                ),
+          //.M0_AXI_awid    (dram0_axi_awid                                   ),
-          .M0_AXI_awregion(                                                 ),
+            .M0_AXI_awlen   (dram0_axi_awlen                                  ),
-          .M0_AXI_awsize  (dram0_axi_awsize                                 ),
+            .M0_AXI_awlock  (dram0_axi_awlock                                 ),
-          .M0_AXI_awvalid (dram0_axi_awvalid                                ),
+            .M0_AXI_awprot  (dram0_axi_awprot                                 ),
-          .M0_AXI_bid     (dram0_axi_bid                                    ),
+            .M0_AXI_awqos   (dram0_axi_awqos                                  ),
-          .M0_AXI_bready  (dram0_axi_bready                                 ),
+            .M0_AXI_awready (dram0_axi_awready                                ),
-          .M0_AXI_bresp   (dram0_axi_bresp                                  ),
+            .M0_AXI_awregion(                                                 ),
-          .M0_AXI_bvalid  (dram0_axi_bvalid                                 ),
+            .M0_AXI_awsize  (dram0_axi_awsize                                 ),
-          .M0_AXI_rdata   (dram0_axi_rdata                                  ),
+            .M0_AXI_awvalid (dram0_axi_awvalid                                ),
-          .M0_AXI_rid     (dram0_axi_rid                                    ),
+          //.M0_AXI_bid     (dram0_axi_bid                                    ),
-          .M0_AXI_rlast   (dram0_axi_rlast                                  ),
+            .M0_AXI_bready  (dram0_axi_bready                                 ),
-          .M0_AXI_rready  (dram0_axi_rready                                 ),
+            .M0_AXI_bresp   (dram0_axi_bresp                                  ),
-          .M0_AXI_rresp   (dram0_axi_rresp                                  ),
+            .M0_AXI_bvalid  (dram0_axi_bvalid                                 ),
-          .M0_AXI_rvalid  (dram0_axi_rvalid                                 ),
+            .M0_AXI_rdata   (dram0_axi_rdata                                  ),
-          .M0_AXI_wdata   (dram0_axi_wdata                                  ),
+          //.M0_AXI_rid     (dram0_axi_rid                                    ),
-          .M0_AXI_wlast   (dram0_axi_wlast                                  ),
+            .M0_AXI_rlast   (dram0_axi_rlast                                  ),
-          .M0_AXI_wready  (dram0_axi_wready                                 ),
+            .M0_AXI_rready  (dram0_axi_rready                                 ),
-          .M0_AXI_wstrb   (dram0_axi_wstrb                                  ),
+            .M0_AXI_rresp   (dram0_axi_rresp                                  ),
-          .M0_AXI_wvalid  (dram0_axi_wvalid                                 ),
+            .M0_AXI_rvalid  (dram0_axi_rvalid                                 ),
-          .S0_AXI_ACLK    (dram_clk                                         ),
+            .M0_AXI_wdata   (dram0_axi_wdata                                  ),
-          .S0_AXI_ARESETN (~dram_rst                                        ),
+            .M0_AXI_wlast   (dram0_axi_wlast                                  ),
-          .S0_AXI_araddr  (dram_axi_araddr  [           2*0 +:           32]),
+            .M0_AXI_wready  (dram0_axi_wready                                 ),
-          .S0_AXI_arburst (dram_axi_arburst [           2*0 +:            2]),
+            .M0_AXI_wstrb   (dram0_axi_wstrb                                  ),
-          .S0_AXI_arcache (dram_axi_arcache [           4*0 +:            4]),
+            .M0_AXI_wvalid  (dram0_axi_wvalid                                 ),
-          .S0_AXI_arid    (dram_axi_arid    [           1*0 +:            1]),
+            .S0_AXI_ACLK    (dram_clk                                         ),
-          .S0_AXI_arlen   (dram_axi_arlen   [           8*0 +:            8]),
+            .S0_AXI_ARESETN (~dram_rst                                        ),
-          .S0_AXI_arlock  (dram_axi_arlock  [           1*0 +:            1]),
+            .S0_AXI_araddr  (dram_axi_araddr  [          32*0 +:           32]),
-          .S0_AXI_arprot  (dram_axi_arprot  [           3*0 +:            3]),
+            .S0_AXI_arburst (dram_axi_arburst [           2*0 +:            2]),
-          .S0_AXI_arqos   (dram_axi_arqos   [           4*0 +:            4]),
+            .S0_AXI_arcache (dram_axi_arcache [           4*0 +:            4]),
-          .S0_AXI_arready (dram_axi_arready [           1*0 +:            1]),
+            .S0_AXI_arid    (dram_axi_arid    [           1*0 +:            1]),
-          .S0_AXI_arregion(dram_axi_arregion[           4*0 +:            4]),
+            .S0_AXI_arlen   (dram_axi_arlen   [           8*0 +:            8]),
-          .S0_AXI_arsize  (dram_axi_arsize  [           3*0 +:            3]),
+            .S0_AXI_arlock  (dram_axi_arlock  [           1*0 +:            1]),
-          .S0_AXI_arvalid (dram_axi_arvalid [           1*0 +:            1]),
+            .S0_AXI_arprot  (dram_axi_arprot  [           3*0 +:            3]),
-          .S0_AXI_awaddr  (dram_axi_awaddr  [           2*0 +:           32]),
+            .S0_AXI_arqos   (dram_axi_arqos   [           4*0 +:            4]),
-          .S0_AXI_awburst (dram_axi_awburst [           2*0 +:            2]),
+            .S0_AXI_arready (dram_axi_arready [           1*0 +:            1]),
-          .S0_AXI_awcache (dram_axi_awcache [           4*0 +:            4]),
+            .S0_AXI_arregion(dram_axi_arregion[           4*0 +:            4]),
-          .S0_AXI_awid    (dram_axi_awid    [           1*0 +:            1]),
+            .S0_AXI_arsize  (dram_axi_arsize  [           3*0 +:            3]),
-          .S0_AXI_awlen   (dram_axi_awlen   [           8*0 +:            8]),
+            .S0_AXI_arvalid (dram_axi_arvalid [           1*0 +:            1]),
-          .S0_AXI_awlock  (dram_axi_awlock  [           1*0 +:            1]),
+            .S0_AXI_awaddr  (dram_axi_awaddr  [          32*0 +:           32]),
-          .S0_AXI_awprot  (dram_axi_awprot  [           3*0 +:            3]),
+            .S0_AXI_awburst (dram_axi_awburst [           2*0 +:            2]),
-          .S0_AXI_awqos   (dram_axi_awqos   [           4*0 +:            4]),
+            .S0_AXI_awcache (dram_axi_awcache [           4*0 +:            4]),
-          .S0_AXI_awready (dram_axi_awready [           1*0 +:            1]),
+            .S0_AXI_awid    (dram_axi_awid    [           1*0 +:            1]),
-          .S0_AXI_awregion(dram_axi_awregion[           4*0 +:            4]),
+            .S0_AXI_awlen   (dram_axi_awlen   [           8*0 +:            8]),
-          .S0_AXI_awsize  (dram_axi_awsize  [           3*0 +:            3]),
+            .S0_AXI_awlock  (dram_axi_awlock  [           1*0 +:            1]),
-          .S0_AXI_awvalid (dram_axi_awvalid [           1*0 +:            1]),
+            .S0_AXI_awprot  (dram_axi_awprot  [           3*0 +:            3]),
-          .S0_AXI_bid     (dram_axi_bid     [           1*0 +:            1]),
+            .S0_AXI_awqos   (dram_axi_awqos   [           4*0 +:            4]),
-          .S0_AXI_bready  (dram_axi_bready  [           1*0 +:            1]),
+            .S0_AXI_awready (dram_axi_awready [           1*0 +:            1]),
-          .S0_AXI_bresp   (dram_axi_bresp   [           2*0 +:            2]),
+            .S0_AXI_awregion(dram_axi_awregion[           4*0 +:            4]),
-          .S0_AXI_bvalid  (dram_axi_bvalid  [           1*0 +:            1]),
+            .S0_AXI_awsize  (dram_axi_awsize  [           3*0 +:            3]),
-          .S0_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_awvalid (dram_axi_awvalid [           1*0 +:            1]),
-          .S0_AXI_rid     (dram_axi_rid     [           1*0 +:            1]),
+            .S0_AXI_bid     (dram_axi_bid     [           1*0 +:            1]),
-          .S0_AXI_rlast   (dram_axi_rlast   [           1*0 +:            1]),
+            .S0_AXI_bready  (dram_axi_bready  [           1*0 +:            1]),
-          .S0_AXI_rready  (dram_axi_rready  [           1*0 +:            1]),
+            .S0_AXI_bresp   (dram_axi_bresp   [           2*0 +:            2]),
-          .S0_AXI_rresp   (dram_axi_rresp   [           2*0 +:            2]),
+            .S0_AXI_bvalid  (dram_axi_bvalid  [           1*0 +:            1]),
-          .S0_AXI_rvalid  (dram_axi_rvalid  [           1*0 +:            1]),
+            .S0_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
-          .S0_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_rid     (dram_axi_rid     [           1*0 +:            1]),
-          .S0_AXI_wlast   (dram_axi_wlast   [           1*0 +:            1]),
+            .S0_AXI_rlast   (dram_axi_rlast   [           1*0 +:            1]),
-          .S0_AXI_wready  (dram_axi_wready  [           1*0 +:            1]),
+            .S0_AXI_rready  (dram_axi_rready  [           1*0 +:            1]),
-          .S0_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*0 +: AXI_DWIDTH/8]),
+            .S0_AXI_rresp   (dram_axi_rresp   [           2*0 +:            2]),
-          .S0_AXI_wvalid  (dram_axi_wvalid  [           1*0 +:            1]),
+            .S0_AXI_rvalid  (dram_axi_rvalid  [           1*0 +:            1]),
-          .S1_AXI_araddr  (dram_axi_araddr  [          32*1 +:           32]),
+            .S0_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
-          .S1_AXI_arburst (dram_axi_arburst [           2*1 +:            2]),
+            .S0_AXI_wlast   (dram_axi_wlast   [           1*0 +:            1]),
-          .S1_AXI_arcache (dram_axi_arcache [           4*1 +:            4]),
+            .S0_AXI_wready  (dram_axi_wready  [           1*0 +:            1]),
-          .S1_AXI_arid    (dram_axi_arid    [           1*1 +:            1]),
+            .S0_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*0 +: AXI_DWIDTH/8]),
-          .S1_AXI_arlen   (dram_axi_arlen   [           8*1 +:            8]),
+            .S0_AXI_wvalid  (dram_axi_wvalid  [           1*0 +:            1])
-          .S1_AXI_arlock  (dram_axi_arlock  [           1*1 +:            1]),
+          );
-          .S1_AXI_arprot  (dram_axi_arprot  [           3*1 +:            3]),
+        end else if (NUM_PORTS == 2) begin : gen_axi_2x64
-          .S1_AXI_arqos   (dram_axi_arqos   [           4*1 +:            4]),
+          axi_inter_2x64_512_bd axi_inter_2x64_512_bd_i (
-          .S1_AXI_arready (dram_axi_arready [           1*1 +:            1]),
+            .M0_AXI_ACLK    (dram0_ui_clk                                     ),
-          .S1_AXI_arregion(dram_axi_arregion[           4*1 +:            4]),
+            .M0_AXI_ARESETN (~dram0_ui_clk_sync_rst                           ),
-          .S1_AXI_arsize  (dram_axi_arsize  [           3*1 +:            3]),
+            .M0_AXI_araddr  (dram0_axi_araddr                                 ),
-          .S1_AXI_arvalid (dram_axi_arvalid [           1*1 +:            1]),
+            .M0_AXI_arburst (dram0_axi_arburst                                ),
-          .S1_AXI_awaddr  (dram_axi_awaddr  [          32*1 +:           32]),
+            .M0_AXI_arcache (dram0_axi_arcache                                ),
-          .S1_AXI_awburst (dram_axi_awburst [           2*1 +:            2]),
+            .M0_AXI_arid    (dram0_axi_arid                                   ),
-          .S1_AXI_awcache (dram_axi_awcache [           4*1 +:            4]),
+            .M0_AXI_arlen   (dram0_axi_arlen                                  ),
-          .S1_AXI_awid    (dram_axi_awid    [           1*1 +:            1]),
+            .M0_AXI_arlock  (dram0_axi_arlock                                 ),
-          .S1_AXI_awlen   (dram_axi_awlen   [           8*1 +:            8]),
+            .M0_AXI_arprot  (dram0_axi_arprot                                 ),
-          .S1_AXI_awlock  (dram_axi_awlock  [           1*1 +:            1]),
+            .M0_AXI_arqos   (dram0_axi_arqos                                  ),
-          .S1_AXI_awprot  (dram_axi_awprot  [           3*1 +:            3]),
+            .M0_AXI_arready (dram0_axi_arready                                ),
-          .S1_AXI_awqos   (dram_axi_awqos   [           4*1 +:            4]),
+            .M0_AXI_arregion(                                                 ),
-          .S1_AXI_awready (dram_axi_awready [           1*1 +:            1]),
+            .M0_AXI_arsize  (dram0_axi_arsize                                 ),
-          .S1_AXI_awregion(dram_axi_awregion[           4*1 +:            4]),
+            .M0_AXI_arvalid (dram0_axi_arvalid                                ),
-          .S1_AXI_awsize  (dram_axi_awsize  [           3*1 +:            3]),
+            .M0_AXI_awaddr  (dram0_axi_awaddr                                 ),
-          .S1_AXI_awvalid (dram_axi_awvalid [           1*1 +:            1]),
+            .M0_AXI_awburst (dram0_axi_awburst                                ),
-          .S1_AXI_bid     (dram_axi_bid     [           1*1 +:            1]),
+            .M0_AXI_awcache (dram0_axi_awcache                                ),
-          .S1_AXI_bready  (dram_axi_bready  [           1*1 +:            1]),
+            .M0_AXI_awid    (dram0_axi_awid                                   ),
-          .S1_AXI_bresp   (dram_axi_bresp   [           2*1 +:            2]),
+            .M0_AXI_awlen   (dram0_axi_awlen                                  ),
-          .S1_AXI_bvalid  (dram_axi_bvalid  [           1*1 +:            1]),
+            .M0_AXI_awlock  (dram0_axi_awlock                                 ),
-          .S1_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .M0_AXI_awprot  (dram0_axi_awprot                                 ),
-          .S1_AXI_rid     (dram_axi_rid     [           1*1 +:            1]),
+            .M0_AXI_awqos   (dram0_axi_awqos                                  ),
-          .S1_AXI_rlast   (dram_axi_rlast   [           1*1 +:            1]),
+            .M0_AXI_awready (dram0_axi_awready                                ),
-          .S1_AXI_rready  (dram_axi_rready  [           1*1 +:            1]),
+            .M0_AXI_awregion(                                                 ),
-          .S1_AXI_rresp   (dram_axi_rresp   [           2*1 +:            2]),
+            .M0_AXI_awsize  (dram0_axi_awsize                                 ),
-          .S1_AXI_rvalid  (dram_axi_rvalid  [           1*1 +:            1]),
+            .M0_AXI_awvalid (dram0_axi_awvalid                                ),
-          .S1_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .M0_AXI_bid     (dram0_axi_bid                                    ),
-          .S1_AXI_wlast   (dram_axi_wlast   [           1*1 +:            1]),
+            .M0_AXI_bready  (dram0_axi_bready                                 ),
-          .S1_AXI_wready  (dram_axi_wready  [           1*1 +:            1]),
+            .M0_AXI_bresp   (dram0_axi_bresp                                  ),
-          .S1_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*1 +: AXI_DWIDTH/8]),
+            .M0_AXI_bvalid  (dram0_axi_bvalid                                 ),
-          .S1_AXI_wvalid  (dram_axi_wvalid  [           1*1 +:            1]),
+            .M0_AXI_rdata   (dram0_axi_rdata                                  ),
-          .S2_AXI_araddr  (dram_axi_araddr  [          32*2 +:           32]),
+            .M0_AXI_rid     (dram0_axi_rid                                    ),
-          .S2_AXI_arburst (dram_axi_arburst [           2*2 +:            2]),
+            .M0_AXI_rlast   (dram0_axi_rlast                                  ),
-          .S2_AXI_arcache (dram_axi_arcache [           4*2 +:            4]),
+            .M0_AXI_rready  (dram0_axi_rready                                 ),
-          .S2_AXI_arid    (dram_axi_arid    [           1*2 +:            1]),
+            .M0_AXI_rresp   (dram0_axi_rresp                                  ),
-          .S2_AXI_arlen   (dram_axi_arlen   [           8*2 +:            8]),
+            .M0_AXI_rvalid  (dram0_axi_rvalid                                 ),
-          .S2_AXI_arlock  (dram_axi_arlock  [           1*2 +:            1]),
+            .M0_AXI_wdata   (dram0_axi_wdata                                  ),
-          .S2_AXI_arprot  (dram_axi_arprot  [           3*2 +:            3]),
+            .M0_AXI_wlast   (dram0_axi_wlast                                  ),
-          .S2_AXI_arqos   (dram_axi_arqos   [           4*2 +:            4]),
+            .M0_AXI_wready  (dram0_axi_wready                                 ),
-          .S2_AXI_arready (dram_axi_arready [           1*2 +:            1]),
+            .M0_AXI_wstrb   (dram0_axi_wstrb                                  ),
-          .S2_AXI_arregion(dram_axi_arregion[           4*2 +:            4]),
+            .M0_AXI_wvalid  (dram0_axi_wvalid                                 ),
-          .S2_AXI_arsize  (dram_axi_arsize  [           3*2 +:            3]),
+            .S0_AXI_ACLK    (dram_clk                                         ),
-          .S2_AXI_arvalid (dram_axi_arvalid [           1*2 +:            1]),
+            .S0_AXI_ARESETN (~dram_rst                                        ),
-          .S2_AXI_awaddr  (dram_axi_awaddr  [          32*2 +:           32]),
+            .S0_AXI_araddr  (dram_axi_araddr  [          32*0 +:           32]),
-          .S2_AXI_awburst (dram_axi_awburst [           2*2 +:            2]),
+            .S0_AXI_arburst (dram_axi_arburst [           2*0 +:            2]),
-          .S2_AXI_awcache (dram_axi_awcache [           4*2 +:            4]),
+            .S0_AXI_arcache (dram_axi_arcache [           4*0 +:            4]),
-          .S2_AXI_awid    (dram_axi_awid    [           1*2 +:            1]),
+            .S0_AXI_arid    (dram_axi_arid    [           1*0 +:            1]),
-          .S2_AXI_awlen   (dram_axi_awlen   [           8*2 +:            8]),
+            .S0_AXI_arlen   (dram_axi_arlen   [           8*0 +:            8]),
-          .S2_AXI_awlock  (dram_axi_awlock  [           1*2 +:            1]),
+            .S0_AXI_arlock  (dram_axi_arlock  [           1*0 +:            1]),
-          .S2_AXI_awprot  (dram_axi_awprot  [           3*2 +:            3]),
+            .S0_AXI_arprot  (dram_axi_arprot  [           3*0 +:            3]),
-          .S2_AXI_awqos   (dram_axi_awqos   [           4*2 +:            4]),
+            .S0_AXI_arqos   (dram_axi_arqos   [           4*0 +:            4]),
-          .S2_AXI_awready (dram_axi_awready [           1*2 +:            1]),
+            .S0_AXI_arready (dram_axi_arready [           1*0 +:            1]),
-          .S2_AXI_awregion(dram_axi_awregion[           4*2 +:            4]),
+            .S0_AXI_arregion(dram_axi_arregion[           4*0 +:            4]),
-          .S2_AXI_awsize  (dram_axi_awsize  [           3*2 +:            3]),
+            .S0_AXI_arsize  (dram_axi_arsize  [           3*0 +:            3]),
-          .S2_AXI_awvalid (dram_axi_awvalid [           1*2 +:            1]),
+            .S0_AXI_arvalid (dram_axi_arvalid [           1*0 +:            1]),
-          .S2_AXI_bid     (dram_axi_bid     [           1*2 +:            1]),
+            .S0_AXI_awaddr  (dram_axi_awaddr  [          32*0 +:           32]),
-          .S2_AXI_bready  (dram_axi_bready  [           1*2 +:            1]),
+            .S0_AXI_awburst (dram_axi_awburst [           2*0 +:            2]),
-          .S2_AXI_bresp   (dram_axi_bresp   [           2*2 +:            2]),
+            .S0_AXI_awcache (dram_axi_awcache [           4*0 +:            4]),
-          .S2_AXI_bvalid  (dram_axi_bvalid  [           1*2 +:            1]),
+            .S0_AXI_awid    (dram_axi_awid    [           1*0 +:            1]),
-          .S2_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*2 +:   AXI_DWIDTH]),
+            .S0_AXI_awlen   (dram_axi_awlen   [           8*0 +:            8]),
-          .S2_AXI_rid     (dram_axi_rid     [           1*2 +:            1]),
+            .S0_AXI_awlock  (dram_axi_awlock  [           1*0 +:            1]),
-          .S2_AXI_rlast   (dram_axi_rlast   [           1*2 +:            1]),
+            .S0_AXI_awprot  (dram_axi_awprot  [           3*0 +:            3]),
-          .S2_AXI_rready  (dram_axi_rready  [           1*2 +:            1]),
+            .S0_AXI_awqos   (dram_axi_awqos   [           4*0 +:            4]),
-          .S2_AXI_rresp   (dram_axi_rresp   [           2*2 +:            2]),
+            .S0_AXI_awready (dram_axi_awready [           1*0 +:            1]),
-          .S2_AXI_rvalid  (dram_axi_rvalid  [           1*2 +:            1]),
+            .S0_AXI_awregion(dram_axi_awregion[           4*0 +:            4]),
-          .S2_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*2 +:   AXI_DWIDTH]),
+            .S0_AXI_awsize  (dram_axi_awsize  [           3*0 +:            3]),
-          .S2_AXI_wlast   (dram_axi_wlast   [           1*2 +:            1]),
+            .S0_AXI_awvalid (dram_axi_awvalid [           1*0 +:            1]),
-          .S2_AXI_wready  (dram_axi_wready  [           1*2 +:            1]),
+            .S0_AXI_bid     (dram_axi_bid     [           1*0 +:            1]),
-          .S2_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*2 +: AXI_DWIDTH/8]),
+            .S0_AXI_bready  (dram_axi_bready  [           1*0 +:            1]),
-          .S2_AXI_wvalid  (dram_axi_wvalid  [           1*2 +:            1]),
+            .S0_AXI_bresp   (dram_axi_bresp   [           2*0 +:            2]),
-          .S3_AXI_araddr  (dram_axi_araddr  [          32*3 +:           32]),
+            .S0_AXI_bvalid  (dram_axi_bvalid  [           1*0 +:            1]),
-          .S3_AXI_arburst (dram_axi_arburst [           2*3 +:            2]),
+            .S0_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
-          .S3_AXI_arcache (dram_axi_arcache [           4*3 +:            4]),
+            .S0_AXI_rid     (dram_axi_rid     [           1*0 +:            1]),
-          .S3_AXI_arid    (dram_axi_arid    [           1*3 +:            1]),
+            .S0_AXI_rlast   (dram_axi_rlast   [           1*0 +:            1]),
-          .S3_AXI_arlen   (dram_axi_arlen   [           8*3 +:            8]),
+            .S0_AXI_rready  (dram_axi_rready  [           1*0 +:            1]),
-          .S3_AXI_arlock  (dram_axi_arlock  [           1*3 +:            1]),
+            .S0_AXI_rresp   (dram_axi_rresp   [           2*0 +:            2]),
-          .S3_AXI_arprot  (dram_axi_arprot  [           3*3 +:            3]),
+            .S0_AXI_rvalid  (dram_axi_rvalid  [           1*0 +:            1]),
-          .S3_AXI_arqos   (dram_axi_arqos   [           4*3 +:            4]),
+            .S0_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
-          .S3_AXI_arready (dram_axi_arready [           1*3 +:            1]),
+            .S0_AXI_wlast   (dram_axi_wlast   [           1*0 +:            1]),
-          .S3_AXI_arregion(dram_axi_arregion[           4*3 +:            4]),
+            .S0_AXI_wready  (dram_axi_wready  [           1*0 +:            1]),
-          .S3_AXI_arsize  (dram_axi_arsize  [           3*3 +:            3]),
+            .S0_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*0 +: AXI_DWIDTH/8]),
-          .S3_AXI_arvalid (dram_axi_arvalid [           1*3 +:            1]),
+            .S0_AXI_wvalid  (dram_axi_wvalid  [           1*0 +:            1]),
-          .S3_AXI_awaddr  (dram_axi_awaddr  [          32*3 +:           32]),
+            .S1_AXI_araddr  (dram_axi_araddr  [          32*1 +:           32]),
-          .S3_AXI_awburst (dram_axi_awburst [           2*3 +:            2]),
+            .S1_AXI_arburst (dram_axi_arburst [           2*1 +:            2]),
-          .S3_AXI_awcache (dram_axi_awcache [           4*3 +:            4]),
+            .S1_AXI_arcache (dram_axi_arcache [           4*1 +:            4]),
-          .S3_AXI_awid    (dram_axi_awid    [           1*3 +:            1]),
+            .S1_AXI_arid    (dram_axi_arid    [           1*1 +:            1]),
-          .S3_AXI_awlen   (dram_axi_awlen   [           8*3 +:            8]),
+            .S1_AXI_arlen   (dram_axi_arlen   [           8*1 +:            8]),
-          .S3_AXI_awlock  (dram_axi_awlock  [           1*3 +:            1]),
+            .S1_AXI_arlock  (dram_axi_arlock  [           1*1 +:            1]),
-          .S3_AXI_awprot  (dram_axi_awprot  [           3*3 +:            3]),
+            .S1_AXI_arprot  (dram_axi_arprot  [           3*1 +:            3]),
-          .S3_AXI_awqos   (dram_axi_awqos   [           4*3 +:            4]),
+            .S1_AXI_arqos   (dram_axi_arqos   [           4*1 +:            4]),
-          .S3_AXI_awready (dram_axi_awready [           1*3 +:            1]),
+            .S1_AXI_arready (dram_axi_arready [           1*1 +:            1]),
-          .S3_AXI_awregion(dram_axi_awregion[           4*3 +:            4]),
+            .S1_AXI_arregion(dram_axi_arregion[           4*1 +:            4]),
-          .S3_AXI_awsize  (dram_axi_awsize  [           3*3 +:            3]),
+            .S1_AXI_arsize  (dram_axi_arsize  [           3*1 +:            3]),
-          .S3_AXI_awvalid (dram_axi_awvalid [           1*3 +:            1]),
+            .S1_AXI_arvalid (dram_axi_arvalid [           1*1 +:            1]),
-          .S3_AXI_bid     (dram_axi_bid     [           1*3 +:            1]),
+            .S1_AXI_awaddr  (dram_axi_awaddr  [          32*1 +:           32]),
-          .S3_AXI_bready  (dram_axi_bready  [           1*3 +:            1]),
+            .S1_AXI_awburst (dram_axi_awburst [           2*1 +:            2]),
-          .S3_AXI_bresp   (dram_axi_bresp   [           2*3 +:            2]),
+            .S1_AXI_awcache (dram_axi_awcache [           4*1 +:            4]),
-          .S3_AXI_bvalid  (dram_axi_bvalid  [           1*3 +:            1]),
+            .S1_AXI_awid    (dram_axi_awid    [           1*1 +:            1]),
-          .S3_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*3 +:   AXI_DWIDTH]),
+            .S1_AXI_awlen   (dram_axi_awlen   [           8*1 +:            8]),
-          .S3_AXI_rid     (dram_axi_rid     [           1*3 +:            1]),
+            .S1_AXI_awlock  (dram_axi_awlock  [           1*1 +:            1]),
-          .S3_AXI_rlast   (dram_axi_rlast   [           1*3 +:            1]),
+            .S1_AXI_awprot  (dram_axi_awprot  [           3*1 +:            3]),
-          .S3_AXI_rready  (dram_axi_rready  [           1*3 +:            1]),
+            .S1_AXI_awqos   (dram_axi_awqos   [           4*1 +:            4]),
-          .S3_AXI_rresp   (dram_axi_rresp   [           2*3 +:            2]),
+            .S1_AXI_awready (dram_axi_awready [           1*1 +:            1]),
-          .S3_AXI_rvalid  (dram_axi_rvalid  [           1*3 +:            1]),
+            .S1_AXI_awregion(dram_axi_awregion[           4*1 +:            4]),
-          .S3_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*3 +:   AXI_DWIDTH]),
+            .S1_AXI_awsize  (dram_axi_awsize  [           3*1 +:            3]),
-          .S3_AXI_wlast   (dram_axi_wlast   [           1*3 +:            1]),
+            .S1_AXI_awvalid (dram_axi_awvalid [           1*1 +:            1]),
-          .S3_AXI_wready  (dram_axi_wready  [           1*3 +:            1]),
+            .S1_AXI_bid     (dram_axi_bid     [           1*1 +:            1]),
-          .S3_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*3 +: AXI_DWIDTH/8]),
+            .S1_AXI_bready  (dram_axi_bready  [           1*1 +:            1]),
-          .S3_AXI_wvalid  (dram_axi_wvalid  [           1*3 +:            1])
+            .S1_AXI_bresp   (dram_axi_bresp   [           2*1 +:            2]),
-        );
+            .S1_AXI_bvalid  (dram_axi_bvalid  [           1*1 +:            1]),
+            .S1_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .S1_AXI_rid     (dram_axi_rid     [           1*1 +:            1]),
+            .S1_AXI_rlast   (dram_axi_rlast   [           1*1 +:            1]),
+            .S1_AXI_rready  (dram_axi_rready  [           1*1 +:            1]),
+            .S1_AXI_rresp   (dram_axi_rresp   [           2*1 +:            2]),
+            .S1_AXI_rvalid  (dram_axi_rvalid  [           1*1 +:            1]),
+            .S1_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .S1_AXI_wlast   (dram_axi_wlast   [           1*1 +:            1]),
+            .S1_AXI_wready  (dram_axi_wready  [           1*1 +:            1]),
+            .S1_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*1 +: AXI_DWIDTH/8]),
+            .S1_AXI_wvalid  (dram_axi_wvalid  [           1*1 +:            1])
+          );
+        end else if (NUM_PORTS == 4) begin : gen_axi_4x64
+          axi_inter_4x64_512_bd axi_inter_4x64_512_bd_i (
+            .M0_AXI_ACLK    (dram0_ui_clk                                     ),
+            .M0_AXI_ARESETN (~dram0_ui_clk_sync_rst                           ),
+            .M0_AXI_araddr  (dram0_axi_araddr                                 ),
+            .M0_AXI_arburst (dram0_axi_arburst                                ),
+            .M0_AXI_arcache (dram0_axi_arcache                                ),
+            .M0_AXI_arid    (dram0_axi_arid                                   ),
+            .M0_AXI_arlen   (dram0_axi_arlen                                  ),
+            .M0_AXI_arlock  (dram0_axi_arlock                                 ),
+            .M0_AXI_arprot  (dram0_axi_arprot                                 ),
+            .M0_AXI_arqos   (dram0_axi_arqos                                  ),
+            .M0_AXI_arready (dram0_axi_arready                                ),
+            .M0_AXI_arregion(                                                 ),
+            .M0_AXI_arsize  (dram0_axi_arsize                                 ),
+            .M0_AXI_arvalid (dram0_axi_arvalid                                ),
+            .M0_AXI_awaddr  (dram0_axi_awaddr                                 ),
+            .M0_AXI_awburst (dram0_axi_awburst                                ),
+            .M0_AXI_awcache (dram0_axi_awcache                                ),
+            .M0_AXI_awid    (dram0_axi_awid                                   ),
+            .M0_AXI_awlen   (dram0_axi_awlen                                  ),
+            .M0_AXI_awlock  (dram0_axi_awlock                                 ),
+            .M0_AXI_awprot  (dram0_axi_awprot                                 ),
+            .M0_AXI_awqos   (dram0_axi_awqos                                  ),
+            .M0_AXI_awready (dram0_axi_awready                                ),
+            .M0_AXI_awregion(                                                 ),
+            .M0_AXI_awsize  (dram0_axi_awsize                                 ),
+            .M0_AXI_awvalid (dram0_axi_awvalid                                ),
+            .M0_AXI_bid     (dram0_axi_bid                                    ),
+            .M0_AXI_bready  (dram0_axi_bready                                 ),
+            .M0_AXI_bresp   (dram0_axi_bresp                                  ),
+            .M0_AXI_bvalid  (dram0_axi_bvalid                                 ),
+            .M0_AXI_rdata   (dram0_axi_rdata                                  ),
+            .M0_AXI_rid     (dram0_axi_rid                                    ),
+            .M0_AXI_rlast   (dram0_axi_rlast                                  ),
+            .M0_AXI_rready  (dram0_axi_rready                                 ),
+            .M0_AXI_rresp   (dram0_axi_rresp                                  ),
+            .M0_AXI_rvalid  (dram0_axi_rvalid                                 ),
+            .M0_AXI_wdata   (dram0_axi_wdata                                  ),
+            .M0_AXI_wlast   (dram0_axi_wlast                                  ),
+            .M0_AXI_wready  (dram0_axi_wready                                 ),
+            .M0_AXI_wstrb   (dram0_axi_wstrb                                  ),
+            .M0_AXI_wvalid  (dram0_axi_wvalid                                 ),
+            .S0_AXI_ACLK    (dram_clk                                         ),
+            .S0_AXI_ARESETN (~dram_rst                                        ),
+            .S0_AXI_araddr  (dram_axi_araddr  [          32*0 +:           32]),
+            .S0_AXI_arburst (dram_axi_arburst [           2*0 +:            2]),
+            .S0_AXI_arcache (dram_axi_arcache [           4*0 +:            4]),
+            .S0_AXI_arid    (dram_axi_arid    [           1*0 +:            1]),
+            .S0_AXI_arlen   (dram_axi_arlen   [           8*0 +:            8]),
+            .S0_AXI_arlock  (dram_axi_arlock  [           1*0 +:            1]),
+            .S0_AXI_arprot  (dram_axi_arprot  [           3*0 +:            3]),
+            .S0_AXI_arqos   (dram_axi_arqos   [           4*0 +:            4]),
+            .S0_AXI_arready (dram_axi_arready [           1*0 +:            1]),
+            .S0_AXI_arregion(dram_axi_arregion[           4*0 +:            4]),
+            .S0_AXI_arsize  (dram_axi_arsize  [           3*0 +:            3]),
+            .S0_AXI_arvalid (dram_axi_arvalid [           1*0 +:            1]),
+            .S0_AXI_awaddr  (dram_axi_awaddr  [          32*0 +:           32]),
+            .S0_AXI_awburst (dram_axi_awburst [           2*0 +:            2]),
+            .S0_AXI_awcache (dram_axi_awcache [           4*0 +:            4]),
+            .S0_AXI_awid    (dram_axi_awid    [           1*0 +:            1]),
+            .S0_AXI_awlen   (dram_axi_awlen   [           8*0 +:            8]),
+            .S0_AXI_awlock  (dram_axi_awlock  [           1*0 +:            1]),
+            .S0_AXI_awprot  (dram_axi_awprot  [           3*0 +:            3]),
+            .S0_AXI_awqos   (dram_axi_awqos   [           4*0 +:            4]),
+            .S0_AXI_awready (dram_axi_awready [           1*0 +:            1]),
+            .S0_AXI_awregion(dram_axi_awregion[           4*0 +:            4]),
+            .S0_AXI_awsize  (dram_axi_awsize  [           3*0 +:            3]),
+            .S0_AXI_awvalid (dram_axi_awvalid [           1*0 +:            1]),
+            .S0_AXI_bid     (dram_axi_bid     [           1*0 +:            1]),
+            .S0_AXI_bready  (dram_axi_bready  [           1*0 +:            1]),
+            .S0_AXI_bresp   (dram_axi_bresp   [           2*0 +:            2]),
+            .S0_AXI_bvalid  (dram_axi_bvalid  [           1*0 +:            1]),
+            .S0_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_rid     (dram_axi_rid     [           1*0 +:            1]),
+            .S0_AXI_rlast   (dram_axi_rlast   [           1*0 +:            1]),
+            .S0_AXI_rready  (dram_axi_rready  [           1*0 +:            1]),
+            .S0_AXI_rresp   (dram_axi_rresp   [           2*0 +:            2]),
+            .S0_AXI_rvalid  (dram_axi_rvalid  [           1*0 +:            1]),
+            .S0_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_wlast   (dram_axi_wlast   [           1*0 +:            1]),
+            .S0_AXI_wready  (dram_axi_wready  [           1*0 +:            1]),
+            .S0_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*0 +: AXI_DWIDTH/8]),
+            .S0_AXI_wvalid  (dram_axi_wvalid  [           1*0 +:            1]),
+            .S1_AXI_araddr  (dram_axi_araddr  [          32*1 +:           32]),
+            .S1_AXI_arburst (dram_axi_arburst [           2*1 +:            2]),
+            .S1_AXI_arcache (dram_axi_arcache [           4*1 +:            4]),
+            .S1_AXI_arid    (dram_axi_arid    [           1*1 +:            1]),
+            .S1_AXI_arlen   (dram_axi_arlen   [           8*1 +:            8]),
+            .S1_AXI_arlock  (dram_axi_arlock  [           1*1 +:            1]),
+            .S1_AXI_arprot  (dram_axi_arprot  [           3*1 +:            3]),
+            .S1_AXI_arqos   (dram_axi_arqos   [           4*1 +:            4]),
+            .S1_AXI_arready (dram_axi_arready [           1*1 +:            1]),
+            .S1_AXI_arregion(dram_axi_arregion[           4*1 +:            4]),
+            .S1_AXI_arsize  (dram_axi_arsize  [           3*1 +:            3]),
+            .S1_AXI_arvalid (dram_axi_arvalid [           1*1 +:            1]),
+            .S1_AXI_awaddr  (dram_axi_awaddr  [          32*1 +:           32]),
+            .S1_AXI_awburst (dram_axi_awburst [           2*1 +:            2]),
+            .S1_AXI_awcache (dram_axi_awcache [           4*1 +:            4]),
+            .S1_AXI_awid    (dram_axi_awid    [           1*1 +:            1]),
+            .S1_AXI_awlen   (dram_axi_awlen   [           8*1 +:            8]),
+            .S1_AXI_awlock  (dram_axi_awlock  [           1*1 +:            1]),
+            .S1_AXI_awprot  (dram_axi_awprot  [           3*1 +:            3]),
+            .S1_AXI_awqos   (dram_axi_awqos   [           4*1 +:            4]),
+            .S1_AXI_awready (dram_axi_awready [           1*1 +:            1]),
+            .S1_AXI_awregion(dram_axi_awregion[           4*1 +:            4]),
+            .S1_AXI_awsize  (dram_axi_awsize  [           3*1 +:            3]),
+            .S1_AXI_awvalid (dram_axi_awvalid [           1*1 +:            1]),
+            .S1_AXI_bid     (dram_axi_bid     [           1*1 +:            1]),
+            .S1_AXI_bready  (dram_axi_bready  [           1*1 +:            1]),
+            .S1_AXI_bresp   (dram_axi_bresp   [           2*1 +:            2]),
+            .S1_AXI_bvalid  (dram_axi_bvalid  [           1*1 +:            1]),
+            .S1_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .S1_AXI_rid     (dram_axi_rid     [           1*1 +:            1]),
+            .S1_AXI_rlast   (dram_axi_rlast   [           1*1 +:            1]),
+            .S1_AXI_rready  (dram_axi_rready  [           1*1 +:            1]),
+            .S1_AXI_rresp   (dram_axi_rresp   [           2*1 +:            2]),
+            .S1_AXI_rvalid  (dram_axi_rvalid  [           1*1 +:            1]),
+            .S1_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .S1_AXI_wlast   (dram_axi_wlast   [           1*1 +:            1]),
+            .S1_AXI_wready  (dram_axi_wready  [           1*1 +:            1]),
+            .S1_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*1 +: AXI_DWIDTH/8]),
+            .S1_AXI_wvalid  (dram_axi_wvalid  [           1*1 +:            1]),
+            .S2_AXI_araddr  (dram_axi_araddr  [          32*2 +:           32]),
+            .S2_AXI_arburst (dram_axi_arburst [           2*2 +:            2]),
+            .S2_AXI_arcache (dram_axi_arcache [           4*2 +:            4]),
+            .S2_AXI_arid    (dram_axi_arid    [           1*2 +:            1]),
+            .S2_AXI_arlen   (dram_axi_arlen   [           8*2 +:            8]),
+            .S2_AXI_arlock  (dram_axi_arlock  [           1*2 +:            1]),
+            .S2_AXI_arprot  (dram_axi_arprot  [           3*2 +:            3]),
+            .S2_AXI_arqos   (dram_axi_arqos   [           4*2 +:            4]),
+            .S2_AXI_arready (dram_axi_arready [           1*2 +:            1]),
+            .S2_AXI_arregion(dram_axi_arregion[           4*2 +:            4]),
+            .S2_AXI_arsize  (dram_axi_arsize  [           3*2 +:            3]),
+            .S2_AXI_arvalid (dram_axi_arvalid [           1*2 +:            1]),
+            .S2_AXI_awaddr  (dram_axi_awaddr  [          32*2 +:           32]),
+            .S2_AXI_awburst (dram_axi_awburst [           2*2 +:            2]),
+            .S2_AXI_awcache (dram_axi_awcache [           4*2 +:            4]),
+            .S2_AXI_awid    (dram_axi_awid    [           1*2 +:            1]),
+            .S2_AXI_awlen   (dram_axi_awlen   [           8*2 +:            8]),
+            .S2_AXI_awlock  (dram_axi_awlock  [           1*2 +:            1]),
+            .S2_AXI_awprot  (dram_axi_awprot  [           3*2 +:            3]),
+            .S2_AXI_awqos   (dram_axi_awqos   [           4*2 +:            4]),
+            .S2_AXI_awready (dram_axi_awready [           1*2 +:            1]),
+            .S2_AXI_awregion(dram_axi_awregion[           4*2 +:            4]),
+            .S2_AXI_awsize  (dram_axi_awsize  [           3*2 +:            3]),
+            .S2_AXI_awvalid (dram_axi_awvalid [           1*2 +:            1]),
+            .S2_AXI_bid     (dram_axi_bid     [           1*2 +:            1]),
+            .S2_AXI_bready  (dram_axi_bready  [           1*2 +:            1]),
+            .S2_AXI_bresp   (dram_axi_bresp   [           2*2 +:            2]),
+            .S2_AXI_bvalid  (dram_axi_bvalid  [           1*2 +:            1]),
+            .S2_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*2 +:   AXI_DWIDTH]),
+            .S2_AXI_rid     (dram_axi_rid     [           1*2 +:            1]),
+            .S2_AXI_rlast   (dram_axi_rlast   [           1*2 +:            1]),
+            .S2_AXI_rready  (dram_axi_rready  [           1*2 +:            1]),
+            .S2_AXI_rresp   (dram_axi_rresp   [           2*2 +:            2]),
+            .S2_AXI_rvalid  (dram_axi_rvalid  [           1*2 +:            1]),
+            .S2_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*2 +:   AXI_DWIDTH]),
+            .S2_AXI_wlast   (dram_axi_wlast   [           1*2 +:            1]),
+            .S2_AXI_wready  (dram_axi_wready  [           1*2 +:            1]),
+            .S2_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*2 +: AXI_DWIDTH/8]),
+            .S2_AXI_wvalid  (dram_axi_wvalid  [           1*2 +:            1]),
+            .S3_AXI_araddr  (dram_axi_araddr  [          32*3 +:           32]),
+            .S3_AXI_arburst (dram_axi_arburst [           2*3 +:            2]),
+            .S3_AXI_arcache (dram_axi_arcache [           4*3 +:            4]),
+            .S3_AXI_arid    (dram_axi_arid    [           1*3 +:            1]),
+            .S3_AXI_arlen   (dram_axi_arlen   [           8*3 +:            8]),
+            .S3_AXI_arlock  (dram_axi_arlock  [           1*3 +:            1]),
+            .S3_AXI_arprot  (dram_axi_arprot  [           3*3 +:            3]),
+            .S3_AXI_arqos   (dram_axi_arqos   [           4*3 +:            4]),
+            .S3_AXI_arready (dram_axi_arready [           1*3 +:            1]),
+            .S3_AXI_arregion(dram_axi_arregion[           4*3 +:            4]),
+            .S3_AXI_arsize  (dram_axi_arsize  [           3*3 +:            3]),
+            .S3_AXI_arvalid (dram_axi_arvalid [           1*3 +:            1]),
+            .S3_AXI_awaddr  (dram_axi_awaddr  [          32*3 +:           32]),
+            .S3_AXI_awburst (dram_axi_awburst [           2*3 +:            2]),
+            .S3_AXI_awcache (dram_axi_awcache [           4*3 +:            4]),
+            .S3_AXI_awid    (dram_axi_awid    [           1*3 +:            1]),
+            .S3_AXI_awlen   (dram_axi_awlen   [           8*3 +:            8]),
+            .S3_AXI_awlock  (dram_axi_awlock  [           1*3 +:            1]),
+            .S3_AXI_awprot  (dram_axi_awprot  [           3*3 +:            3]),
+            .S3_AXI_awqos   (dram_axi_awqos   [           4*3 +:            4]),
+            .S3_AXI_awready (dram_axi_awready [           1*3 +:            1]),
+            .S3_AXI_awregion(dram_axi_awregion[           4*3 +:            4]),
+            .S3_AXI_awsize  (dram_axi_awsize  [           3*3 +:            3]),
+            .S3_AXI_awvalid (dram_axi_awvalid [           1*3 +:            1]),
+            .S3_AXI_bid     (dram_axi_bid     [           1*3 +:            1]),
+            .S3_AXI_bready  (dram_axi_bready  [           1*3 +:            1]),
+            .S3_AXI_bresp   (dram_axi_bresp   [           2*3 +:            2]),
+            .S3_AXI_bvalid  (dram_axi_bvalid  [           1*3 +:            1]),
+            .S3_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*3 +:   AXI_DWIDTH]),
+            .S3_AXI_rid     (dram_axi_rid     [           1*3 +:            1]),
+            .S3_AXI_rlast   (dram_axi_rlast   [           1*3 +:            1]),
+            .S3_AXI_rready  (dram_axi_rready  [           1*3 +:            1]),
+            .S3_AXI_rresp   (dram_axi_rresp   [           2*3 +:            2]),
+            .S3_AXI_rvalid  (dram_axi_rvalid  [           1*3 +:            1]),
+            .S3_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*3 +:   AXI_DWIDTH]),
+            .S3_AXI_wlast   (dram_axi_wlast   [           1*3 +:            1]),
+            .S3_AXI_wready  (dram_axi_wready  [           1*3 +:            1]),
+            .S3_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*3 +: AXI_DWIDTH/8]),
+            .S3_AXI_wvalid  (dram_axi_wvalid  [           1*3 +:            1])
+          );
+        end
       end else begin : gen_axi_128
-        axi_inter_2x128_512_bd axi_inter_2x128_512_bd_i (
+        if (NUM_PORTS == 1) begin : gen_1x128
-          .M0_AXI_ACLK    (dram0_ui_clk                                     ),
+          assign dram0_axi_arid = 4'b0;
-          .M0_AXI_ARESETN (~dram0_ui_clk_sync_rst                           ),
+          assign dram0_axi_awid = 4'b0;
-          .M0_AXI_araddr  (dram0_axi_araddr                                 ),
+          assign dram0_axi_bid  = 4'b0;
-          .M0_AXI_arburst (dram0_axi_arburst                                ),
+          assign dram0_axi_rid  = 4'b0;
-          .M0_AXI_arcache (dram0_axi_arcache                                ),
+          axi_inter_1x128_512_bd axi_inter_1x128_512_bd_i (
-          .M0_AXI_arid    (dram0_axi_arid                                   ),
+            .M0_AXI_ACLK    (dram0_ui_clk                                     ),
-          .M0_AXI_arlen   (dram0_axi_arlen                                  ),
+            .M0_AXI_ARESETN (~dram0_ui_clk_sync_rst                           ),
-          .M0_AXI_arlock  (dram0_axi_arlock                                 ),
+            .M0_AXI_araddr  (dram0_axi_araddr                                 ),
-          .M0_AXI_arprot  (dram0_axi_arprot                                 ),
+            .M0_AXI_arburst (dram0_axi_arburst                                ),
-          .M0_AXI_arqos   (dram0_axi_arqos                                  ),
+            .M0_AXI_arcache (dram0_axi_arcache                                ),
-          .M0_AXI_arready (dram0_axi_arready                                ),
+          //.M0_AXI_arid    (dram0_axi_arid                                   ),
-          .M0_AXI_arregion(                                                 ),
+            .M0_AXI_arlen   (dram0_axi_arlen                                  ),
-          .M0_AXI_arsize  (dram0_axi_arsize                                 ),
+            .M0_AXI_arlock  (dram0_axi_arlock                                 ),
-          .M0_AXI_arvalid (dram0_axi_arvalid                                ),
+            .M0_AXI_arprot  (dram0_axi_arprot                                 ),
-          .M0_AXI_awaddr  (dram0_axi_awaddr                                 ),
+            .M0_AXI_arqos   (dram0_axi_arqos                                  ),
-          .M0_AXI_awburst (dram0_axi_awburst                                ),
+            .M0_AXI_arready (dram0_axi_arready                                ),
-          .M0_AXI_awcache (dram0_axi_awcache                                ),
+            .M0_AXI_arregion(                                                 ),
-          .M0_AXI_awid    (dram0_axi_awid                                   ),
+            .M0_AXI_arsize  (dram0_axi_arsize                                 ),
-          .M0_AXI_awlen   (dram0_axi_awlen                                  ),
+            .M0_AXI_arvalid (dram0_axi_arvalid                                ),
-          .M0_AXI_awlock  (dram0_axi_awlock                                 ),
+            .M0_AXI_awaddr  (dram0_axi_awaddr                                 ),
-          .M0_AXI_awprot  (dram0_axi_awprot                                 ),
+            .M0_AXI_awburst (dram0_axi_awburst                                ),
-          .M0_AXI_awqos   (dram0_axi_awqos                                  ),
+            .M0_AXI_awcache (dram0_axi_awcache                                ),
-          .M0_AXI_awready (dram0_axi_awready                                ),
+          //.M0_AXI_awid    (dram0_axi_awid                                   ),
-          .M0_AXI_awregion(                                                 ),
+            .M0_AXI_awlen   (dram0_axi_awlen                                  ),
-          .M0_AXI_awsize  (dram0_axi_awsize                                 ),
+            .M0_AXI_awlock  (dram0_axi_awlock                                 ),
-          .M0_AXI_awvalid (dram0_axi_awvalid                                ),
+            .M0_AXI_awprot  (dram0_axi_awprot                                 ),
-          .M0_AXI_bid     (dram0_axi_bid                                    ),
+            .M0_AXI_awqos   (dram0_axi_awqos                                  ),
-          .M0_AXI_bready  (dram0_axi_bready                                 ),
+            .M0_AXI_awready (dram0_axi_awready                                ),
-          .M0_AXI_bresp   (dram0_axi_bresp                                  ),
+            .M0_AXI_awregion(                                                 ),
-          .M0_AXI_bvalid  (dram0_axi_bvalid                                 ),
+            .M0_AXI_awsize  (dram0_axi_awsize                                 ),
-          .M0_AXI_rdata   (dram0_axi_rdata                                  ),
+            .M0_AXI_awvalid (dram0_axi_awvalid                                ),
-          .M0_AXI_rid     (dram0_axi_rid                                    ),
+          //.M0_AXI_bid     (dram0_axi_bid                                    ),
-          .M0_AXI_rlast   (dram0_axi_rlast                                  ),
+            .M0_AXI_bready  (dram0_axi_bready                                 ),
-          .M0_AXI_rready  (dram0_axi_rready                                 ),
+            .M0_AXI_bresp   (dram0_axi_bresp                                  ),
-          .M0_AXI_rresp   (dram0_axi_rresp                                  ),
+            .M0_AXI_bvalid  (dram0_axi_bvalid                                 ),
-          .M0_AXI_rvalid  (dram0_axi_rvalid                                 ),
+            .M0_AXI_rdata   (dram0_axi_rdata                                  ),
-          .M0_AXI_wdata   (dram0_axi_wdata                                  ),
+          //.M0_AXI_rid     (dram0_axi_rid                                    ),
-          .M0_AXI_wlast   (dram0_axi_wlast                                  ),
+            .M0_AXI_rlast   (dram0_axi_rlast                                  ),
-          .M0_AXI_wready  (dram0_axi_wready                                 ),
+            .M0_AXI_rready  (dram0_axi_rready                                 ),
-          .M0_AXI_wstrb   (dram0_axi_wstrb                                  ),
+            .M0_AXI_rresp   (dram0_axi_rresp                                  ),
-          .M0_AXI_wvalid  (dram0_axi_wvalid                                 ),
+            .M0_AXI_rvalid  (dram0_axi_rvalid                                 ),
-          .S0_AXI_ACLK    (dram_clk                                         ),
+            .M0_AXI_wdata   (dram0_axi_wdata                                  ),
-          .S0_AXI_ARESETN (~dram_rst                                        ),
+            .M0_AXI_wlast   (dram0_axi_wlast                                  ),
-          .S0_AXI_araddr  (dram_axi_araddr  [          32*0 +:           32]),
+            .M0_AXI_wready  (dram0_axi_wready                                 ),
-          .S0_AXI_arburst (dram_axi_arburst [           2*0 +:            2]),
+            .M0_AXI_wstrb   (dram0_axi_wstrb                                  ),
-          .S0_AXI_arcache (dram_axi_arcache [           4*0 +:            4]),
+            .M0_AXI_wvalid  (dram0_axi_wvalid                                 ),
-          .S0_AXI_arid    (dram_axi_arid    [           1*0 +:            1]),
+            .S0_AXI_ACLK    (dram_clk                                         ),
-          .S0_AXI_arlen   (dram_axi_arlen   [           8*0 +:            8]),
+            .S0_AXI_ARESETN (~dram_rst                                        ),
-          .S0_AXI_arlock  (dram_axi_arlock  [           1*0 +:            1]),
+            .S0_AXI_araddr  (dram_axi_araddr  [          32*0 +:           32]),
-          .S0_AXI_arprot  (dram_axi_arprot  [           3*0 +:            3]),
+            .S0_AXI_arburst (dram_axi_arburst [           2*0 +:            2]),
-          .S0_AXI_arqos   (dram_axi_arqos   [           4*0 +:            4]),
+            .S0_AXI_arcache (dram_axi_arcache [           4*0 +:            4]),
-          .S0_AXI_arready (dram_axi_arready [           1*0 +:            1]),
+            .S0_AXI_arid    (dram_axi_arid    [           1*0 +:            1]),
-          .S0_AXI_arregion(dram_axi_arregion[           4*0 +:            4]),
+            .S0_AXI_arlen   (dram_axi_arlen   [           8*0 +:            8]),
-          .S0_AXI_arsize  (dram_axi_arsize  [           3*0 +:            3]),
+            .S0_AXI_arlock  (dram_axi_arlock  [           1*0 +:            1]),
-          .S0_AXI_arvalid (dram_axi_arvalid [           1*0 +:            1]),
+            .S0_AXI_arprot  (dram_axi_arprot  [           3*0 +:            3]),
-          .S0_AXI_awaddr  (dram_axi_awaddr  [          32*0 +:           32]),
+            .S0_AXI_arqos   (dram_axi_arqos   [           4*0 +:            4]),
-          .S0_AXI_awburst (dram_axi_awburst [           2*0 +:            2]),
+            .S0_AXI_arready (dram_axi_arready [           1*0 +:            1]),
-          .S0_AXI_awcache (dram_axi_awcache [           4*0 +:            4]),
+            .S0_AXI_arregion(dram_axi_arregion[           4*0 +:            4]),
-          .S0_AXI_awid    (dram_axi_awid    [           1*0 +:            1]),
+            .S0_AXI_arsize  (dram_axi_arsize  [           3*0 +:            3]),
-          .S0_AXI_awlen   (dram_axi_awlen   [           8*0 +:            8]),
+            .S0_AXI_arvalid (dram_axi_arvalid [           1*0 +:            1]),
-          .S0_AXI_awlock  (dram_axi_awlock  [           1*0 +:            1]),
+            .S0_AXI_awaddr  (dram_axi_awaddr  [          32*0 +:           32]),
-          .S0_AXI_awprot  (dram_axi_awprot  [           3*0 +:            3]),
+            .S0_AXI_awburst (dram_axi_awburst [           2*0 +:            2]),
-          .S0_AXI_awqos   (dram_axi_awqos   [           4*0 +:            4]),
+            .S0_AXI_awcache (dram_axi_awcache [           4*0 +:            4]),
-          .S0_AXI_awready (dram_axi_awready [           1*0 +:            1]),
+            .S0_AXI_awid    (dram_axi_awid    [           1*0 +:            1]),
-          .S0_AXI_awregion(dram_axi_awregion[           4*0 +:            4]),
+            .S0_AXI_awlen   (dram_axi_awlen   [           8*0 +:            8]),
-          .S0_AXI_awsize  (dram_axi_awsize  [           3*0 +:            3]),
+            .S0_AXI_awlock  (dram_axi_awlock  [           1*0 +:            1]),
-          .S0_AXI_awvalid (dram_axi_awvalid [           1*0 +:            1]),
+            .S0_AXI_awprot  (dram_axi_awprot  [           3*0 +:            3]),
-          .S0_AXI_bid     (dram_axi_bid     [           1*0 +:            1]),
+            .S0_AXI_awqos   (dram_axi_awqos   [           4*0 +:            4]),
-          .S0_AXI_bready  (dram_axi_bready  [           1*0 +:            1]),
+            .S0_AXI_awready (dram_axi_awready [           1*0 +:            1]),
-          .S0_AXI_bresp   (dram_axi_bresp   [           2*0 +:            2]),
+            .S0_AXI_awregion(dram_axi_awregion[           4*0 +:            4]),
-          .S0_AXI_bvalid  (dram_axi_bvalid  [           1*0 +:            1]),
+            .S0_AXI_awsize  (dram_axi_awsize  [           3*0 +:            3]),
-          .S0_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_awvalid (dram_axi_awvalid [           1*0 +:            1]),
-          .S0_AXI_rid     (dram_axi_rid     [           1*0 +:            1]),
+            .S0_AXI_bid     (dram_axi_bid     [           1*0 +:            1]),
-          .S0_AXI_rlast   (dram_axi_rlast   [           1*0 +:            1]),
+            .S0_AXI_bready  (dram_axi_bready  [           1*0 +:            1]),
-          .S0_AXI_rready  (dram_axi_rready  [           1*0 +:            1]),
+            .S0_AXI_bresp   (dram_axi_bresp   [           2*0 +:            2]),
-          .S0_AXI_rresp   (dram_axi_rresp   [           2*0 +:            2]),
+            .S0_AXI_bvalid  (dram_axi_bvalid  [           1*0 +:            1]),
-          .S0_AXI_rvalid  (dram_axi_rvalid  [           1*0 +:            1]),
+            .S0_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
-          .S0_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_rid     (dram_axi_rid     [           1*0 +:            1]),
-          .S0_AXI_wlast   (dram_axi_wlast   [           1*0 +:            1]),
+            .S0_AXI_rlast   (dram_axi_rlast   [           1*0 +:            1]),
-          .S0_AXI_wready  (dram_axi_wready  [           1*0 +:            1]),
+            .S0_AXI_rready  (dram_axi_rready  [           1*0 +:            1]),
-          .S0_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*0 +: AXI_DWIDTH/8]),
+            .S0_AXI_rresp   (dram_axi_rresp   [           2*0 +:            2]),
-          .S0_AXI_wvalid  (dram_axi_wvalid  [           1*0 +:            1]),
+            .S0_AXI_rvalid  (dram_axi_rvalid  [           1*0 +:            1]),
-          .S1_AXI_araddr  (dram_axi_araddr  [          32*1 +:           32]),
+            .S0_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
-          .S1_AXI_arburst (dram_axi_arburst [           2*1 +:            2]),
+            .S0_AXI_wlast   (dram_axi_wlast   [           1*0 +:            1]),
-          .S1_AXI_arcache (dram_axi_arcache [           4*1 +:            4]),
+            .S0_AXI_wready  (dram_axi_wready  [           1*0 +:            1]),
-          .S1_AXI_arid    (dram_axi_arid    [           1*1 +:            1]),
+            .S0_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*0 +: AXI_DWIDTH/8]),
-          .S1_AXI_arlen   (dram_axi_arlen   [           8*1 +:            8]),
+            .S0_AXI_wvalid  (dram_axi_wvalid  [           1*0 +:            1])
-          .S1_AXI_arlock  (dram_axi_arlock  [           1*1 +:            1]),
+          );
-          .S1_AXI_arprot  (dram_axi_arprot  [           3*1 +:            3]),
+        end else begin : gen_2x128
-          .S1_AXI_arqos   (dram_axi_arqos   [           4*1 +:            4]),
+          axi_inter_2x128_512_bd axi_inter_2x128_512_bd_i (
-          .S1_AXI_arready (dram_axi_arready [           1*1 +:            1]),
+            .M0_AXI_ACLK    (dram0_ui_clk                                     ),
-          .S1_AXI_arregion(dram_axi_arregion[           4*1 +:            4]),
+            .M0_AXI_ARESETN (~dram0_ui_clk_sync_rst                           ),
-          .S1_AXI_arsize  (dram_axi_arsize  [           3*1 +:            3]),
+            .M0_AXI_araddr  (dram0_axi_araddr                                 ),
-          .S1_AXI_arvalid (dram_axi_arvalid [           1*1 +:            1]),
+            .M0_AXI_arburst (dram0_axi_arburst                                ),
-          .S1_AXI_awaddr  (dram_axi_awaddr  [          32*1 +:           32]),
+            .M0_AXI_arcache (dram0_axi_arcache                                ),
-          .S1_AXI_awburst (dram_axi_awburst [           2*1 +:            2]),
+            .M0_AXI_arid    (dram0_axi_arid                                   ),
-          .S1_AXI_awcache (dram_axi_awcache [           4*1 +:            4]),
+            .M0_AXI_arlen   (dram0_axi_arlen                                  ),
-          .S1_AXI_awid    (dram_axi_awid    [           1*1 +:            1]),
+            .M0_AXI_arlock  (dram0_axi_arlock                                 ),
-          .S1_AXI_awlen   (dram_axi_awlen   [           8*1 +:            8]),
+            .M0_AXI_arprot  (dram0_axi_arprot                                 ),
-          .S1_AXI_awlock  (dram_axi_awlock  [           1*1 +:            1]),
+            .M0_AXI_arqos   (dram0_axi_arqos                                  ),
-          .S1_AXI_awprot  (dram_axi_awprot  [           3*1 +:            3]),
+            .M0_AXI_arready (dram0_axi_arready                                ),
-          .S1_AXI_awqos   (dram_axi_awqos   [           4*1 +:            4]),
+            .M0_AXI_arregion(                                                 ),
-          .S1_AXI_awready (dram_axi_awready [           1*1 +:            1]),
+            .M0_AXI_arsize  (dram0_axi_arsize                                 ),
-          .S1_AXI_awregion(dram_axi_awregion[           4*1 +:            4]),
+            .M0_AXI_arvalid (dram0_axi_arvalid                                ),
-          .S1_AXI_awsize  (dram_axi_awsize  [           3*1 +:            3]),
+            .M0_AXI_awaddr  (dram0_axi_awaddr                                 ),
-          .S1_AXI_awvalid (dram_axi_awvalid [           1*1 +:            1]),
+            .M0_AXI_awburst (dram0_axi_awburst                                ),
-          .S1_AXI_bid     (dram_axi_bid     [           1*1 +:            1]),
+            .M0_AXI_awcache (dram0_axi_awcache                                ),
-          .S1_AXI_bready  (dram_axi_bready  [           1*1 +:            1]),
+            .M0_AXI_awid    (dram0_axi_awid                                   ),
-          .S1_AXI_bresp   (dram_axi_bresp   [           2*1 +:            2]),
+            .M0_AXI_awlen   (dram0_axi_awlen                                  ),
-          .S1_AXI_bvalid  (dram_axi_bvalid  [           1*1 +:            1]),
+            .M0_AXI_awlock  (dram0_axi_awlock                                 ),
-          .S1_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .M0_AXI_awprot  (dram0_axi_awprot                                 ),
-          .S1_AXI_rid     (dram_axi_rid     [           1*1 +:            1]),
+            .M0_AXI_awqos   (dram0_axi_awqos                                  ),
-          .S1_AXI_rlast   (dram_axi_rlast   [           1*1 +:            1]),
+            .M0_AXI_awready (dram0_axi_awready                                ),
-          .S1_AXI_rready  (dram_axi_rready  [           1*1 +:            1]),
+            .M0_AXI_awregion(                                                 ),
-          .S1_AXI_rresp   (dram_axi_rresp   [           2*1 +:            2]),
+            .M0_AXI_awsize  (dram0_axi_awsize                                 ),
-          .S1_AXI_rvalid  (dram_axi_rvalid  [           1*1 +:            1]),
+            .M0_AXI_awvalid (dram0_axi_awvalid                                ),
-          .S1_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .M0_AXI_bid     (dram0_axi_bid                                    ),
-          .S1_AXI_wlast   (dram_axi_wlast   [           1*1 +:            1]),
+            .M0_AXI_bready  (dram0_axi_bready                                 ),
-          .S1_AXI_wready  (dram_axi_wready  [           1*1 +:            1]),
+            .M0_AXI_bresp   (dram0_axi_bresp                                  ),
-          .S1_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*1 +: AXI_DWIDTH/8]),
+            .M0_AXI_bvalid  (dram0_axi_bvalid                                 ),
-          .S1_AXI_wvalid  (dram_axi_wvalid  [           1*1 +:            1])
+            .M0_AXI_rdata   (dram0_axi_rdata                                  ),
-        );
+            .M0_AXI_rid     (dram0_axi_rid                                    ),
+            .M0_AXI_rlast   (dram0_axi_rlast                                  ),
+            .M0_AXI_rready  (dram0_axi_rready                                 ),
+            .M0_AXI_rresp   (dram0_axi_rresp                                  ),
+            .M0_AXI_rvalid  (dram0_axi_rvalid                                 ),
+            .M0_AXI_wdata   (dram0_axi_wdata                                  ),
+            .M0_AXI_wlast   (dram0_axi_wlast                                  ),
+            .M0_AXI_wready  (dram0_axi_wready                                 ),
+            .M0_AXI_wstrb   (dram0_axi_wstrb                                  ),
+            .M0_AXI_wvalid  (dram0_axi_wvalid                                 ),
+            .S0_AXI_ACLK    (dram_clk                                         ),
+            .S0_AXI_ARESETN (~dram_rst                                        ),
+            .S0_AXI_araddr  (dram_axi_araddr  [          32*0 +:           32]),
+            .S0_AXI_arburst (dram_axi_arburst [           2*0 +:            2]),
+            .S0_AXI_arcache (dram_axi_arcache [           4*0 +:            4]),
+            .S0_AXI_arid    (dram_axi_arid    [           1*0 +:            1]),
+            .S0_AXI_arlen   (dram_axi_arlen   [           8*0 +:            8]),
+            .S0_AXI_arlock  (dram_axi_arlock  [           1*0 +:            1]),
+            .S0_AXI_arprot  (dram_axi_arprot  [           3*0 +:            3]),
+            .S0_AXI_arqos   (dram_axi_arqos   [           4*0 +:            4]),
+            .S0_AXI_arready (dram_axi_arready [           1*0 +:            1]),
+            .S0_AXI_arregion(dram_axi_arregion[           4*0 +:            4]),
+            .S0_AXI_arsize  (dram_axi_arsize  [           3*0 +:            3]),
+            .S0_AXI_arvalid (dram_axi_arvalid [           1*0 +:            1]),
+            .S0_AXI_awaddr  (dram_axi_awaddr  [          32*0 +:           32]),
+            .S0_AXI_awburst (dram_axi_awburst [           2*0 +:            2]),
+            .S0_AXI_awcache (dram_axi_awcache [           4*0 +:            4]),
+            .S0_AXI_awid    (dram_axi_awid    [           1*0 +:            1]),
+            .S0_AXI_awlen   (dram_axi_awlen   [           8*0 +:            8]),
+            .S0_AXI_awlock  (dram_axi_awlock  [           1*0 +:            1]),
+            .S0_AXI_awprot  (dram_axi_awprot  [           3*0 +:            3]),
+            .S0_AXI_awqos   (dram_axi_awqos   [           4*0 +:            4]),
+            .S0_AXI_awready (dram_axi_awready [           1*0 +:            1]),
+            .S0_AXI_awregion(dram_axi_awregion[           4*0 +:            4]),
+            .S0_AXI_awsize  (dram_axi_awsize  [           3*0 +:            3]),
+            .S0_AXI_awvalid (dram_axi_awvalid [           1*0 +:            1]),
+            .S0_AXI_bid     (dram_axi_bid     [           1*0 +:            1]),
+            .S0_AXI_bready  (dram_axi_bready  [           1*0 +:            1]),
+            .S0_AXI_bresp   (dram_axi_bresp   [           2*0 +:            2]),
+            .S0_AXI_bvalid  (dram_axi_bvalid  [           1*0 +:            1]),
+            .S0_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_rid     (dram_axi_rid     [           1*0 +:            1]),
+            .S0_AXI_rlast   (dram_axi_rlast   [           1*0 +:            1]),
+            .S0_AXI_rready  (dram_axi_rready  [           1*0 +:            1]),
+            .S0_AXI_rresp   (dram_axi_rresp   [           2*0 +:            2]),
+            .S0_AXI_rvalid  (dram_axi_rvalid  [           1*0 +:            1]),
+            .S0_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*0 +:   AXI_DWIDTH]),
+            .S0_AXI_wlast   (dram_axi_wlast   [           1*0 +:            1]),
+            .S0_AXI_wready  (dram_axi_wready  [           1*0 +:            1]),
+            .S0_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*0 +: AXI_DWIDTH/8]),
+            .S0_AXI_wvalid  (dram_axi_wvalid  [           1*0 +:            1]),
+            .S1_AXI_araddr  (dram_axi_araddr  [          32*1 +:           32]),
+            .S1_AXI_arburst (dram_axi_arburst [           2*1 +:            2]),
+            .S1_AXI_arcache (dram_axi_arcache [           4*1 +:            4]),
+            .S1_AXI_arid    (dram_axi_arid    [           1*1 +:            1]),
+            .S1_AXI_arlen   (dram_axi_arlen   [           8*1 +:            8]),
+            .S1_AXI_arlock  (dram_axi_arlock  [           1*1 +:            1]),
+            .S1_AXI_arprot  (dram_axi_arprot  [           3*1 +:            3]),
+            .S1_AXI_arqos   (dram_axi_arqos   [           4*1 +:            4]),
+            .S1_AXI_arready (dram_axi_arready [           1*1 +:            1]),
+            .S1_AXI_arregion(dram_axi_arregion[           4*1 +:            4]),
+            .S1_AXI_arsize  (dram_axi_arsize  [           3*1 +:            3]),
+            .S1_AXI_arvalid (dram_axi_arvalid [           1*1 +:            1]),
+            .S1_AXI_awaddr  (dram_axi_awaddr  [          32*1 +:           32]),
+            .S1_AXI_awburst (dram_axi_awburst [           2*1 +:            2]),
+            .S1_AXI_awcache (dram_axi_awcache [           4*1 +:            4]),
+            .S1_AXI_awid    (dram_axi_awid    [           1*1 +:            1]),
+            .S1_AXI_awlen   (dram_axi_awlen   [           8*1 +:            8]),
+            .S1_AXI_awlock  (dram_axi_awlock  [           1*1 +:            1]),
+            .S1_AXI_awprot  (dram_axi_awprot  [           3*1 +:            3]),
+            .S1_AXI_awqos   (dram_axi_awqos   [           4*1 +:            4]),
+            .S1_AXI_awready (dram_axi_awready [           1*1 +:            1]),
+            .S1_AXI_awregion(dram_axi_awregion[           4*1 +:            4]),
+            .S1_AXI_awsize  (dram_axi_awsize  [           3*1 +:            3]),
+            .S1_AXI_awvalid (dram_axi_awvalid [           1*1 +:            1]),
+            .S1_AXI_bid     (dram_axi_bid     [           1*1 +:            1]),
+            .S1_AXI_bready  (dram_axi_bready  [           1*1 +:            1]),
+            .S1_AXI_bresp   (dram_axi_bresp   [           2*1 +:            2]),
+            .S1_AXI_bvalid  (dram_axi_bvalid  [           1*1 +:            1]),
+            .S1_AXI_rdata   (dram_axi_rdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .S1_AXI_rid     (dram_axi_rid     [           1*1 +:            1]),
+            .S1_AXI_rlast   (dram_axi_rlast   [           1*1 +:            1]),
+            .S1_AXI_rready  (dram_axi_rready  [           1*1 +:            1]),
+            .S1_AXI_rresp   (dram_axi_rresp   [           2*1 +:            2]),
+            .S1_AXI_rvalid  (dram_axi_rvalid  [           1*1 +:            1]),
+            .S1_AXI_wdata   (dram_axi_wdata   [  AXI_DWIDTH*1 +:   AXI_DWIDTH]),
+            .S1_AXI_wlast   (dram_axi_wlast   [           1*1 +:            1]),
+            .S1_AXI_wready  (dram_axi_wready  [           1*1 +:            1]),
+            .S1_AXI_wstrb   (dram_axi_wstrb   [AXI_DWIDTH/8*1 +: AXI_DWIDTH/8]),
+            .S1_AXI_wvalid  (dram_axi_wvalid  [           1*1 +:            1])
+          );
+        end
       end
 
       ddr4_64bits ddr4_64bits_i (