Max Köhler
ec70691e84
The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags. Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
83 lines
3.7 KiB
Verilog
83 lines
3.7 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: handshake
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// Description:
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// Implements clock domain crossing for data from one clock domain
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// to another independent of the relative clock frequencies or phases of
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// clk_a and clk_b.
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//
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// Once a handshake is triggered it cannot be aborted. A proper design needs to
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// apply reset to the target clock domain downstream module to make sure a
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// valid_b pulse does not cause any issues.
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//
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// Input Behavior:
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// ┌┐┌┐┌┐┌┐┋ ┋┌┐┌┐┌┐┌┐┌┐┋ ┋┌┐┌┐┌┐┌┐┌┐┌┐┌┐
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// clk_a ┘└┘└┘└┘└┋ ┋┘└┘└┘└┘└┘└┋ ┋┘└┘└┘└┘└┘└┘└┘└
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// ┌─┐ ┋ ┋ ┌─┐ ┋ ┋
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// valid_a ──┘ └───┋ ┋────┘ └───┋ ┋──────────────
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// ▄▄┬─┬▄▄▄┋ ┋▄▄▄▄┬─┬▄▄▄┋ ┋▄▄▄▄▄▄▄▄▄▄▄▄▄▄
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// data_a ▀▀┴─┴▀▀▀┋ ┋▀▀▀▀┴─┴▀▀▀┋ ┋▀▀▀▀▀▀▀▀▀▀▀▀▀▀
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// ┌───┋ ┋────┐ ┌───┋ ┋────────┐
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// busy_a ────┘ ┋ ┋ └─┘ ┋ ┋ └─────
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//
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//
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// Output Behavior:
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// ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┋ ┋ ┌─┐ ┌─┐ ┌─┐ ┌─┐
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// clk_b ─┘ └─┘ └─┘ └─┘ └─┋ ┋─┘ └─┘ └─┘ └─┘ └─
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// ┌───┐ ┋ ┋ ┌───┐
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// valid_b ─────────┘ └───┋ ┋─────┘ └───────
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// ▄▄▄▄▄▄▄▄▄┬───┬▄▄▄┋ ┋▄▄▄▄▄┬───┬▄▄▄▄▄▄▄
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// data_b ▀▀▀▀▀▀▀▀▀┴───┴▀▀▀┋ ┋▀▀▀▀▀┴───┴▀▀▀▀▀▀▀
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///////////////////////////////////////////////////////////////////////////////
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module handshake #(
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parameter WIDTH = 32 // data width
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) (
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// source clock domain
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input wire clk_a,
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input wire rst_a,
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input wire valid_a, // trigger handshake on rising edge
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input wire [WIDTH-1:0] data_a,
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output wire busy_a,
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// target clock domain
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input wire clk_b,
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output wire valid_b,
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output wire [WIDTH-1:0] data_b
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);
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// Handling of the handshaking between the two clock domains. The reset does
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// not delete a pulse, which is already triggered!
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pulse_synchronizer #(
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.MODE("PULSE"), .STAGES(4)
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) push_sync_inst (
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.clk_a(clk_a), .rst_a(rst_a), .pulse_a(valid_a), .busy_a(busy_a),
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.clk_b(clk_b), .pulse_b(valid_b)
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);
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// Capture the data aligned with triggering the handshake.
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reg [WIDTH-1:0] data_a_lcl;
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always @(posedge clk_a) begin
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if (valid_a & ~busy_a) begin
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data_a_lcl <= data_a;
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end
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end
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// Transfer data with timing exception. Data is captured upfront and kept
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// stable in clk_a domain. As there are more synchronizer stages in the
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// pulse_synchronizer the data in these 2 stage synchronizer is stable once
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// the valid_b pulse arrives in clk_b domain. 2 stages are used to resolve
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// meta-stability. Reset is not needed on the data path as it is controlled by
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// the valid signals.
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synchronizer #(
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.WIDTH(WIDTH), .STAGES(2), .INITIAL_VAL({WIDTH {1'b0}}), .FALSE_PATH_TO_IN(1)
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) data_sync_inst (
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.clk(clk_b), .rst(1'b0), .in(data_a_lcl), .out(data_b)
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);
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endmodule
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