Martin Braun
613444b39b
This allows the BSP files that instantiate radio blocks to pass in clock indices. Original-commit: c669d16a0a500de6b10b0817c7ebbd175818f2cb
591 lines
24 KiB
Verilog
591 lines
24 KiB
Verilog
//
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// Copyright 2019 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_block_radio
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//
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// Description: This is the top-level file for the RFNoC radio block.
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//
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// Parameters:
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//
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// THIS_PORTID : CTRL port ID to which this block is connected
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// CHDR_W : CHDR AXI-Stream data bus width
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// NIPC : Number of radio samples per radio clock cycle
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// ITEM_W : Radio sample width
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// NUM_PORTS : Number of radio channels (RX/TX pairs)
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// MTU : Maximum transmission unit (i.e., maximum packet size)
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// in CHDR words is 2**MTU.
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// PERIPH_BASE_ADDR : CTRL port peripheral window base address
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// PERIPH_ADDR_W : CTRL port peripheral address space = 2**PERIPH_ADDR_W
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//
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module rfnoc_block_radio #(
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parameter THIS_PORTID = 0,
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parameter CHDR_W = 64,
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parameter NIPC = 1,
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parameter ITEM_W = 32,
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parameter NUM_PORTS = 2,
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parameter MTU = 10,
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parameter PERIPH_BASE_ADDR = 20'h80000,
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parameter PERIPH_ADDR_W = 19,
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parameter [5:0] CTRL_CLK_IDX = 6'h3F,
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parameter [5:0] TB_CLK_IDX = 6'h3F
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) (
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//---------------------------------------------------------------------------
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// AXIS CHDR Port
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//---------------------------------------------------------------------------
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input wire rfnoc_chdr_clk,
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// CHDR inputs from framework
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input wire [CHDR_W*NUM_PORTS-1:0] s_rfnoc_chdr_tdata,
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input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
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input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
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output wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tready,
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// CHDR outputs to framework
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output wire [CHDR_W*NUM_PORTS-1:0] m_rfnoc_chdr_tdata,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
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input wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tready,
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// Backend interface
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input wire [511:0] rfnoc_core_config,
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output wire [511:0] rfnoc_core_status,
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//---------------------------------------------------------------------------
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// AXIS CTRL Port
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//---------------------------------------------------------------------------
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input wire rfnoc_ctrl_clk,
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// CTRL port requests from framework
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input wire [31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// CTRL port requests to framework
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output wire [31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready,
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//---------------------------------------------------------------------------
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// CTRL Port Peripheral Interface
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//---------------------------------------------------------------------------
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_ctrlport_req_has_time,
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output wire [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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//---------------------------------------------------------------------------
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// Radio Interface
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//---------------------------------------------------------------------------
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input wire radio_clk,
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// Timekeeper interface
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input wire [63:0] radio_time,
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// Radio Rx interface
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input wire [(ITEM_W*NIPC)*NUM_PORTS-1:0] radio_rx_data,
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input wire [ NUM_PORTS-1:0] radio_rx_stb,
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output wire [ NUM_PORTS-1:0] radio_rx_running,
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// Radio Tx interface
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output wire [(ITEM_W*NIPC)*NUM_PORTS-1:0] radio_tx_data,
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input wire [ NUM_PORTS-1:0] radio_tx_stb,
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output wire [ NUM_PORTS-1:0] radio_tx_running
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);
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`include "rfnoc_block_radio_regs.vh"
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`include "../../core/rfnoc_axis_ctrl_utils.vh"
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localparam RADIO_W = NIPC*ITEM_W;
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// Radio Tx data stream
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wire [RADIO_W*NUM_PORTS-1:0] axis_tx_tdata;
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wire [ NUM_PORTS-1:0] axis_tx_tlast;
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wire [ NUM_PORTS-1:0] axis_tx_tvalid;
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wire [ NUM_PORTS-1:0] axis_tx_tready;
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wire [ 64*NUM_PORTS-1:0] axis_tx_ttimestamp;
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wire [ NUM_PORTS-1:0] axis_tx_thas_time;
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wire [ NUM_PORTS-1:0] axis_tx_teob;
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// Radio Rx data stream
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wire [RADIO_W*NUM_PORTS-1:0] axis_rx_tdata;
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wire [ NUM_PORTS-1:0] axis_rx_tlast;
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wire [ NUM_PORTS-1:0] axis_rx_tvalid;
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wire [ NUM_PORTS-1:0] axis_rx_tready;
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wire [ 64*NUM_PORTS-1:0] axis_rx_ttimestamp;
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wire [ NUM_PORTS-1:0] axis_rx_thas_time;
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wire [ NUM_PORTS-1:0] axis_rx_teob;
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// Control port signals used for register access (NoC shell masters user logic)
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wire ctrlport_reg_req_wr;
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wire ctrlport_reg_req_rd;
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wire [19:0] ctrlport_reg_req_addr;
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wire ctrlport_reg_has_time;
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wire [63:0] ctrlport_reg_time;
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wire [31:0] ctrlport_reg_req_data;
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wire [ 3:0] ctrlport_reg_req_byte_en;
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wire [31:0] ctrlport_reg_resp_data;
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wire ctrlport_reg_resp_ack;
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wire [ 1:0] ctrlport_reg_resp_status;
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// Control port signals used for error reporting (user logic masters to NoC shell)
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wire ctrlport_err_req_wr;
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wire [19:0] ctrlport_err_req_addr;
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wire [ 9:0] ctrlport_err_req_portid;
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wire [15:0] ctrlport_err_req_rem_epid;
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wire [ 9:0] ctrlport_err_req_rem_portid;
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wire [31:0] ctrlport_err_req_data;
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wire ctrlport_err_req_has_time;
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wire [63:0] ctrlport_err_req_time;
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wire ctrlport_err_resp_ack;
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//---------------------------------------------------------------------------
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// NoC Shell
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//---------------------------------------------------------------------------
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wire radio_rst;
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noc_shell_radio #(
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.THIS_PORTID (THIS_PORTID),
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.CHDR_W (CHDR_W),
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.CTRL_CLK_IDX (CTRL_CLK_IDX),
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.TB_CLK_IDX (TB_CLK_IDX),
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.MTU (MTU),
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.NUM_PORTS (NUM_PORTS),
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.NIPC (NIPC),
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.ITEM_W (ITEM_W)
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) noc_shell_radio_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.radio_clk (radio_clk),
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.rfnoc_chdr_rst (),
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.rfnoc_ctrl_rst (),
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.radio_rst (radio_rst),
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
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.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
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.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
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.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
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.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
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.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
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.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
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.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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.ctrlport_clk (),
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.ctrlport_rst (),
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.m_ctrlport_req_wr (ctrlport_reg_req_wr),
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.m_ctrlport_req_rd (ctrlport_reg_req_rd),
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.m_ctrlport_req_addr (ctrlport_reg_req_addr),
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.m_ctrlport_req_data (ctrlport_reg_req_data),
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.m_ctrlport_req_byte_en (ctrlport_reg_req_byte_en),
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.m_ctrlport_req_has_time (ctrlport_reg_has_time),
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.m_ctrlport_req_time (ctrlport_reg_time),
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.m_ctrlport_resp_ack (ctrlport_reg_resp_ack),
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.m_ctrlport_resp_status (ctrlport_reg_resp_status),
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.m_ctrlport_resp_data (ctrlport_reg_resp_data),
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.s_ctrlport_req_wr (ctrlport_err_req_wr),
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.s_ctrlport_req_rd (1'b0),
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.s_ctrlport_req_addr (ctrlport_err_req_addr),
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.s_ctrlport_req_portid (ctrlport_err_req_portid),
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.s_ctrlport_req_rem_epid (ctrlport_err_req_rem_epid),
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.s_ctrlport_req_rem_portid (ctrlport_err_req_rem_portid),
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.s_ctrlport_req_data (ctrlport_err_req_data),
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.s_ctrlport_req_byte_en (4'hF),
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.s_ctrlport_req_has_time (ctrlport_err_req_has_time),
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.s_ctrlport_req_time (ctrlport_err_req_time),
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.s_ctrlport_resp_ack (ctrlport_err_resp_ack),
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.s_ctrlport_resp_status (),
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.s_ctrlport_resp_data (),
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.axis_data_clk (),
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.axis_data_rst (),
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.m_in_axis_tdata (axis_tx_tdata),
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.m_in_axis_tkeep (), // Radio only transmits full words
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.m_in_axis_tlast (axis_tx_tlast),
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.m_in_axis_tvalid (axis_tx_tvalid),
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.m_in_axis_tready (axis_tx_tready),
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.m_in_axis_ttimestamp (axis_tx_ttimestamp),
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.m_in_axis_thas_time (axis_tx_thas_time),
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.m_in_axis_tlength (),
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.m_in_axis_teov (),
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.m_in_axis_teob (axis_tx_teob),
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.s_out_axis_tdata (axis_rx_tdata),
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.s_out_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}), // Radio only receives full words
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.s_out_axis_tlast (axis_rx_tlast),
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.s_out_axis_tvalid (axis_rx_tvalid),
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.s_out_axis_tready (axis_rx_tready),
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.s_out_axis_ttimestamp (axis_rx_ttimestamp),
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.s_out_axis_thas_time (axis_rx_thas_time),
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.s_out_axis_teov ({NUM_PORTS{1'b0}}),
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.s_out_axis_teob (axis_rx_teob)
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);
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//---------------------------------------------------------------------------
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// Decode Control Port Addresses
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//---------------------------------------------------------------------------
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//
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// This block splits the NoC shell's single master control port interface
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// into three masters, connected to the shared registers, radio cores, and
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// the external CTRL port peripheral interface. The responses from each of
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// these are merged into a single response and sent back to the NoC shell.
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//
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//---------------------------------------------------------------------------
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wire ctrlport_shared_req_wr;
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wire ctrlport_shared_req_rd;
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wire [19:0] ctrlport_shared_req_addr;
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wire [31:0] ctrlport_shared_req_data;
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wire [ 3:0] ctrlport_shared_req_byte_en;
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wire ctrlport_shared_req_has_time;
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wire [63:0] ctrlport_shared_req_time;
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wire ctrlport_shared_resp_ack;
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wire [31:0] ctrlport_shared_resp_data;
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wire ctrlport_core_req_wr;
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wire ctrlport_core_req_rd;
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wire [19:0] ctrlport_core_req_addr;
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wire [31:0] ctrlport_core_req_data;
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wire [ 3:0] ctrlport_core_req_byte_en;
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wire ctrlport_core_req_has_time;
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wire [63:0] ctrlport_core_req_time;
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wire ctrlport_core_resp_ack;
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wire [31:0] ctrlport_core_resp_data;
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ctrlport_decoder_param #(
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.NUM_SLAVES (3),
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.PORT_BASE ({PERIPH_BASE_ADDR, RADIO_BASE_ADDR, SHARED_BASE_ADDR}),
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.PORT_ADDR_W({PERIPH_ADDR_W, RADIO_ADDR_W + $clog2(NUM_PORTS), SHARED_ADDR_W})
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) ctrlport_decoder_param_i (
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.ctrlport_clk (radio_clk),
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.ctrlport_rst (radio_rst),
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.s_ctrlport_req_wr (ctrlport_reg_req_wr),
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.s_ctrlport_req_rd (ctrlport_reg_req_rd),
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.s_ctrlport_req_addr (ctrlport_reg_req_addr),
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.s_ctrlport_req_data (ctrlport_reg_req_data),
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.s_ctrlport_req_byte_en (ctrlport_reg_req_byte_en),
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.s_ctrlport_req_has_time (ctrlport_reg_has_time),
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.s_ctrlport_req_time (ctrlport_reg_time),
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.s_ctrlport_resp_ack (ctrlport_reg_resp_ack),
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.s_ctrlport_resp_status (ctrlport_reg_resp_status),
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.s_ctrlport_resp_data (ctrlport_reg_resp_data),
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.m_ctrlport_req_wr ({m_ctrlport_req_wr,
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ctrlport_core_req_wr,
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ctrlport_shared_req_wr}),
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.m_ctrlport_req_rd ({m_ctrlport_req_rd,
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ctrlport_core_req_rd,
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ctrlport_shared_req_rd}),
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.m_ctrlport_req_addr ({m_ctrlport_req_addr,
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ctrlport_core_req_addr,
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ctrlport_shared_req_addr}),
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.m_ctrlport_req_data ({m_ctrlport_req_data,
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ctrlport_core_req_data,
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ctrlport_shared_req_data}),
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.m_ctrlport_req_byte_en ({m_ctrlport_req_byte_en,
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ctrlport_core_req_byte_en,
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ctrlport_shared_req_byte_en}),
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.m_ctrlport_req_has_time ({m_ctrlport_req_has_time,
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ctrlport_core_req_has_time,
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ctrlport_shared_req_has_time}),
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.m_ctrlport_req_time ({m_ctrlport_req_time,
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ctrlport_core_req_time,
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ctrlport_shared_req_time}),
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.m_ctrlport_resp_ack ({m_ctrlport_resp_ack,
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ctrlport_core_resp_ack,
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ctrlport_shared_resp_ack}),
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.m_ctrlport_resp_status ({m_ctrlport_resp_status,
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2'b00,
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2'b00}),
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.m_ctrlport_resp_data ({m_ctrlport_resp_data,
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ctrlport_core_resp_data,
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ctrlport_shared_resp_data
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})
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);
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//---------------------------------------------------------------------------
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// Split Radio Control Port Interfaces
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//---------------------------------------------------------------------------
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wire [ NUM_PORTS-1:0] ctrlport_radios_req_wr;
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wire [ NUM_PORTS-1:0] ctrlport_radios_req_rd;
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wire [20*NUM_PORTS-1:0] ctrlport_radios_req_addr;
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wire [32*NUM_PORTS-1:0] ctrlport_radios_req_data;
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wire [ NUM_PORTS-1:0] ctrlport_radios_resp_ack;
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wire [32*NUM_PORTS-1:0] ctrlport_radios_resp_data;
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ctrlport_decoder #(
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.NUM_SLAVES (NUM_PORTS),
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.BASE_ADDR (0),
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.SLAVE_ADDR_W (RADIO_ADDR_W)
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) ctrlport_decoder_i (
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.ctrlport_clk (radio_clk),
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.ctrlport_rst (radio_rst),
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.s_ctrlport_req_wr (ctrlport_core_req_wr),
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.s_ctrlport_req_rd (ctrlport_core_req_rd),
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.s_ctrlport_req_addr (ctrlport_core_req_addr),
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.s_ctrlport_req_data (ctrlport_core_req_data),
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.s_ctrlport_req_byte_en (4'b0),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'b0),
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.s_ctrlport_resp_ack (ctrlport_core_resp_ack),
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.s_ctrlport_resp_status (),
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.s_ctrlport_resp_data (ctrlport_core_resp_data),
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.m_ctrlport_req_wr (ctrlport_radios_req_wr),
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.m_ctrlport_req_rd (ctrlport_radios_req_rd),
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.m_ctrlport_req_addr (ctrlport_radios_req_addr),
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.m_ctrlport_req_data (ctrlport_radios_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (ctrlport_radios_resp_ack),
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.m_ctrlport_resp_status ({NUM_PORTS{2'b00}}),
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.m_ctrlport_resp_data (ctrlport_radios_resp_data)
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);
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//---------------------------------------------------------------------------
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// Merge Control Port Interfaces
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//---------------------------------------------------------------------------
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//
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// This block merges the master control port interfaces of all radio_cores
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// into a single master for the NoC shell.
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//
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//---------------------------------------------------------------------------
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wire [ NUM_PORTS-1:0] ctrlport_err_radio_req_wr;
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wire [20*NUM_PORTS-1:0] ctrlport_err_radio_req_addr;
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wire [10*NUM_PORTS-1:0] ctrlport_err_radio_req_portid;
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wire [16*NUM_PORTS-1:0] ctrlport_err_radio_req_rem_epid;
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wire [10*NUM_PORTS-1:0] ctrlport_err_radio_req_rem_portid;
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wire [32*NUM_PORTS-1:0] ctrlport_err_radio_req_data;
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wire [ NUM_PORTS-1:0] ctrlport_err_radio_req_has_time;
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wire [64*NUM_PORTS-1:0] ctrlport_err_radio_req_time;
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wire [ NUM_PORTS-1:0] ctrlport_err_radio_resp_ack;
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ctrlport_combiner #(
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.NUM_MASTERS (NUM_PORTS),
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.PRIORITY (0)
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) ctrlport_combiner_i (
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.ctrlport_clk (radio_clk),
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.ctrlport_rst (radio_rst),
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.s_ctrlport_req_wr (ctrlport_err_radio_req_wr),
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.s_ctrlport_req_rd ({NUM_PORTS{1'b0}}),
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|
.s_ctrlport_req_addr (ctrlport_err_radio_req_addr),
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|
.s_ctrlport_req_portid (ctrlport_err_radio_req_portid),
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|
.s_ctrlport_req_rem_epid (ctrlport_err_radio_req_rem_epid),
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|
.s_ctrlport_req_rem_portid (ctrlport_err_radio_req_rem_portid),
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|
.s_ctrlport_req_data (ctrlport_err_radio_req_data),
|
|
.s_ctrlport_req_byte_en ({4*NUM_PORTS{1'b1}}),
|
|
.s_ctrlport_req_has_time (ctrlport_err_radio_req_has_time),
|
|
.s_ctrlport_req_time (ctrlport_err_radio_req_time),
|
|
.s_ctrlport_resp_ack (ctrlport_err_radio_resp_ack),
|
|
.s_ctrlport_resp_status (),
|
|
.s_ctrlport_resp_data (),
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|
.m_ctrlport_req_wr (ctrlport_err_req_wr),
|
|
.m_ctrlport_req_rd (),
|
|
.m_ctrlport_req_addr (ctrlport_err_req_addr),
|
|
.m_ctrlport_req_portid (ctrlport_err_req_portid),
|
|
.m_ctrlport_req_rem_epid (ctrlport_err_req_rem_epid),
|
|
.m_ctrlport_req_rem_portid (ctrlport_err_req_rem_portid),
|
|
.m_ctrlport_req_data (ctrlport_err_req_data),
|
|
.m_ctrlport_req_byte_en (),
|
|
.m_ctrlport_req_has_time (ctrlport_err_req_has_time),
|
|
.m_ctrlport_req_time (ctrlport_err_req_time),
|
|
.m_ctrlport_resp_ack (ctrlport_err_resp_ack),
|
|
.m_ctrlport_resp_status (2'b0),
|
|
.m_ctrlport_resp_data (32'b0)
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Control Port Timer for Shared Registers
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// Makes sure shared register access waits for the time if one is provided.
|
|
// This allows timed command packets to be tested by reading the time using
|
|
// command packets with a time supplied.
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire ctrlport_timer_req_rd;
|
|
wire [19:0] ctrlport_timer_req_addr;
|
|
reg ctrlport_timer_resp_ack = 1'b0;
|
|
reg [31:0] ctrlport_timer_resp_data = 0;
|
|
|
|
ctrlport_timer ctrlport_timer_i (
|
|
// Clocks and Resets
|
|
.clk(radio_clk),
|
|
.rst(radio_rst),
|
|
// Timestamp (synchronous to radio_clk)
|
|
.time_now(radio_time),
|
|
.time_now_stb(1'b1),
|
|
.time_ignore_bits($clog2(NIPC)),
|
|
// Control Port Master (Request)
|
|
.s_ctrlport_req_wr(ctrlport_shared_req_wr),
|
|
.s_ctrlport_req_rd(ctrlport_shared_req_rd),
|
|
.s_ctrlport_req_addr(ctrlport_shared_req_addr),
|
|
.s_ctrlport_req_data(ctrlport_shared_req_data),
|
|
.s_ctrlport_req_byte_en(ctrlport_shared_req_byte_en),
|
|
.s_ctrlport_req_has_time(ctrlport_shared_req_has_time),
|
|
.s_ctrlport_req_time(ctrlport_shared_req_time),
|
|
// Control Port Slave (Response)
|
|
.s_ctrlport_resp_ack(ctrlport_shared_resp_ack),
|
|
.s_ctrlport_resp_status(),
|
|
.s_ctrlport_resp_data(ctrlport_shared_resp_data),
|
|
// Control Port Master (Request)
|
|
.m_ctrlport_req_wr(),
|
|
.m_ctrlport_req_rd(ctrlport_timer_req_rd),
|
|
.m_ctrlport_req_addr(ctrlport_timer_req_addr),
|
|
.m_ctrlport_req_data(),
|
|
.m_ctrlport_req_byte_en(),
|
|
// Control Port Master (Response)
|
|
.m_ctrlport_resp_ack(ctrlport_timer_resp_ack),
|
|
.m_ctrlport_resp_status(2'b00),
|
|
.m_ctrlport_resp_data(ctrlport_timer_resp_data)
|
|
);
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Shared Registers
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// These registers are shared by all radio channels.
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
|
|
localparam [15:0] compat_major = 16'd0;
|
|
localparam [15:0] compat_minor = 16'd1;
|
|
|
|
reg [31:0] radio_time_hi;
|
|
|
|
always @(posedge radio_clk) begin
|
|
if (radio_rst) begin
|
|
ctrlport_timer_resp_ack <= 0;
|
|
ctrlport_timer_resp_data <= 0;
|
|
radio_time_hi <= 32'h0;
|
|
end else begin
|
|
// Default assignments
|
|
ctrlport_timer_resp_ack <= 0;
|
|
ctrlport_timer_resp_data <= 0;
|
|
|
|
// Handle register reads
|
|
if (ctrlport_timer_req_rd) begin
|
|
ctrlport_timer_resp_ack <= 1;
|
|
case (ctrlport_timer_req_addr)
|
|
REG_COMPAT_NUM: begin
|
|
ctrlport_timer_resp_data <= { compat_major, compat_minor };
|
|
end
|
|
REG_TIME_LO: begin
|
|
ctrlport_timer_resp_data <= radio_time[31:0];
|
|
radio_time_hi <= radio_time[63:32];
|
|
end
|
|
REG_TIME_HI: begin
|
|
ctrlport_timer_resp_data <= radio_time_hi;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Radio Cores
|
|
//---------------------------------------------------------------------------
|
|
//
|
|
// This generate block instantiates one radio core for each channel that is
|
|
// requested by NUM_PORTS.
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
|
|
genvar i;
|
|
generate
|
|
for (i = 0; i < NUM_PORTS; i = i+1) begin : radio_core_gen
|
|
|
|
// The radio core contains all the logic related to a single radio channel.
|
|
radio_core #(
|
|
.SAMP_W (ITEM_W),
|
|
.NSPC (NIPC)
|
|
) radio_core_i (
|
|
.radio_clk (radio_clk),
|
|
.radio_rst (radio_rst),
|
|
|
|
// Slave Control Port (Register Access)
|
|
.s_ctrlport_req_wr (ctrlport_radios_req_wr[i]),
|
|
.s_ctrlport_req_rd (ctrlport_radios_req_rd[i]),
|
|
.s_ctrlport_req_addr (ctrlport_radios_req_addr[i*20 +: 20]),
|
|
.s_ctrlport_req_data (ctrlport_radios_req_data[i*32 +: 32]),
|
|
.s_ctrlport_resp_ack (ctrlport_radios_resp_ack[i]),
|
|
.s_ctrlport_resp_data (ctrlport_radios_resp_data[i*32 +: 32]),
|
|
|
|
// Master Control Port (Error Reporting)
|
|
.m_ctrlport_req_wr (ctrlport_err_radio_req_wr[i]),
|
|
.m_ctrlport_req_addr (ctrlport_err_radio_req_addr[i*20 +: 20]),
|
|
.m_ctrlport_req_portid (ctrlport_err_radio_req_portid[i*10 +: 10]),
|
|
.m_ctrlport_req_rem_epid (ctrlport_err_radio_req_rem_epid[i*16 +: 16]),
|
|
.m_ctrlport_req_rem_portid (ctrlport_err_radio_req_rem_portid[i*10 +: 10]),
|
|
.m_ctrlport_req_data (ctrlport_err_radio_req_data[i*32 +: 32]),
|
|
.m_ctrlport_req_has_time (ctrlport_err_radio_req_has_time[i]),
|
|
.m_ctrlport_req_time (ctrlport_err_radio_req_time[i*64 +: 64]),
|
|
.m_ctrlport_resp_ack (ctrlport_err_radio_resp_ack[i]),
|
|
|
|
// Tx Data Stream
|
|
.s_axis_tdata (axis_tx_tdata[RADIO_W*i +: RADIO_W]),
|
|
.s_axis_tlast (axis_tx_tlast[i]),
|
|
.s_axis_tvalid (axis_tx_tvalid[i]),
|
|
.s_axis_tready (axis_tx_tready[i]),
|
|
// Sideband Info
|
|
.s_axis_ttimestamp (axis_tx_ttimestamp[i*64 +: 64]),
|
|
.s_axis_thas_time (axis_tx_thas_time[i]),
|
|
.s_axis_teob (axis_tx_teob[i]),
|
|
|
|
// Rx Data Stream
|
|
.m_axis_tdata (axis_rx_tdata[RADIO_W*i +: RADIO_W]),
|
|
.m_axis_tlast (axis_rx_tlast[i]),
|
|
.m_axis_tvalid (axis_rx_tvalid[i]),
|
|
.m_axis_tready (axis_rx_tready[i]),
|
|
// Sideband Info
|
|
.m_axis_ttimestamp (axis_rx_ttimestamp[i*64 +: 64]),
|
|
.m_axis_thas_time (axis_rx_thas_time[i]),
|
|
.m_axis_teob (axis_rx_teob[i]),
|
|
|
|
// Radio Data
|
|
.radio_time (radio_time),
|
|
.radio_rx_data (radio_rx_data[(RADIO_W)*i +: (RADIO_W)]),
|
|
.radio_rx_stb (radio_rx_stb[i]),
|
|
.radio_rx_running (radio_rx_running[i]),
|
|
.radio_tx_data (radio_tx_data[(RADIO_W)*i +: (RADIO_W)]),
|
|
.radio_tx_stb (radio_tx_stb[i]),
|
|
.radio_tx_running (radio_tx_running[i])
|
|
);
|
|
end
|
|
endgenerate
|
|
endmodule
|