126 lines
5.0 KiB
Verilog
126 lines
5.0 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_data_swap
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// Description:
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// A generic data swapper module for AXI-Stream. The contents of
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// tdata are swapped based on the tswap signal. For each bit 'i'
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// in tswap, adjacent words of width 2^i are swapped if tswap[i]
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// is high. For example, if tswap[3] = 1, then each byte in tdata
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// will be swapped with its adjacent neighbor. It is permissible
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// for tswap to change for each transfer in an AXIS packet.
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// Swapping can also be configured to be static (zero logic) by
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// setting DYNAMIC = 0. To reduce area, certain swap stages can
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// even be disabled. For example, if STAGES_EN[2:0] is set to 0
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// then the lowest granularity for swaps will be a byte.
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//
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// Parameters:
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// - DATA_W: Width of the tdata bus in bits
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// - USER_W: Width of the tuser bus in bits
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// - STAGES_EN: Which swap stages are enabled.
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// - DYNAMIC: Dynamic swapping enabled (use tswap)
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//
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// Signals:
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// - s_axis_*: The input AXI stream
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// - m_axis_*: The output AXI stream
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//
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module axis_data_swap #(
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parameter integer DATA_W = 256,
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parameter integer USER_W = 1,
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parameter [$clog2(DATA_W)-1:0] STAGES_EN = 'hFFFFFFFF, //@HACK: Vivado does not allow $clog2 in value of this expr
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parameter [0:0] DYNAMIC = 1
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)(
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// Clock and Reset
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input wire clk,
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input wire rst,
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// Input AXIS
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input wire [DATA_W-1:0] s_axis_tdata,
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input wire [$clog2(DATA_W)-2:0] s_axis_tswap,
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input wire [USER_W-1:0] s_axis_tuser,
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input wire s_axis_tlast,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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// Output AXIS
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output wire [DATA_W-1:0] m_axis_tdata,
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output wire [USER_W-1:0] m_axis_tuser,
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output wire m_axis_tlast,
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output wire m_axis_tvalid,
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input wire m_axis_tready
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);
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localparam SWAP_STAGES = $clog2(DATA_W);
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localparam SWAP_W = $clog2(DATA_W)-1;
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genvar s, w;
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wire [DATA_W-1:0] stg_tdata [0:SWAP_STAGES], stg_tdata_swp[0:SWAP_STAGES], stg_tdata_res[0:SWAP_STAGES];
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wire [SWAP_W-1:0] stg_tswap [0:SWAP_STAGES];
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wire [USER_W-1:0] stg_tuser [0:SWAP_STAGES];
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wire stg_tlast [0:SWAP_STAGES];
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wire stg_tvalid[0:SWAP_STAGES];
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wire stg_tready[0:SWAP_STAGES];
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// Connect input and output to stage wires
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generate
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assign stg_tdata [0] = s_axis_tdata;
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assign stg_tswap [0] = s_axis_tswap;
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assign stg_tuser [0] = s_axis_tuser;
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assign stg_tlast [0] = s_axis_tlast;
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assign stg_tvalid[0] = s_axis_tvalid;
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assign s_axis_tready = stg_tready[0];
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assign m_axis_tdata = stg_tdata [SWAP_STAGES];
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assign m_axis_tuser = stg_tuser [SWAP_STAGES];
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assign m_axis_tlast = stg_tlast [SWAP_STAGES];
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assign m_axis_tvalid = stg_tvalid[SWAP_STAGES];
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assign stg_tready[SWAP_STAGES] = m_axis_tready;
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endgenerate
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// Instantiate AXIS flip-flops for each stage
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generate
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for (s = 0; s < SWAP_STAGES; s=s+1) begin
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if (STAGES_EN[SWAP_STAGES-s-1]) begin
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// Swap Logic
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for (w = 0; w < (1<<s); w=w+1) begin
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assign stg_tdata_swp[s][(w*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))] =
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stg_tdata[s][(((1<<s)-w-1)*(DATA_W/(1<<s)))+:(DATA_W/(1<<s))];
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end
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if (DYNAMIC) begin
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// Honor tswap in DYNAMIC mode.
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// Also add a flip_flop to break the long start-to-end critical path
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assign stg_tdata_res[s] = (s > 0 && stg_tswap[s][SWAP_W-s]) ?
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stg_tdata_swp[s] : stg_tdata[s];
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// Flip-flop
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axi_fifo_flop #(.WIDTH(DATA_W+SWAP_W+USER_W+1)) reg_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.i_tdata({stg_tlast[s], stg_tuser[s], stg_tswap[s], stg_tdata_res[s]}),
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.i_tvalid(stg_tvalid[s]), .i_tready(stg_tready[s]),
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.o_tdata({stg_tlast[s+1], stg_tuser[s+1], stg_tswap[s+1], stg_tdata[s+1]}),
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.o_tvalid(stg_tvalid[s+1]), .o_tready(stg_tready[s+1]),
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.occupied(), .space()
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);
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end else begin
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// Static swapping logic
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assign stg_tdata [s+1] = stg_tdata_swp[s];
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assign stg_tswap [s+1] = stg_tswap [s];
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assign stg_tuser [s+1] = stg_tuser [s];
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assign stg_tlast [s+1] = stg_tlast [s];
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assign stg_tvalid[s+1] = stg_tvalid [s];
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assign stg_tready[s] = stg_tready [s+1];
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end
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end else begin
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// Skip this stage
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assign stg_tdata [s+1] = stg_tdata [s];
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assign stg_tswap [s+1] = stg_tswap [s];
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assign stg_tuser [s+1] = stg_tuser [s];
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assign stg_tlast [s+1] = stg_tlast [s];
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assign stg_tvalid[s+1] = stg_tvalid[s];
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assign stg_tready[s] = stg_tready[s+1];
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end
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end
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endgenerate
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endmodule // axis_data_swap
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