Wade Fife
ab63d78a6c
Adds a BUILD_SEED make variable that can be set to a 32-bit integer, and adds an FPGA read-only register initialized by this variable. Changing this variable will randomly affect the FPGA build results. This can be useful when your build fails timing by a small amount, allowing you to build again and get different results with the same code. For example, you could run the following to produce an FPGA build with different timing results from the default build: make X310_XG BUILD_SEED=123 Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
283 lines
15 KiB
Systemverilog
283 lines
15 KiB
Systemverilog
//
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// Copyright 2023 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: global_regs_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// COMPAT_NUM_REG : 0x0 (x4xx_global_regs.v)
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// DATESTAMP_REG : 0x4 (x4xx_global_regs.v)
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// GIT_HASH_REG : 0x8 (x4xx_global_regs.v)
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// SCRATCH_REG : 0xC (x4xx_global_regs.v)
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// DEVICE_ID_REG : 0x10 (x4xx_global_regs.v)
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// RFNOC_INFO_REG : 0x14 (x4xx_global_regs.v)
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// CLOCK_CTRL_REG : 0x18 (x4xx_global_regs.v)
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// PPS_CTRL_REG : 0x1C (x4xx_global_regs.v)
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// CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v)
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// CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v)
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// BUILD_SEED_REG : 0x28 (x4xx_global_regs.v)
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// GPS_CTRL_REG : 0x38 (x4xx_global_regs.v)
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// GPS_STATUS_REG : 0x3C (x4xx_global_regs.v)
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// DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v)
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// DBOARD_STATUS_REG : 0x44 (x4xx_global_regs.v)
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// NUM_TIMEKEEPERS_REG : 0x48 (x4xx_global_regs.v)
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// SERIAL_NUM_LOW_REG : 0x4C (x4xx_global_regs.v)
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// SERIAL_NUM_HIGH_REG : 0x50 (x4xx_global_regs.v)
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// MFG_TEST_CTRL_REG : 0x54 (x4xx_global_regs.v)
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// MFG_TEST_STATUS_REG : 0x58 (x4xx_global_regs.v)
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// QSFP_PORT_0_0_INFO_REG : 0x60 (x4xx_global_regs.v)
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// QSFP_PORT_0_1_INFO_REG : 0x64 (x4xx_global_regs.v)
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// QSFP_PORT_0_2_INFO_REG : 0x68 (x4xx_global_regs.v)
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// QSFP_PORT_0_3_INFO_REG : 0x6C (x4xx_global_regs.v)
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// QSFP_PORT_1_0_INFO_REG : 0x70 (x4xx_global_regs.v)
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// QSFP_PORT_1_1_INFO_REG : 0x74 (x4xx_global_regs.v)
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// QSFP_PORT_1_2_INFO_REG : 0x78 (x4xx_global_regs.v)
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// QSFP_PORT_1_3_INFO_REG : 0x7C (x4xx_global_regs.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group GLOBAL_REGS
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//===============================================================================
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// COMPAT_NUM_REG Register (from x4xx_global_regs.v)
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localparam COMPAT_NUM_REG = 'h0; // Register Offset
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localparam COMPAT_NUM_REG_SIZE = 32; // register width in bits
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localparam COMPAT_NUM_REG_MASK = 32'hFFFFFFFF;
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localparam COMPAT_MINOR_SIZE = 16; //COMPAT_NUM_REG:COMPAT_MINOR
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localparam COMPAT_MINOR_MSB = 15; //COMPAT_NUM_REG:COMPAT_MINOR
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localparam COMPAT_MINOR = 0; //COMPAT_NUM_REG:COMPAT_MINOR
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localparam COMPAT_MAJOR_SIZE = 16; //COMPAT_NUM_REG:COMPAT_MAJOR
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localparam COMPAT_MAJOR_MSB = 31; //COMPAT_NUM_REG:COMPAT_MAJOR
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localparam COMPAT_MAJOR = 16; //COMPAT_NUM_REG:COMPAT_MAJOR
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// DATESTAMP_REG Register (from x4xx_global_regs.v)
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localparam DATESTAMP_REG = 'h4; // Register Offset
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localparam DATESTAMP_REG_SIZE = 32; // register width in bits
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localparam DATESTAMP_REG_MASK = 32'hFFFFFFFF;
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localparam SECONDS_SIZE = 6; //DATESTAMP_REG:SECONDS
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localparam SECONDS_MSB = 5; //DATESTAMP_REG:SECONDS
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localparam SECONDS = 0; //DATESTAMP_REG:SECONDS
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localparam MINUTES_SIZE = 6; //DATESTAMP_REG:MINUTES
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localparam MINUTES_MSB = 11; //DATESTAMP_REG:MINUTES
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localparam MINUTES = 6; //DATESTAMP_REG:MINUTES
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localparam HOUR_SIZE = 5; //DATESTAMP_REG:HOUR
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localparam HOUR_MSB = 16; //DATESTAMP_REG:HOUR
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localparam HOUR = 12; //DATESTAMP_REG:HOUR
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localparam YEAR_SIZE = 6; //DATESTAMP_REG:YEAR
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localparam YEAR_MSB = 22; //DATESTAMP_REG:YEAR
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localparam YEAR = 17; //DATESTAMP_REG:YEAR
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localparam MONTH_SIZE = 4; //DATESTAMP_REG:MONTH
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localparam MONTH_MSB = 26; //DATESTAMP_REG:MONTH
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localparam MONTH = 23; //DATESTAMP_REG:MONTH
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localparam DAY_SIZE = 5; //DATESTAMP_REG:DAY
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localparam DAY_MSB = 31; //DATESTAMP_REG:DAY
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localparam DAY = 27; //DATESTAMP_REG:DAY
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// GIT_HASH_REG Register (from x4xx_global_regs.v)
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localparam GIT_HASH_REG = 'h8; // Register Offset
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localparam GIT_HASH_REG_SIZE = 32; // register width in bits
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localparam GIT_HASH_REG_MASK = 32'h0;
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// SCRATCH_REG Register (from x4xx_global_regs.v)
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localparam SCRATCH_REG = 'hC; // Register Offset
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localparam SCRATCH_REG_SIZE = 32; // register width in bits
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localparam SCRATCH_REG_MASK = 32'h0;
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// DEVICE_ID_REG Register (from x4xx_global_regs.v)
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localparam DEVICE_ID_REG = 'h10; // Register Offset
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localparam DEVICE_ID_REG_SIZE = 32; // register width in bits
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localparam DEVICE_ID_REG_MASK = 32'h8000FFFF;
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localparam DEVICE_ID_SIZE = 16; //DEVICE_ID_REG:DEVICE_ID
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localparam DEVICE_ID_MSB = 15; //DEVICE_ID_REG:DEVICE_ID
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localparam DEVICE_ID = 0; //DEVICE_ID_REG:DEVICE_ID
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localparam PCIE_PRESENT_BIT_SIZE = 1; //DEVICE_ID_REG:PCIE_PRESENT_BIT
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localparam PCIE_PRESENT_BIT_MSB = 31; //DEVICE_ID_REG:PCIE_PRESENT_BIT
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localparam PCIE_PRESENT_BIT = 31; //DEVICE_ID_REG:PCIE_PRESENT_BIT
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// RFNOC_INFO_REG Register (from x4xx_global_regs.v)
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localparam RFNOC_INFO_REG = 'h14; // Register Offset
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localparam RFNOC_INFO_REG_SIZE = 32; // register width in bits
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localparam RFNOC_INFO_REG_MASK = 32'hFFFFFFFF;
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localparam RFNOC_PROTO_MINOR_SIZE = 8; //RFNOC_INFO_REG:RFNOC_PROTO_MINOR
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localparam RFNOC_PROTO_MINOR_MSB = 7; //RFNOC_INFO_REG:RFNOC_PROTO_MINOR
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localparam RFNOC_PROTO_MINOR = 0; //RFNOC_INFO_REG:RFNOC_PROTO_MINOR
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localparam RFNOC_PROTO_MAJOR_SIZE = 8; //RFNOC_INFO_REG:RFNOC_PROTO_MAJOR
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localparam RFNOC_PROTO_MAJOR_MSB = 15; //RFNOC_INFO_REG:RFNOC_PROTO_MAJOR
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localparam RFNOC_PROTO_MAJOR = 8; //RFNOC_INFO_REG:RFNOC_PROTO_MAJOR
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localparam CHDR_WIDTH_SIZE = 16; //RFNOC_INFO_REG:CHDR_WIDTH
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localparam CHDR_WIDTH_MSB = 31; //RFNOC_INFO_REG:CHDR_WIDTH
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localparam CHDR_WIDTH = 16; //RFNOC_INFO_REG:CHDR_WIDTH
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// CLOCK_CTRL_REG Register (from x4xx_global_regs.v)
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localparam CLOCK_CTRL_REG = 'h18; // Register Offset
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localparam CLOCK_CTRL_REG_SIZE = 32; // register width in bits
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localparam CLOCK_CTRL_REG_MASK = 32'hFFFF033F;
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localparam PPS_SELECT_SIZE = 2; //CLOCK_CTRL_REG:PPS_SELECT
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localparam PPS_SELECT_MSB = 1; //CLOCK_CTRL_REG:PPS_SELECT
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localparam PPS_SELECT = 0; //CLOCK_CTRL_REG:PPS_SELECT
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localparam PPS_ENUM_SIZE = 3;
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localparam PPS_INT_25MHZ = 'h0; // enum value
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localparam PPS_INT_10MHZ = 'h1; // enum value
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localparam PPS_EXT = 'h2; // enum value
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localparam REF_SELECT_SIZE = 1; //CLOCK_CTRL_REG:REF_SELECT
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localparam REF_SELECT_MSB = 2; //CLOCK_CTRL_REG:REF_SELECT
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localparam REF_SELECT = 2; //CLOCK_CTRL_REG:REF_SELECT
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localparam REFCLK_LOCKED_SIZE = 1; //CLOCK_CTRL_REG:REFCLK_LOCKED
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localparam REFCLK_LOCKED_MSB = 3; //CLOCK_CTRL_REG:REFCLK_LOCKED
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localparam REFCLK_LOCKED = 3; //CLOCK_CTRL_REG:REFCLK_LOCKED
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localparam TRIGGER_IO_SELECT_SIZE = 2; //CLOCK_CTRL_REG:TRIGGER_IO_SELECT
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localparam TRIGGER_IO_SELECT_MSB = 5; //CLOCK_CTRL_REG:TRIGGER_IO_SELECT
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localparam TRIGGER_IO_SELECT = 4; //CLOCK_CTRL_REG:TRIGGER_IO_SELECT
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localparam TRIG_IO_ENUM_SIZE = 2;
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localparam TRIG_IO_INPUT = 'h0; // enum value
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localparam TRIG_IO_PPS_OUTPUT = 'h1; // enum value
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localparam PLL_SYNC_TRIGGER_SIZE = 1; //CLOCK_CTRL_REG:PLL_SYNC_TRIGGER
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localparam PLL_SYNC_TRIGGER_MSB = 8; //CLOCK_CTRL_REG:PLL_SYNC_TRIGGER
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localparam PLL_SYNC_TRIGGER = 8; //CLOCK_CTRL_REG:PLL_SYNC_TRIGGER
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localparam PLL_SYNC_DONE_SIZE = 1; //CLOCK_CTRL_REG:PLL_SYNC_DONE
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localparam PLL_SYNC_DONE_MSB = 9; //CLOCK_CTRL_REG:PLL_SYNC_DONE
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localparam PLL_SYNC_DONE = 9; //CLOCK_CTRL_REG:PLL_SYNC_DONE
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localparam PLL_SYNC_DELAY_SIZE = 8; //CLOCK_CTRL_REG:PLL_SYNC_DELAY
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localparam PLL_SYNC_DELAY_MSB = 23; //CLOCK_CTRL_REG:PLL_SYNC_DELAY
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localparam PLL_SYNC_DELAY = 16; //CLOCK_CTRL_REG:PLL_SYNC_DELAY
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localparam PPS_BRC_DELAY_SIZE = 8; //CLOCK_CTRL_REG:PPS_BRC_DELAY
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localparam PPS_BRC_DELAY_MSB = 31; //CLOCK_CTRL_REG:PPS_BRC_DELAY
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localparam PPS_BRC_DELAY = 24; //CLOCK_CTRL_REG:PPS_BRC_DELAY
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// PPS_CTRL_REG Register (from x4xx_global_regs.v)
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localparam PPS_CTRL_REG = 'h1C; // Register Offset
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localparam PPS_CTRL_REG_SIZE = 32; // register width in bits
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localparam PPS_CTRL_REG_MASK = 32'hB3FFFFFF;
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localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY
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localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY
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localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY
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localparam PRC_RC_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC_DIVIDER
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localparam PRC_RC_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC_DIVIDER
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localparam PRC_RC_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC_DIVIDER
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localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED
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localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
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localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED
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// CHDR_CLK_RATE_REG Register (from x4xx_global_regs.v)
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localparam CHDR_CLK_RATE_REG = 'h20; // Register Offset
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localparam CHDR_CLK_RATE_REG_SIZE = 32; // register width in bits
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localparam CHDR_CLK_RATE_REG_MASK = 32'hFFFFFFFF;
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localparam CHDR_CLK_SIZE = 32; //CHDR_CLK_RATE_REG:CHDR_CLK
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localparam CHDR_CLK_MSB = 31; //CHDR_CLK_RATE_REG:CHDR_CLK
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localparam CHDR_CLK = 0; //CHDR_CLK_RATE_REG:CHDR_CLK
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localparam CHDR_CLK_ENUM_SIZE = 1;
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localparam CHDR_CLK_VALUE = 'hBEBC200; // enum value
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// CHDR_CLK_COUNT_REG Register (from x4xx_global_regs.v)
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localparam CHDR_CLK_COUNT_REG = 'h24; // Register Offset
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localparam CHDR_CLK_COUNT_REG_SIZE = 32; // register width in bits
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localparam CHDR_CLK_COUNT_REG_MASK = 32'h0;
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// BUILD_SEED_REG Register (from x4xx_global_regs.v)
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localparam BUILD_SEED_REG = 'h28; // Register Offset
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localparam BUILD_SEED_REG_SIZE = 32; // register width in bits
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localparam BUILD_SEED_REG_MASK = 32'h0;
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// GPS_CTRL_REG Register (from x4xx_global_regs.v)
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localparam GPS_CTRL_REG = 'h38; // Register Offset
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localparam GPS_CTRL_REG_SIZE = 32; // register width in bits
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localparam GPS_CTRL_REG_MASK = 32'h0;
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// GPS_STATUS_REG Register (from x4xx_global_regs.v)
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localparam GPS_STATUS_REG = 'h3C; // Register Offset
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localparam GPS_STATUS_REG_SIZE = 32; // register width in bits
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localparam GPS_STATUS_REG_MASK = 32'h0;
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// DBOARD_CTRL_REG Register (from x4xx_global_regs.v)
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localparam DBOARD_CTRL_REG = 'h40; // Register Offset
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localparam DBOARD_CTRL_REG_SIZE = 32; // register width in bits
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localparam DBOARD_CTRL_REG_MASK = 32'h0;
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// DBOARD_STATUS_REG Register (from x4xx_global_regs.v)
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localparam DBOARD_STATUS_REG = 'h44; // Register Offset
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localparam DBOARD_STATUS_REG_SIZE = 32; // register width in bits
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localparam DBOARD_STATUS_REG_MASK = 32'h0;
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// NUM_TIMEKEEPERS_REG Register (from x4xx_global_regs.v)
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localparam NUM_TIMEKEEPERS_REG = 'h48; // Register Offset
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localparam NUM_TIMEKEEPERS_REG_SIZE = 32; // register width in bits
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localparam NUM_TIMEKEEPERS_REG_MASK = 32'h0;
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// SERIAL_NUM_LOW_REG Register (from x4xx_global_regs.v)
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localparam SERIAL_NUM_LOW_REG = 'h4C; // Register Offset
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localparam SERIAL_NUM_LOW_REG_SIZE = 32; // register width in bits
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localparam SERIAL_NUM_LOW_REG_MASK = 32'h0;
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// SERIAL_NUM_HIGH_REG Register (from x4xx_global_regs.v)
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localparam SERIAL_NUM_HIGH_REG = 'h50; // Register Offset
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localparam SERIAL_NUM_HIGH_REG_SIZE = 32; // register width in bits
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localparam SERIAL_NUM_HIGH_REG_MASK = 32'h0;
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// MFG_TEST_CTRL_REG Register (from x4xx_global_regs.v)
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localparam MFG_TEST_CTRL_REG = 'h54; // Register Offset
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localparam MFG_TEST_CTRL_REG_SIZE = 32; // register width in bits
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localparam MFG_TEST_CTRL_REG_MASK = 32'h3;
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localparam MFG_TEST_EN_GTY_RCV_CLK_SIZE = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_GTY_RCV_CLK
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localparam MFG_TEST_EN_GTY_RCV_CLK_MSB = 0; //MFG_TEST_CTRL_REG:MFG_TEST_EN_GTY_RCV_CLK
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localparam MFG_TEST_EN_GTY_RCV_CLK = 0; //MFG_TEST_CTRL_REG:MFG_TEST_EN_GTY_RCV_CLK
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localparam MFG_TEST_EN_FABRIC_CLK_SIZE = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_FABRIC_CLK
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localparam MFG_TEST_EN_FABRIC_CLK_MSB = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_FABRIC_CLK
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localparam MFG_TEST_EN_FABRIC_CLK = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_FABRIC_CLK
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// MFG_TEST_STATUS_REG Register (from x4xx_global_regs.v)
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localparam MFG_TEST_STATUS_REG = 'h58; // Register Offset
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localparam MFG_TEST_STATUS_REG_SIZE = 32; // register width in bits
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localparam MFG_TEST_STATUS_REG_MASK = 32'h3FFFFFF;
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localparam MFG_TEST_FPGA_AUX_REF_FREQ_SIZE = 26; //MFG_TEST_STATUS_REG:MFG_TEST_FPGA_AUX_REF_FREQ
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localparam MFG_TEST_FPGA_AUX_REF_FREQ_MSB = 25; //MFG_TEST_STATUS_REG:MFG_TEST_FPGA_AUX_REF_FREQ
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localparam MFG_TEST_FPGA_AUX_REF_FREQ = 0; //MFG_TEST_STATUS_REG:MFG_TEST_FPGA_AUX_REF_FREQ
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// QSFP_PORT_0_0_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_0_0_INFO_REG = 'h60; // Register Offset
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localparam QSFP_PORT_0_0_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_0_0_INFO_REG_MASK = 32'h0;
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// QSFP_PORT_0_1_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_0_1_INFO_REG = 'h64; // Register Offset
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localparam QSFP_PORT_0_1_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_0_1_INFO_REG_MASK = 32'h0;
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// QSFP_PORT_0_2_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_0_2_INFO_REG = 'h68; // Register Offset
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localparam QSFP_PORT_0_2_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_0_2_INFO_REG_MASK = 32'h0;
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// QSFP_PORT_0_3_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_0_3_INFO_REG = 'h6C; // Register Offset
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localparam QSFP_PORT_0_3_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_0_3_INFO_REG_MASK = 32'h0;
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// QSFP_PORT_1_0_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_1_0_INFO_REG = 'h70; // Register Offset
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localparam QSFP_PORT_1_0_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_1_0_INFO_REG_MASK = 32'h0;
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// QSFP_PORT_1_1_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_1_1_INFO_REG = 'h74; // Register Offset
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localparam QSFP_PORT_1_1_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_1_1_INFO_REG_MASK = 32'h0;
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// QSFP_PORT_1_2_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_1_2_INFO_REG = 'h78; // Register Offset
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localparam QSFP_PORT_1_2_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_1_2_INFO_REG_MASK = 32'h0;
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// QSFP_PORT_1_3_INFO_REG Register (from x4xx_global_regs.v)
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localparam QSFP_PORT_1_3_INFO_REG = 'h7C; // Register Offset
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localparam QSFP_PORT_1_3_INFO_REG_SIZE = 32; // register width in bits
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localparam QSFP_PORT_1_3_INFO_REG_MASK = 32'h0;
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