5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
88 lines
3.7 KiB
Tcl
88 lines
3.7 KiB
Tcl
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# RF data converters pin constraints for X440.
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# Converter pin mapping can be found at(redirected from UG1075):
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# https://www.xilinx.com/support/packagefiles/zuppackages/xczu28drffvg1517pkg.txt
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#
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# SYSREF input for data converters.
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set_property PACKAGE_PIN U4 [get_ports {SYSREF_RF_N}]
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set_property PACKAGE_PIN U5 [get_ports {SYSREF_RF_P}]
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###############################################################################
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# Pin constraints for the ADCs
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###############################################################################
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# ADC Reference Clocks for Slot 0 (DBA)
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set_property PACKAGE_PIN AF5 [get_ports {ADC_CLK_P[0]}]
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set_property PACKAGE_PIN AF4 [get_ports {ADC_CLK_N[0]}]
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set_property PACKAGE_PIN AD5 [get_ports {ADC_CLK_P[1]}]
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set_property PACKAGE_PIN AD4 [get_ports {ADC_CLK_N[1]}]
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# ADC Reference Clocks for Slot 1 (DBB)
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set_property PACKAGE_PIN AB5 [get_ports {ADC_CLK_P[2]}]
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set_property PACKAGE_PIN AB4 [get_ports {ADC_CLK_N[2]}]
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set_property PACKAGE_PIN Y5 [get_ports {ADC_CLK_P[3]}]
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set_property PACKAGE_PIN Y4 [get_ports {ADC_CLK_N[3]}]
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# ADC Inputs for Slot 0 (DBA)
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# Note: numbering here does NOT match schematic, but it is the right order
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# according to RF BD Connection spec.
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set_property PACKAGE_PIN AH2 [get_ports {DB0_RX_P[3]}]
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set_property PACKAGE_PIN AH1 [get_ports {DB0_RX_N[3]}]
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set_property PACKAGE_PIN AK2 [get_ports {DB0_RX_P[2]}]
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set_property PACKAGE_PIN AK1 [get_ports {DB0_RX_N[2]}]
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set_property PACKAGE_PIN AM2 [get_ports {DB0_RX_P[1]}]
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set_property PACKAGE_PIN AM1 [get_ports {DB0_RX_N[1]}]
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set_property PACKAGE_PIN AP2 [get_ports {DB0_RX_P[0]}]
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set_property PACKAGE_PIN AP1 [get_ports {DB0_RX_N[0]}]
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# ADC Inputs for Slot 1 (DBB)
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# Note: numbering here does NOT match schematic, but it is the right order
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# according to RF BD Connection spec.
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set_property PACKAGE_PIN Y2 [get_ports {DB1_RX_P[3]}]
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set_property PACKAGE_PIN Y1 [get_ports {DB1_RX_N[3]}]
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set_property PACKAGE_PIN AB2 [get_ports {DB1_RX_P[2]}]
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set_property PACKAGE_PIN AB1 [get_ports {DB1_RX_N[2]}]
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set_property PACKAGE_PIN AD2 [get_ports {DB1_RX_P[1]}]
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set_property PACKAGE_PIN AD1 [get_ports {DB1_RX_N[1]}]
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set_property PACKAGE_PIN AF2 [get_ports {DB1_RX_P[0]}]
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set_property PACKAGE_PIN AF1 [get_ports {DB1_RX_N[0]}]
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###############################################################################
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# Pin constraints for the DACs
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###############################################################################
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# DAC Reference Clock for Slot 0 (DBA)
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set_property PACKAGE_PIN R5 [get_ports {DAC_CLK_P[0]}]
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set_property PACKAGE_PIN R4 [get_ports {DAC_CLK_N[0]}]
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# DAC Reference Clock for Slot 1 (DBB)
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set_property PACKAGE_PIN N5 [get_ports {DAC_CLK_P[1]}]
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set_property PACKAGE_PIN N4 [get_ports {DAC_CLK_N[1]}]
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# DAC Outputs for Slot 0 (DBA)
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set_property PACKAGE_PIN U2 [get_ports {DB0_TX_P[0]}]
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set_property PACKAGE_PIN U1 [get_ports {DB0_TX_N[0]}]
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set_property PACKAGE_PIN R2 [get_ports {DB0_TX_P[1]}]
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set_property PACKAGE_PIN R1 [get_ports {DB0_TX_N[1]}]
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set_property PACKAGE_PIN N2 [get_ports {DB0_TX_P[2]}]
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set_property PACKAGE_PIN N1 [get_ports {DB0_TX_N[2]}]
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set_property PACKAGE_PIN L2 [get_ports {DB0_TX_P[3]}]
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set_property PACKAGE_PIN L1 [get_ports {DB0_TX_N[3]}]
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# DAC Outputs for Slot 1 (DBB)
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set_property PACKAGE_PIN J2 [get_ports {DB1_TX_P[0]}]
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set_property PACKAGE_PIN J1 [get_ports {DB1_TX_N[0]}]
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set_property PACKAGE_PIN G2 [get_ports {DB1_TX_P[1]}]
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set_property PACKAGE_PIN G1 [get_ports {DB1_TX_N[1]}]
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set_property PACKAGE_PIN E2 [get_ports {DB1_TX_P[2]}]
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set_property PACKAGE_PIN E1 [get_ports {DB1_TX_N[2]}]
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set_property PACKAGE_PIN C2 [get_ports {DB1_TX_P[3]}]
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set_property PACKAGE_PIN C1 [get_ports {DB1_TX_N[3]}]
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