Andrew Moch
02e4ef3318
AxiLiteBfm incorrectly included stb argument on rd() and printed actual response instead of expected in debug message. Original-commit: cb7e9e24578ccf4db79878a7437a6a85ad315ee2
739 lines
23 KiB
Systemverilog
739 lines
23 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: PkgAxiLiteBfm
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//
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// Description: Package for AXI4-Lite bus functional model (BFM).
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// This consists of the AxiLiteTransaction and AxiLiteBfm classes.
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// It's based on the AxiLiteIf interface.
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//
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//-----------------------------------------------------------------------------
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// AXI-Lite BFM Package
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//-----------------------------------------------------------------------------
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package PkgAxiLiteBfm;
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import PkgAxiLite::*;
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export PkgAxiLite::*;
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typedef enum {READ,WRITE} xtype_t;
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//---------------------------------------------------------------------------
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// AXI Lite Transaction Class
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//---------------------------------------------------------------------------
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class AxiLiteTransaction #(DATA_WIDTH = 32, ADDR_WIDTH = 32);
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//------------------
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// Type Definitions
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//------------------
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localparam BYTES_PER_WORD = DATA_WIDTH/8;
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// local type defs
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typedef logic [DATA_WIDTH-1:0] data_t;
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typedef logic [ADDR_WIDTH-1:0] addr_t;
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typedef logic [BYTES_PER_WORD-1:0] strb_t;
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typedef AxiLiteTransaction #(DATA_WIDTH, ADDR_WIDTH) AxiLiteTransaction_t;
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//------------
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// Properties
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//------------
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xtype_t xtype;
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data_t data;
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addr_t addr;
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strb_t strb = '1;
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resp_t resp = OKAY;
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int id;
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//---------
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// Methods
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//---------
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// Return a handle to a copy of this transaction
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function AxiLiteTransaction_t copy();
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AxiLiteTransaction_t temp;
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temp = new();
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temp.xtype = this.xtype;
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temp.data = this.data;
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temp.addr = this.addr;
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temp.strb = this.strb;
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temp.resp = this.resp;
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temp.id = this.id;
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return temp;
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endfunction
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// Return true if this xaction equals that of the argument
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virtual function bit equal(AxiLiteTransaction_t xaction);
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return (this.xtype === xaction.xtype &&
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this.data === xaction.data &&
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this.addr === xaction.addr &&
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this.strb === xaction.strb &&
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this.resp === xaction.resp);
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endfunction : equal
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// Format the contents of the xaction into a string
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function string sprint();
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return $sformatf("%s a=%X d=%X strb=%X resp=%s id=%d",this.xtype.name,
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this.addr,this.data,this.strb,this.resp.name,this.id);
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endfunction : sprint
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// Print the contents of the xaction
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function void print();
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$display(sprint());
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endfunction : print
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endclass : AxiLiteTransaction;
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//---------------------------------------------------------------------------
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// AXI Lite BFM Class
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//---------------------------------------------------------------------------
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class AxiLiteBfm #(
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int DATA_WIDTH = 32,
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int ADDR_WIDTH = 32
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);
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//------------------
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// Type Definitions
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//------------------
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typedef AxiLiteTransaction #(DATA_WIDTH, ADDR_WIDTH) AxiLiteTransaction_t;
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typedef AxiLiteTransaction_t::data_t data_t;
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typedef AxiLiteTransaction_t::addr_t addr_t;
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typedef AxiLiteTransaction_t::strb_t strb_t;
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//------------
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// Properties
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//------------
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// Default stall probability, as a percentage (0-100).
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local const int DEF_STALL_PROB = 38;
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// Virtual interfaces for master and slave connections to DUT
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local virtual AxiLiteIf #(DATA_WIDTH,ADDR_WIDTH).master master;
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local virtual AxiLiteIf #(DATA_WIDTH,ADDR_WIDTH).slave slave;
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// NOTE: We should not need these flags if Vivado would be OK with null check
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// without throwing unnecessary null-ptr deref exceptions.
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local bit master_en;
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local bit slave_en;
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// Each submitted transaction is given an id. The id is used when
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// waiting for the response
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local int id=0;
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// submit/completion id's are used to enforce rd/wr ordering
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local int wr_submit_id=0;
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local int wr_complete_id=0;
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local int rd_submit_id=0;
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local int rd_complete_id=0;
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// Queues to store the bus transactions
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mailbox #(AxiLiteTransaction_t) master_rd_req_xactions;
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mailbox #(AxiLiteTransaction_t) master_rd_inflight_xactions;
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mailbox #(AxiLiteTransaction_t) master_rd_resp_xactions;
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mailbox #(AxiLiteTransaction_t) master_wr_req_xactions;
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mailbox #(AxiLiteTransaction_t) master_wr_inflight_xactions;
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mailbox #(AxiLiteTransaction_t) master_wr_resp_xactions;
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mailbox #(AxiLiteTransaction_t) slave_rd_req_xactions;
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mailbox #(AxiLiteTransaction_t) slave_rd_resp_xactions;
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mailbox #(AxiLiteTransaction_t) slave_wr_req_xactions;
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mailbox #(AxiLiteTransaction_t) slave_wr_resp_xactions;
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// Properties for the stall behavior of the BFM
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int stall_prob = DEF_STALL_PROB;
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// determine if ready parks innactive
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bit ready_idle_state = 1;
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// Read write ordering
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bit rds_wait_for_wrs = 1;
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bit wrs_wait_for_rds = 1;
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// Number of clocks betwen transactions
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int inter_xaction_gap = 0;
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//---------
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// Methods
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//---------
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// Returns 1 if the xactions have the same contents, otherwise returns 0.
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function bit xactions_equal(AxiLiteTransaction_t a, AxiLiteTransaction_t b);
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return a.equal(b);
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endfunction : xactions_equal
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// Class constructor. This must be given an interface for the master
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// connection and an interface for the slave connection.
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function new(
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virtual AxiLiteIf #(DATA_WIDTH,ADDR_WIDTH).master master=null,
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virtual AxiLiteIf #(DATA_WIDTH,ADDR_WIDTH).slave slave=null
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);
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this.master_en = (master != null);
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this.slave_en = (slave != null);
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this.master = master;
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this.slave = slave;
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master_rd_req_xactions = new;
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master_rd_inflight_xactions = new;
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master_rd_resp_xactions = new;
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master_wr_req_xactions = new;
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master_wr_inflight_xactions = new;
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master_wr_resp_xactions = new;
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slave_rd_req_xactions = new;
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slave_rd_resp_xactions = new;
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slave_wr_req_xactions = new;
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slave_wr_resp_xactions = new;
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endfunction : new
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// Internal functions - Users should use wr/wr_block
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// This function pushes the write_addr/write_data channels
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task automatic post_wr(addr_t addr, data_t data, strb_t strb='1,
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AxiLiteTransaction_t xaction);
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int rd_submit_id_at_start = rd_submit_id;
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xaction.xtype = WRITE;
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xaction.addr = addr;
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xaction.data = data;
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xaction.strb = strb;
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xaction.id = ++this.id;
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wr_submit_id = xaction.id;
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if (wrs_wait_for_rds) begin
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// wait for any reads that may of been submitted before
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// this write to complete before exectuing
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while (rd_complete_id-rd_submit_id_at_start < 0) begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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end
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put(xaction);
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endtask : post_wr
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// Internal functions - Users should use wr/wr_block
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// This function wait for the write respone channel
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task automatic get_wr_response(AxiLiteTransaction_t xaction);
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AxiLiteTransaction_t resp_xaction = null;
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forever begin
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while(!try_peek_wr(resp_xaction)) begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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if (resp_xaction.id == xaction.id) begin
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break;
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end else begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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end
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get_wr(xaction);
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wr_complete_id = xaction.id;
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endtask :get_wr_response
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// Simple blocking write
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task automatic wr_block(addr_t addr, data_t data, strb_t strb='1, output resp_t resp);
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AxiLiteTransaction_t xaction = new;
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post_wr(addr,data,strb,xaction);
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get_wr_response(xaction);
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resp = xaction.resp;
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endtask : wr_block
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// Non-blocking write that checks against an expected response
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task automatic wr(addr_t addr, data_t data, strb_t strb='1,resp_t resp=OKAY);
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AxiLiteTransaction_t xaction = new;
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post_wr(addr,data,strb,xaction);
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fork
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begin
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get_wr_response(xaction);
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assert (xaction.resp == resp) else begin
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xaction.print();
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$error({"mismatch on wr response. expected:",resp.name});
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end
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end
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join_none
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endtask : wr
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// Internal functions - Users should use rd/rd_block
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// This function pushes the read address channel
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task automatic post_rd(addr_t addr,AxiLiteTransaction_t xaction);
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int wr_submit_id_at_start = wr_submit_id;
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xaction.xtype = READ;
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xaction.addr = addr;
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xaction.id = ++this.id;
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rd_submit_id = xaction.id;
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// wait for any writes that may have been
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// submitted before this read to complete
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if (rds_wait_for_wrs) begin
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while (wr_complete_id-wr_submit_id_at_start < 0) begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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end
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put(xaction);
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endtask : post_rd
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// Internal functions - Users should use rd/rd_block
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// This function waits for the read response channel
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task automatic get_rd_response(AxiLiteTransaction_t xaction);
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AxiLiteTransaction_t resp_xaction = null;
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forever begin
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while(!try_peek_rd(resp_xaction)) begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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if (resp_xaction.id == xaction.id) begin
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break;
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end else begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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end
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get_rd(xaction);
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rd_complete_id = xaction.id;
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endtask : get_rd_response
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// Simple blocking read
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task automatic rd_block(addr_t addr, output data_t data, output resp_t resp);
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AxiLiteTransaction_t xaction = new;
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post_rd(addr,xaction);
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get_rd_response(xaction);
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data = xaction.data;
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resp = xaction.resp;
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endtask : rd_block
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// Non-blocking read that checks against an expected data response
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task automatic rd(addr_t addr, data_t data, resp_t resp=OKAY);
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AxiLiteTransaction_t xaction = new;
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post_rd(addr,xaction);
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fork
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begin
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get_rd_response(xaction);
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assert (xaction.resp == resp) else begin
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xaction.print();
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$error({"mismatch on rd response. expected:",resp.name});
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end
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assert (xaction.data === data) else begin
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xaction.print();
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$error({"mismatch on rd data. expected:",$sformatf("%x",data)});
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end
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end
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join_none
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endtask : rd
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task automatic block();
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int rd_submit_id_at_start = rd_submit_id;
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int wr_submit_id_at_start = wr_submit_id;
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while (rd_complete_id-rd_submit_id_at_start < 0 ||
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wr_complete_id-wr_submit_id_at_start < 0) begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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endtask : block
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// Queue the provided xaction for transmission
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task put(AxiLiteTransaction_t xaction);
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if (xaction.xtype == READ && master_en) begin
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master_rd_req_xactions.put(xaction);
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end else if (xaction.xtype == WRITE && master_en) begin
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master_wr_req_xactions.put(xaction);
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end else if (xaction.xtype == READ && slave_en) begin
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slave_rd_resp_xactions.put(xaction);
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end else if (xaction.xtype == WRITE && slave_en) begin
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slave_wr_resp_xactions.put(xaction);
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end
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endtask : put
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// Attempt to queue the provided xaction for transmission. Return 1 if
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// successful, return 0 if the queue is full.
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function bit try_put(AxiLiteTransaction_t xaction);
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if (xaction.xtype == READ && master_en) begin
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return master_rd_req_xactions.try_put(xaction);
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end else if (xaction.xtype == WRITE && master_en) begin
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return master_wr_req_xactions.try_put(xaction);
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end else if (xaction.xtype == READ && slave_en) begin
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return slave_rd_resp_xactions.try_put(xaction);
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end else if (xaction.xtype == WRITE && slave_en) begin
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return slave_wr_resp_xactions.try_put(xaction);
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end
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endfunction : try_put
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// Get the next rd_xaction when it becomes available (waits if necessary)
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task get_rd(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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master_rd_resp_xactions.get(xaction);
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end else if (slave_en) begin
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slave_rd_req_xactions.get(xaction);
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end
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endtask : get_rd
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// Get the next wr_xaction when it becomes available (waits if necessary)
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task get_wr(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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master_wr_resp_xactions.get(xaction);
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end else if (slave_en) begin
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slave_wr_req_xactions.get(xaction);
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end
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endtask : get_wr
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// Get the next rd_xaction if there's one available and return 1. Return 0 if
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// there's no xaction available.
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function bit try_get_rd(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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return master_rd_resp_xactions.try_get(xaction);
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end else if (slave_en) begin
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return slave_rd_req_xactions.try_get(xaction);
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end
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endfunction : try_get_rd
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// Get the next wr_xaction if there's one available and return 1. Return 0 if
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// there's no xaction available.
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function bit try_get_wr(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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return master_wr_resp_xactions.try_get(xaction);
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end else if (slave_en) begin
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return slave_wr_req_xactions.try_get(xaction);
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end
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endfunction : try_get_wr
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// Get the next wr xaction when it becomes available (wait if necessary), but
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// don't remove it from the receive queue.
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task peek_rd(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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master_rd_resp_xactions.peek(xaction);
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end else if (slave_en) begin
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slave_rd_req_xactions.peek(xaction);
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end
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endtask : peek_rd
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// Get the next wr xaction when it becomes available (wait if necessary), but
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// don't remove it from the receive queue.
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task peek_wr(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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master_wr_resp_xactions.peek(xaction);
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end else if (slave_en) begin
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slave_wr_req_xactions.peek(xaction);
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end
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endtask : peek_wr
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// Get the next rd xaction if there's one available and return 1, but don't
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// remove it from the receive queue. Return 0 if there's no xaction
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// available.
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function bit try_peek_rd(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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return master_rd_resp_xactions.try_peek(xaction);
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end else if (slave_en) begin
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return slave_rd_req_xactions.try_peek(xaction);
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end
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endfunction : try_peek_rd
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// Get the next wr xaction if there's one available and return 1, but don't
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// remove it from the receive queue. Return 0 if there's no xaction
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// available.
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function bit try_peek_wr(output AxiLiteTransaction_t xaction);
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if (master_en) begin
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return master_wr_resp_xactions.try_peek(xaction);
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end else if (slave_en) begin
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return slave_wr_req_xactions.try_peek(xaction);
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end
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endfunction : try_peek_wr
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// Return the number of xactions available in the receive queue
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function int num_rd_pending();
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if (master_en) begin
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return master_rd_resp_xactions.num() +
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master_rd_inflight_xactions.num() +
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master_rd_req_xactions.num();
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end else if (slave_en) begin
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$fatal(1,"Slave AxiLite not yet implemented!");
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end
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endfunction
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function int num_wr_pending();
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if (master_en) begin
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return master_wr_resp_xactions.num() +
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master_wr_inflight_xactions.num() +
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master_wr_req_xactions.num();
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end else if (slave_en) begin
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$fatal(1,"Slave AxiLite not yet implemented!");
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end
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endfunction
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// Create separate processes for driving the master and slave interfaces
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task run();
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fork
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if (master_en) master_body();
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if (slave_en) slave_body();
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join_none
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endtask
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//----------------
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// Master Process
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//----------------
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// wait my_delay clocks - while not reset
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local task master_wait(my_delay);
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repeat(my_delay) begin
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@(posedge master.clk);
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if (master.rst) break;
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end
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endtask
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// stall for a random delay - while not reset
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local task master_stall(int my_stall_prob);
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if ($urandom_range(99) < my_stall_prob) begin
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do begin
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@(posedge master.clk);
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if (master.rst) break;
|
|
end while ($urandom_range(99) < my_stall_prob);
|
|
end
|
|
endtask
|
|
|
|
local task master_body();
|
|
|
|
// start idle
|
|
master.drive_w_idle();
|
|
master.drive_aw_idle();
|
|
master.bready = ready_idle_state;
|
|
|
|
master.drive_read_idle();
|
|
master.rready = ready_idle_state;
|
|
|
|
fork // write_req / write_resp / rd_req / rd_resp
|
|
//--------------------------------------
|
|
begin : write_req_thread
|
|
AxiLiteTransaction_t xaction;
|
|
|
|
forever begin
|
|
// add inter xaction gap
|
|
master_wait(inter_xaction_gap);
|
|
|
|
if (master_wr_req_xactions.try_get(xaction)) begin : req_transaction
|
|
|
|
//drive the write address+data channel
|
|
fork
|
|
begin
|
|
// randomly delay driving
|
|
master_stall(stall_prob);
|
|
master.drive_aw(xaction.addr);
|
|
// wait for ready
|
|
do begin
|
|
@(posedge master.clk);
|
|
if (master.rst) break;
|
|
end while (!master.awready);
|
|
master.drive_aw_idle();
|
|
end
|
|
begin // wait for data ready
|
|
// randomly delay driving
|
|
master_stall(stall_prob);
|
|
master.drive_w(xaction.data,xaction.strb);
|
|
|
|
// push to inflight xactions
|
|
master_wr_inflight_xactions.put(xaction);
|
|
|
|
// wait for ready
|
|
do begin
|
|
@(posedge master.clk);
|
|
if (master.rst) break;
|
|
end while (!master.wready);
|
|
master.drive_w_idle();
|
|
end
|
|
join
|
|
|
|
|
|
end else begin : no_req_transaction
|
|
@(posedge master.clk);
|
|
if (master.rst) continue;
|
|
end : no_req_transaction;
|
|
end //forever
|
|
end : write_req_thread;
|
|
|
|
//--------------------------------------
|
|
begin : write_resp_thread
|
|
AxiLiteTransaction_t xaction;
|
|
|
|
forever begin
|
|
|
|
if (master_wr_inflight_xactions.try_get(xaction)) begin : resp_transaction
|
|
// wait for a little bit of time and assert ready
|
|
if ($urandom_range(99) < 50) begin
|
|
if (master.bready == 0) begin
|
|
// randomly delay ready
|
|
master_stall(stall_prob);
|
|
master.bready = 1;
|
|
end
|
|
master.bready = 1;
|
|
// wait for valid
|
|
do begin
|
|
@(posedge master.clk);
|
|
if (master.rst) break;
|
|
end while (!master.bvalid);
|
|
//wait for valid then wait a bit of time and assert ready
|
|
end else begin
|
|
// wait for valid
|
|
do begin
|
|
@(posedge master.clk);
|
|
if (master.rst) break;
|
|
end while (!master.bvalid);
|
|
|
|
if (master.bready == 0) begin
|
|
// randomly delay ready while valid is true
|
|
master_stall(stall_prob);
|
|
master.bready = 1;
|
|
@(posedge master.clk);
|
|
end
|
|
end
|
|
|
|
|
|
// put the response and clear ready
|
|
master.bready = 0;
|
|
xaction.resp = master.bresp;
|
|
master_wr_resp_xactions.put(xaction);
|
|
// randomly keep ready low for awhile
|
|
master_stall(stall_prob);
|
|
master.bready = ready_idle_state;
|
|
|
|
end else begin : no_resp_transaction
|
|
@(posedge master.clk);
|
|
if (master.rst) continue;
|
|
end
|
|
|
|
end // forever
|
|
end : write_resp_thread;
|
|
|
|
begin : read_req_thread
|
|
AxiLiteTransaction_t xaction;
|
|
|
|
forever begin
|
|
// add inter xaction gap
|
|
master_wait(inter_xaction_gap);
|
|
|
|
if (master_rd_req_xactions.try_get(xaction)) begin : req_transaction
|
|
// randomly delay driving
|
|
master_stall(stall_prob);
|
|
|
|
//drive the read address channel
|
|
master.drive_read(xaction.addr);
|
|
// push to in-flight xactions
|
|
master_rd_inflight_xactions.put(xaction);
|
|
|
|
// wait for read address channel ready
|
|
do begin
|
|
@(posedge master.clk);
|
|
if (master.rst) break;
|
|
end while (!master.arready);
|
|
master.drive_read_idle();
|
|
|
|
|
|
end else begin : no_req_transaction
|
|
@(posedge master.clk);
|
|
if (master.rst) continue;
|
|
end
|
|
end // forever
|
|
end : read_req_thread;
|
|
|
|
//--------------------------------------
|
|
begin : read_resp_thread
|
|
AxiLiteTransaction_t xaction;
|
|
|
|
forever begin
|
|
|
|
if (master_rd_inflight_xactions.try_get(xaction)) begin : resp_transaction
|
|
if ($urandom_range(99) < 50) begin
|
|
if (master.rready == 0) begin
|
|
// randomly delay ready
|
|
master_stall(stall_prob);
|
|
master.rready = 1;
|
|
end
|
|
master.rready = 1;
|
|
// wait for valid
|
|
do begin
|
|
@(posedge master.clk);
|
|
if (master.rst) break;
|
|
end while (!master.rvalid);
|
|
// wait for valid then wait a bit of time and assert ready
|
|
end else begin
|
|
// wait for valid
|
|
do begin
|
|
@(posedge master.clk);
|
|
if (master.rst) break;
|
|
end while (!master.rvalid);
|
|
|
|
if (master.rready == 0) begin
|
|
// randomly delay ready while valid is true
|
|
master_stall(stall_prob);
|
|
master.rready = 1;
|
|
@(posedge master.clk);
|
|
end
|
|
end
|
|
|
|
// put the response and clear ready
|
|
master.rready = 0;
|
|
xaction.data = master.rdata;
|
|
xaction.resp = master.rresp;
|
|
master_rd_resp_xactions.put(xaction);
|
|
// randomly keep ready low for awhile
|
|
master_stall(stall_prob);
|
|
master.rready = ready_idle_state;
|
|
|
|
end else begin : no_resp_transaction
|
|
@(posedge master.clk);
|
|
if (master.rst) continue;
|
|
end
|
|
|
|
end // forever
|
|
end : read_resp_thread;
|
|
|
|
join_none
|
|
endtask : master_body
|
|
|
|
|
|
//---------------
|
|
// Slave Process
|
|
//---------------
|
|
|
|
local task slave_body();
|
|
AxiLiteTransaction_t xaction = new();
|
|
|
|
// start idle
|
|
slave.drive_write_resp_idle();
|
|
slave.awready = 0;
|
|
slave.wready = 0;
|
|
|
|
slave.drive_read_resp_idle();
|
|
slave.arready = 0;
|
|
|
|
forever begin
|
|
@(posedge slave.clk);
|
|
if (slave.rst) continue;
|
|
|
|
// not written!
|
|
$fatal(1,"Slave AxiLite not yet implemented!");
|
|
|
|
end
|
|
endtask : slave_body
|
|
|
|
endclass : AxiLiteBfm
|
|
|
|
|
|
endpackage : PkgAxiLiteBfm
|