Andrew Moch
05eb1bc2f1
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
30 lines
1.1 KiB
Systemverilog
30 lines
1.1 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_constants (Header File)
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//
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// Description:
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// Holds register offsets for the Ethernet Interface
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// NOTE: These depend on the following parameters
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// Parameters:
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// REG_AWIDTH - How wide the register window is in bits
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// BASE - Base address added to the offsets here
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// REGISTER OFFSETS
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// Allocate one full page for MAC
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localparam [REG_AWIDTH-1:0] REG_MAC_LSB = BASE + 'h0000;
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localparam [REG_AWIDTH-1:0] REG_MAC_MSB = BASE + 'h0004;
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// Source IP address
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localparam [REG_AWIDTH-1:0] REG_IP = BASE + 'h1000;
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// Source UDP Port
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localparam [REG_AWIDTH-1:0] REG_UDP = BASE + 'h1004;
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// Registers for Internal/Bridge Network Mode in CPU
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_LSB = BASE + 'h1010;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_MSB = BASE + 'h1014;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_IP = BASE + 'h1018;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_UDP = BASE + 'h101c;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_ENABLE = BASE + 'h1020;
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