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Michael West 45d274746f X300: Make VITA time monotonic 
Make timekeeper tick on every cycle of the radio clock.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: 7886b71f13e9f6e5786c95286ef98f49ab716119
2020-05-12 12:03:31 -05:00
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coregen_dsp
Merge FPGA repository back into UHD repository
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ip
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sim
Merge FPGA repository back into UHD repository
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.gitignore
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build_x300.tcl
Merge FPGA repository back into UHD repository
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bus_int.v
X300: Make VITA time monotonic
2020-05-12 12:03:31 -05:00
capture_ddrlvds.v
Merge FPGA repository back into UHD repository
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dev_config.json
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gen_ddrlvds.v
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Makefile
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Makefile.x300.inc
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nirio_chdr64_adapter.v
rfnoc: Add management filter to generic xport
2020-02-19 13:27:16 -06:00
setupenv.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
soft_ctrl.v
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timing.xdc
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x3x0_base.lvbitx
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x300_1ge.xdc
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x300_10ge_port0.xdc
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x300_10ge_port1.xdc
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x300_10ge.xdc
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x300_aurora.xdc
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2020-01-28 09:35:36 -08:00
x300_core.v
x300: add front-panel GPIO source control
2020-02-18 07:21:24 -06:00
x300_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_eth_interface.v
Merge FPGA repository back into UHD repository
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x300_pcie_int.v
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x300_rfnoc_image_core.v
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x300_rfnoc_image_core.yml
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x300_sfpp_io_core.v
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x300_static_router.hex
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x300_zpu_config.vhd
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x300.v
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x300.xdc
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x310_rfnoc_image_core.v
Merge FPGA repository back into UHD repository
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x310_rfnoc_image_core.yml
Merge FPGA repository back into UHD repository
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x310_static_router.hex
Merge FPGA repository back into UHD repository
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