214 lines
4.5 KiB
Verilog
214 lines
4.5 KiB
Verilog
module b200_tb ();
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wire cat_ce;
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wire cat_miso;
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wire cat_mosi;
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wire cat_sclk;
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wire fx3_ce;
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wire fx3_miso;
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wire fx3_mosi;
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wire fx3_sclk;
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wire pll_ce;
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wire pll_mosi;
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wire pll_sclk;
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// UART
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wire FPGA_RXD0;
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wire FPGA_TXD0;
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// Catalina Controls
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wire codec_enable;
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wire codec_en_agc;
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wire codec_reset;
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wire codec_sync;
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wire codec_txrx;
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wire [3:0] codec_ctrl_in; // These should be outputs
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wire [7:0] codec_ctrl_out; // MUST BE INPUT
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// Catalina Data
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wire codec_data_clk_p; // Clock from CAT (RX)
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wire codec_fb_clk_p; // Clock to CAT (TX)
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wire [11:0] rx_codec_d;
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wire [11:0] tx_codec_d;
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wire rx_frame_p;
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wire tx_frame_p;
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wire cat_clkout_fpga;
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//always on 40MHz clock
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wire codec_main_clk_p;
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wire codec_main_clk_n;
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// Debug Bus
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wire [31:0] debug;
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wire [1:0] debug_clk;
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// GPIF; FX3 Slave FIFO
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wire IFCLK; // pclk
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wire FX3_EXTINT;
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wire GPIF_CTL0; // n_slcs
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wire GPIF_CTL1; // n_slwr
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wire GPIF_CTL2; // n_sloe
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wire GPIF_CTL3; // n_slrd
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wire GPIF_CTL7; // n_pktend
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wire GPIF_CTL4; // slfifo_flags[0]
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wire GPIF_CTL5; // slfifo_flags[1]
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wire GPIF_CTL6; // slfifo_flags[2]
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wire GPIF_CTL8; // slfifo_flags[3]
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wire GPIF_CTL11; // slfifo_addr[1]
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wire GPIF_CTL12; // slfifo_addr[0]
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wire [31:0] GPIF_D;
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wire GPIF_CTL9; // global_reset
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// GPS
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wire gps_lock;
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wire gps_rxd;
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wire gps_txd;
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wire gps_txd_nmea;
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// LEDS
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wire LED_RX1;
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wire LED_RX2;
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wire LED_TXRX1_RX;
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wire LED_TXRX1_TX;
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wire LED_TXRX2_RX;
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wire LED_TXRX2_TX;
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// Misc Hardware Control
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wire ref_sel;
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wire pll_lock;
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wire FPGA_CFG_CS; // Driven by FX3 gpio.
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wire AUX_PWR_ON; // Driven by FX3 gpio.
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// PPS
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wire PPS_IN_EXT;
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wire PPS_IN_INT;
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// RF Hardware Control
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wire SFDX1_RX;
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wire SFDX1_TX;
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wire SFDX2_RX;
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wire SFDX2_TX;
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wire SRX1_RX;
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wire SRX1_TX;
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wire SRX2_RX;
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wire SRX2_TX;
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wire tx_bandsel_a;
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wire tx_bandsel_b;
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wire tx_enable1;
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wire tx_enable2;
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wire rx_bandsel_a;
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wire rx_bandsel_b;
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wire rx_bandsel_c;
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b200 b200_i1(
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// SPI Interfaces
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.cat_ce(),
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.cat_miso(),
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.cat_mosi(),
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.cat_sclk(),
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.fx3_ce(),
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.fx3_miso(),
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.fx3_mosi(),
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.fx3_sclk(),
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.pll_ce(),
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.pll_mosi(),
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.pll_sclk(),
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// UART
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.FPGA_RXD0(),
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.FPGA_TXD0(),
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// Catalina Controls
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.codec_enable(),
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.codec_en_agc(),
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.codec_reset(),
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.codec_sync(),
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.codec_txrx(),
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.codec_ctrl_in(), // These should be outputs
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.codec_ctrl_out(), // MUST BE INPUT
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// Catalina Data
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.codec_data_clk_p(), // Clock from CAT (RX)
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.codec_fb_clk_p(), // Clock to CAT (TX)
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.rx_codec_d(),
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.tx_codec_d(),
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.rx_frame_p(),
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.tx_frame_p(),
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.cat_clkout_fpga(),
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//always on 40MHz clock
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.codec_main_clk_p(),
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.codec_main_clk_n(),
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// Debug Bus
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.debug(),
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.debug_clk(),
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// GPIF, FX3 Slave FIFO
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.IFCLK(), // pclk
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.FX3_EXTINT(),
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.GPIF_CTL0(), // n_slcs
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.GPIF_CTL1(), // n_slwr
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.GPIF_CTL2(), // n_sloe
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.GPIF_CTL3(), // n_slrd
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.GPIF_CTL7(), // n_pktend
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.GPIF_CTL4(), // slfifo_flags[0]
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.GPIF_CTL5(), // slfifo_flags[1]
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.GPIF_CTL6(), // slfifo_flags[2]
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.GPIF_CTL8(), // slfifo_flags[3]
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.GPIF_CTL11(), // slfifo_addr[1]
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.GPIF_CTL12(), // slfifo_addr[0]
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.GPIF_D(),
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.GPIF_CTL9(), // global_reset
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// GPS
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.gps_lock(),
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.gps_rxd(),
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.gps_txd(),
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.gps_txd_nmea(),
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// LEDS
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.LED_RX1(),
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.LED_RX2(),
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.LED_TXRX1_RX(),
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.LED_TXRX1_TX(),
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.LED_TXRX2_RX(),
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.LED_TXRX2_TX(),
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// Misc Hardware Control
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.ref_sel(),
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.pll_lock(),
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.FPGA_CFG_CS(), // Driven by FX3 gpio.
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.AUX_PWR_ON(), // Driven by FX3 gpio.
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// PPS
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.PPS_IN_EXT(),
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.PPS_IN_INT(),
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// RF Hardware Control
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.SFDX1_RX(),
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.SFDX1_TX(),
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.SFDX2_RX(),
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.SFDX2_TX(),
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.SRX1_RX(),
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.SRX1_TX(),
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.SRX2_RX(),
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.SRX2_TX(),
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.tx_bandsel_a(),
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.tx_bandsel_b(),
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.tx_enable1(),
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.tx_enable2(),
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.rx_bandsel_a(),
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.rx_bandsel_b(),
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.rx_bandsel_c()
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);
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endmodule // b200_tb
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