260 lines
6.6 KiB
Verilog
260 lines
6.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module simple_gemac_tx
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(input clk125, input reset,
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output GMII_GTX_CLK, output reg GMII_TX_EN, output reg GMII_TX_ER, output reg [7:0] GMII_TXD,
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output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack,
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input [7:0] ifg, input [47:0] mac_addr,
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input pause_req, input [15:0] pause_time,
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input pause_apply, output reg paused
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);
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reg tx_en_pre, tx_er_pre;
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reg [7:0] txd_pre;
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assign GMII_GTX_CLK = clk125;
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assign tx_clk = clk125;
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reg [7:0] tx_state;
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reg [7:0] ifg_ctr;
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reg [15:0] frame_len_ctr;
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reg [7:0] pause_ctr, pause_dat;
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wire in_ifg = (ifg_ctr != 0);
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wire [31:0] crc_out;
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localparam TX_IDLE = 0;
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localparam TX_PREAMBLE = 1;
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localparam TX_SOF_DEL = TX_PREAMBLE + 7;
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localparam TX_FIRSTBYTE = TX_SOF_DEL + 1;
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localparam TX_IN_FRAME = TX_FIRSTBYTE + 1;
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localparam TX_IN_FRAME_2 = TX_IN_FRAME + 1;
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localparam TX_PAD = TX_IN_FRAME_2 + 1;
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localparam TX_CRC_0 = 16;
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localparam TX_CRC_1 = TX_CRC_0 + 1;
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localparam TX_CRC_2 = TX_CRC_0 + 2;
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localparam TX_CRC_3 = TX_CRC_0 + 3;
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localparam TX_ERROR = 32;
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localparam TX_PAUSE = 55;
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localparam TX_PAUSE_SOF = TX_PAUSE + 7;
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localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1;
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localparam TX_PAUSE_END = TX_PAUSE_SOF + 18;
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localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes preamble but not CRC
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localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we want to handle?
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always @(posedge tx_clk)
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if(reset |(tx_state == TX_IDLE))
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frame_len_ctr <= 0;
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else
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frame_len_ctr <= frame_len_ctr + 1;
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reg send_pause;
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reg [15:0] pause_time_held;
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always @(posedge tx_clk)
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if(reset)
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send_pause <= 0;
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else if(pause_req)
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send_pause <= 1;
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else if(tx_state == TX_PAUSE)
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send_pause <= 0;
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always @(posedge tx_clk)
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if(pause_req)
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pause_time_held <= pause_time;
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always @(posedge tx_clk)
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if(reset)
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tx_state <= TX_IDLE;
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else
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case(tx_state)
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TX_IDLE :
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if(~in_ifg)
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if(send_pause)
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tx_state <= TX_PAUSE;
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else if(tx_valid & ~pause_apply)
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tx_state <= TX_PREAMBLE;
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TX_FIRSTBYTE :
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if(tx_error)
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tx_state <= TX_ERROR; // underrun
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else if(~tx_valid)
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tx_state <= TX_PAD;
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else
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tx_state <= TX_IN_FRAME;
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TX_IN_FRAME :
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if(tx_error)
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tx_state <= TX_ERROR; // underrun
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else if(~tx_valid)
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tx_state <= TX_PAD;
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else if(frame_len_ctr == MIN_FRAME_LEN - 1)
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tx_state <= TX_IN_FRAME_2;
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TX_IN_FRAME_2 :
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if(tx_error)
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tx_state <= TX_ERROR; // underrun
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else if(~tx_valid)
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tx_state <= TX_CRC_0;
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TX_PAD :
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if(frame_len_ctr == MIN_FRAME_LEN)
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tx_state <= TX_CRC_0;
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TX_CRC_3 :
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tx_state <= TX_IDLE;
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TX_ERROR :
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tx_state <= TX_IDLE;
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TX_PAUSE_END :
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tx_state <= TX_PAD;
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default :
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tx_state <= tx_state + 1;
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endcase // case (tx_state)
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always @(posedge tx_clk)
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if(reset)
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begin
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tx_en_pre <= 0;
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tx_er_pre <= 0;
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txd_pre <= 0;
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end
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else
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casex(tx_state)
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TX_IDLE :
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begin
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tx_en_pre <= 0;
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tx_er_pre <= 0;
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txd_pre <= 0;
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end
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TX_PREAMBLE, TX_PAUSE :
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begin
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txd_pre <= 8'h55;
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tx_en_pre <= 1;
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end
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TX_SOF_DEL, TX_PAUSE_SOF :
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txd_pre <= 8'hD5;
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TX_FIRSTBYTE, TX_IN_FRAME, TX_IN_FRAME_2 :
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txd_pre <= tx_valid ? tx_data : 0;
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TX_ERROR :
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begin
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tx_er_pre <= 1;
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txd_pre <= 0;
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end
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TX_CRC_3 :
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tx_en_pre <= 0;
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TX_PAD :
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txd_pre <= 0;
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TX_PAUSE_FIRST, 8'b01xx_xxxx : // In Pause Frame
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txd_pre <= pause_dat;
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endcase // case (tx_state)
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localparam SGE_FLOW_CTRL_ADDR = 48'h01_80_C2_00_00_01;
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always @(posedge tx_clk)
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case(tx_state)
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TX_PAUSE_SOF :
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pause_dat <= SGE_FLOW_CTRL_ADDR[47:40]; // Note everything must be 1 cycle early
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TX_PAUSE_SOF + 1:
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pause_dat <= SGE_FLOW_CTRL_ADDR[39:32];
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TX_PAUSE_SOF + 2:
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pause_dat <= SGE_FLOW_CTRL_ADDR[31:24];
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TX_PAUSE_SOF + 3:
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pause_dat <= SGE_FLOW_CTRL_ADDR[23:16];
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TX_PAUSE_SOF + 4:
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pause_dat <= SGE_FLOW_CTRL_ADDR[15:8];
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TX_PAUSE_SOF + 5:
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pause_dat <= SGE_FLOW_CTRL_ADDR[7:0];
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TX_PAUSE_SOF + 6:
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pause_dat <= mac_addr[47:40];
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TX_PAUSE_SOF + 7:
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pause_dat <= mac_addr[39:32];
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TX_PAUSE_SOF + 8:
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pause_dat <= mac_addr[31:24];
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TX_PAUSE_SOF + 9:
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pause_dat <= mac_addr[23:16];
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TX_PAUSE_SOF + 10:
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pause_dat <= mac_addr[15:8];
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TX_PAUSE_SOF + 11:
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pause_dat <= mac_addr[7:0];
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TX_PAUSE_SOF + 12:
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pause_dat <= 8'h88; // Type = 8808 = MAC ctrl frame
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TX_PAUSE_SOF + 13:
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pause_dat <= 8'h08;
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TX_PAUSE_SOF + 14:
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pause_dat <= 8'h00; // Opcode = 0001 = PAUSE
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TX_PAUSE_SOF + 15:
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pause_dat <= 8'h01;
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TX_PAUSE_SOF + 16:
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pause_dat <= pause_time_held[15:8];
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TX_PAUSE_SOF + 17:
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pause_dat <= pause_time_held[7:0];
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endcase // case (tx_state)
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wire start_ifg = (tx_state == TX_CRC_3);
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always @(posedge tx_clk)
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if(reset)
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ifg_ctr <= 100;
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else if(start_ifg)
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ifg_ctr <= ifg;
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else if(ifg_ctr != 0)
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ifg_ctr <= ifg_ctr - 1;
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wire clear_crc = (tx_state == TX_IDLE);
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wire calc_crc =
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(tx_state==TX_IN_FRAME) |
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(tx_state==TX_IN_FRAME_2) |
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(tx_state==TX_PAD) |
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(tx_state[6]);
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crc crc(.clk(tx_clk), .reset(reset), .clear(clear_crc),
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.data(txd_pre), .calc(calc_crc), .crc_out(crc_out));
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assign tx_ack = (tx_state == TX_FIRSTBYTE);
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always @(posedge tx_clk)
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begin
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GMII_TX_EN <= tx_en_pre;
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GMII_TX_ER <= tx_er_pre;
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case(tx_state)
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TX_CRC_0 :
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GMII_TXD <= crc_out[31:24];
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TX_CRC_1 :
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GMII_TXD <= crc_out[23:16];
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TX_CRC_2 :
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GMII_TXD <= crc_out[15:8];
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TX_CRC_3 :
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GMII_TXD <= crc_out[7:0];
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default :
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GMII_TXD <= txd_pre;
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endcase // case (tx_state)
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end
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// report that we are paused only when we get back to IDLE
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always @(posedge tx_clk)
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if(reset)
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paused <= 0;
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else if(~pause_apply)
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paused <= 0;
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else if(tx_state == TX_IDLE)
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paused <= 1;
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endmodule // simple_gemac_tx
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// Testing code
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/*
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reg [7:0] crc_ctr;
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reg calc_crc_d1;
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always @(posedge tx_clk)
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calc_crc_d1 <= calc_crc;
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always @(posedge tx_clk)
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if(reset)
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crc_ctr <= 0;
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else if(calc_crc)
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crc_ctr <= crc_ctr+1;
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else if(calc_crc_d1)
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$display("CRC COUNT = %d",crc_ctr);
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else
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crc_ctr <= 0;
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*/
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