72 lines
3.0 KiB
Verilog
72 lines
3.0 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module crc
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(input clk,
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input reset,
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input clear,
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input [7:0] data,
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input calc,
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output [31:0] crc_out,
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output match);
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function[31:0] NextCRC;
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input[7:0] D;
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input[31:0] C;
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reg[31:0] NewCRC;
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begin
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NewCRC[0] = C[24]^C[30]^D[1]^D[7];
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NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
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NewCRC[5] = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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NewCRC[6] = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
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NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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NewCRC[12] = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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NewCRC[13] = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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NewCRC[14] = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
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NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
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NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
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NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
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NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
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NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4];
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NewCRC[20] = C[12]^C[28]^D[3];
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NewCRC[21] = C[13]^C[29]^D[2];
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NewCRC[22] = C[14]^C[24]^D[7];
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NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5];
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NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
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NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
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NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
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NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
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NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3];
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NewCRC[31] = C[23]^C[29]^D[2];
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NextCRC = NewCRC;
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end
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endfunction
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reg [31:0] crc_reg;
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always @ (posedge clk)
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if (reset | clear)
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crc_reg <= 32'hffffffff;
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else if (calc)
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crc_reg <= NextCRC(data,crc_reg);
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assign crc_out = ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31],
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crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23],
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crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15],
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crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7] };
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assign match = (crc_reg == 32'hc704_dd7b);
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endmodule // crc
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