59 lines
1.6 KiB
Verilog
59 lines
1.6 KiB
Verilog
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initial $dumpfile("axi_crossbar_tb.vcd");
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initial $dumpvars(0,axi_crossbar_tb);
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reg [15:0] x;
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initial
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begin
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@(posedge clk);
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reset <= 1;
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repeat (5) @(posedge clk);
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@(posedge clk);
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reset <= 0;
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@(posedge clk);
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// 2x2 Switch so only mask one bit of SID for route dest.
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// Each slave must have a unique address, logic doesn't check for this.
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//
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// Network Addr 0 & 1 go to Slave 0.
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write_setting_bus(0,0); // 0.X goes to Port 0
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write_setting_bus(1,0); // 1.X goes to Port 0
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// Local Addr = 2
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write_setting_bus(512,2);
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// Host Addr 0 & 2 go to Slave 0...
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write_setting_bus(256,0); // 2.0 goes to Port 0
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write_setting_bus(258,0); // 2.2 goes to Port 0
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// ...Host Addr 1 & 3 go to Slave 1...
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write_setting_bus(257,1); // 2.1 goes to Port 1
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write_setting_bus(259,1); // 2.3 goes to Port 1
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//
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@(posedge clk);
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fork
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begin
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// Master0, addr 0.0 to Slave0
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enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0});
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// Master0, addr 2.0 to Slave0
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enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0});
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// Master0, addr 2.3 to Slave1
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enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3});
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// Master0, addr 2.2 to Slave0
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enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2});
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end
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begin
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// Master1, addr 1.0 to Slave0
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enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0});
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// Master1, addr 2.1 to Slave1
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enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1});
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// Master1, addr 2.3 to Slave1
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enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3});
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end
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join
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repeat (1000) @(posedge clk);
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$finish;
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end // initial begin
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